2c91dc1bcd
This includes support for the CXL commands, and adds the following packages: cxl-cli, cxl-devel, cxl-libs. Resolves: rhbz#2132167
170 lines
5.7 KiB
Diff
170 lines
5.7 KiB
Diff
From eef9685245d172a80e9a5dfd830942824e7d40b4 Mon Sep 17 00:00:00 2001
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From: Dan Williams <dan.j.williams@intel.com>
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Date: Thu, 14 Jul 2022 10:02:55 -0700
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Subject: [PATCH 186/217] cxl/test: Checkout region setup/teardown
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Exercise the fundamental region provisioning sysfs mechanisms of discovering
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available DPA capacity, allocating DPA to a region, and programming HDM
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decoders.
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Link: https://lore.kernel.org/r/165781817516.1555691.3557156570639615515.stgit@dwillia2-xfh.jf.intel.com
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Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
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---
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test/cxl-region-sysfs.sh | 122 +++++++++++++++++++++++++++++++++++++++
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test/meson.build | 2 +
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2 files changed, 124 insertions(+)
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create mode 100644 test/cxl-region-sysfs.sh
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diff --git a/test/cxl-region-sysfs.sh b/test/cxl-region-sysfs.sh
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new file mode 100644
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index 0000000..2582edb
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--- /dev/null
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+++ b/test/cxl-region-sysfs.sh
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@@ -0,0 +1,122 @@
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+#!/bin/bash
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+# SPDX-License-Identifier: GPL-2.0
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+# Copyright (C) 2022 Intel Corporation. All rights reserved.
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+
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+. $(dirname $0)/common
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+
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+rc=1
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+
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+set -ex
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+
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+trap 'err $LINENO' ERR
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+
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+check_prereq "jq"
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+
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+modprobe -r cxl_test
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+modprobe cxl_test
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+udevadm settle
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+
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+# THEORY OF OPERATION: Create a x8 interleave across the pmem capacity
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+# of the 8 endpoints defined by cxl_test, commit the decoders (which
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+# just stubs out the actual hardware programming aspect, but updates the
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+# driver state), and then tear it all down again. As with other cxl_test
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+# tests if the CXL topology in tools/testing/cxl/test/cxl.c ever changes
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+# then the paired update must be made to this test.
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+
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+# find the root decoder that spans both test host-bridges and support pmem
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+decoder=$($CXL list -b cxl_test -D -d root | jq -r ".[] |
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+ select(.pmem_capable == true) |
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+ select(.nr_targets == 2) |
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+ .decoder")
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+
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+# find the memdevs mapped by that decoder
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+readarray -t mem < <($CXL list -M -d $decoder | jq -r ".[].memdev")
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+
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+# ask cxl reserve-dpa to allocate pmem capacity from each of those memdevs
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+readarray -t endpoint < <($CXL reserve-dpa -t pmem ${mem[*]} -s $((256<<20)) |
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+ jq -r ".[] | .decoder.decoder")
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+
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+# instantiate an empty region
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+region=$(cat /sys/bus/cxl/devices/$decoder/create_pmem_region)
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+echo $region > /sys/bus/cxl/devices/$decoder/create_pmem_region
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+uuidgen > /sys/bus/cxl/devices/$region/uuid
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+
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+# setup interleave geometry
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+nr_targets=${#endpoint[@]}
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+echo $nr_targets > /sys/bus/cxl/devices/$region/interleave_ways
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+g=$(cat /sys/bus/cxl/devices/$decoder/interleave_granularity)
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+echo $g > /sys/bus/cxl/devices/$region/interleave_granularity
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+echo $((nr_targets * (256<<20))) > /sys/bus/cxl/devices/$region/size
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+
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+# grab the list of memdevs grouped by host-bridge interleave position
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+port_dev0=$($CXL list -T -d $decoder | jq -r ".[] |
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+ .targets | .[] | select(.position == 0) | .target")
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+port_dev1=$($CXL list -T -d $decoder | jq -r ".[] |
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+ .targets | .[] | select(.position == 1) | .target")
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+readarray -t mem_sort0 < <($CXL list -M -p $port_dev0 | jq -r ".[] | .memdev")
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+readarray -t mem_sort1 < <($CXL list -M -p $port_dev1 | jq -r ".[] | .memdev")
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+
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+# TODO: add a cxl list option to list memdevs in valid region provisioning
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+# order, hardcode for now.
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+mem_sort=()
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+mem_sort[0]=${mem_sort0[0]}
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+mem_sort[1]=${mem_sort1[0]}
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+mem_sort[2]=${mem_sort0[2]}
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+mem_sort[3]=${mem_sort1[2]}
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+mem_sort[4]=${mem_sort0[1]}
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+mem_sort[5]=${mem_sort1[1]}
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+mem_sort[6]=${mem_sort0[3]}
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+mem_sort[7]=${mem_sort1[3]}
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+
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+# TODO: use this alternative memdev ordering to validate a negative test for
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+# specifying invalid positions of memdevs
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+#mem_sort[2]=${mem_sort0[0]}
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+#mem_sort[1]=${mem_sort1[0]}
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+#mem_sort[0]=${mem_sort0[2]}
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+#mem_sort[3]=${mem_sort1[2]}
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+#mem_sort[4]=${mem_sort0[1]}
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+#mem_sort[5]=${mem_sort1[1]}
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+#mem_sort[6]=${mem_sort0[3]}
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+#mem_sort[7]=${mem_sort1[3]}
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+
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+# re-generate the list of endpoint decoders in region position programming order
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+endpoint=()
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+for i in ${mem_sort[@]}
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+do
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+ readarray -O ${#endpoint[@]} -t endpoint < <($CXL list -Di -d endpoint -m $i | jq -r ".[] |
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+ select(.mode == \"pmem\") | .decoder")
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+done
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+
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+# attach all endpoint decoders to the region
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+pos=0
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+for i in ${endpoint[@]}
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+do
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+ echo $i > /sys/bus/cxl/devices/$region/target$pos
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+ pos=$((pos+1))
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+done
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+echo "$region added ${#endpoint[@]} targets: ${endpoint[@]}"
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+
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+# walk up the topology and commit all decoders
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+echo 1 > /sys/bus/cxl/devices/$region/commit
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+
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+# walk down the topology and de-commit all decoders
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+echo 0 > /sys/bus/cxl/devices/$region/commit
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+
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+# remove endpoints from the region
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+pos=0
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+for i in ${endpoint[@]}
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+do
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+ echo "" > /sys/bus/cxl/devices/$region/target$pos
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+ pos=$((pos+1))
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+done
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+
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+# release DPA capacity
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+readarray -t endpoint < <($CXL free-dpa -t pmem ${mem[*]} |
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+ jq -r ".[] | .decoder.decoder")
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+echo "$region released ${#endpoint[@]} targets: ${endpoint[@]}"
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+
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+# validate no WARN or lockdep report during the run
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+log=$(journalctl -r -k --since "-$((SECONDS+1))s")
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+grep -q "Call Trace" <<< $log && err "$LINENO"
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+
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+modprobe -r cxl_test
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diff --git a/test/meson.build b/test/meson.build
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index 210dcb0..3203d9c 100644
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--- a/test/meson.build
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+++ b/test/meson.build
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@@ -151,6 +151,7 @@ max_extent = find_program('max_available_extent_ns.sh')
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pfn_meta_errors = find_program('pfn-meta-errors.sh')
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track_uuid = find_program('track-uuid.sh')
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cxl_topo = find_program('cxl-topology.sh')
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+cxl_sysfs = find_program('cxl-region-sysfs.sh')
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tests = [
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[ 'libndctl', libndctl, 'ndctl' ],
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@@ -176,6 +177,7 @@ tests = [
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[ 'pfn-meta-errors.sh', pfn_meta_errors, 'ndctl' ],
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[ 'track-uuid.sh', track_uuid, 'ndctl' ],
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[ 'cxl-topology.sh', cxl_topo, 'cxl' ],
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+ [ 'cxl-region-sysfs.sh', cxl_sysfs, 'cxl' ],
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]
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if get_option('destructive').enabled()
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--
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2.27.0
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