2c91dc1bcd
This includes support for the CXL commands, and adds the following packages: cxl-cli, cxl-devel, cxl-libs. Resolves: rhbz#2132167
458 lines
14 KiB
Diff
458 lines
14 KiB
Diff
From d87cee2dd4756f7e067bdadc78a0632dd666cc64 Mon Sep 17 00:00:00 2001
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From: Dan Williams <dan.j.williams@intel.com>
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Date: Sun, 23 Jan 2022 16:54:44 -0800
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Subject: [PATCH 119/217] cxl/list: Reuse the --target option for ports
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It is useful to be able to dump the dport-id to host-device-name. Rather
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than introduce a new option, just interpret --target as "list dports" for
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port objects.
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$ cxl list -BTu -b ACPI.CXL
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{
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"bus":"root0",
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"provider":"ACPI.CXL",
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"nr_dports":1,
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"dports":[
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{
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"dport":"ACPI0016:00",
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"alias":"pci0000:34",
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"id":"0"
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}
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]
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}
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Link: https://lore.kernel.org/r/164298568481.3021641.4632086646702812643.stgit@dwillia2-desk3.amr.corp.intel.com
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Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
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---
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.clang-format | 1 +
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Documentation/cxl/cxl-list.txt | 18 ++++-
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Documentation/cxl/lib/libcxl.txt | 27 ++++++++
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cxl/json.c | 56 +++++++++++++++-
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cxl/lib/libcxl.c | 109 ++++++++++++++++++++++++++++++-
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cxl/lib/libcxl.sym | 7 ++
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cxl/lib/private.h | 13 ++++
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cxl/libcxl.h | 12 ++++
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cxl/list.c | 2 +-
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9 files changed, 240 insertions(+), 5 deletions(-)
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diff --git a/.clang-format b/.clang-format
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index 47fb657..c753487 100644
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--- a/.clang-format
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+++ b/.clang-format
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@@ -82,6 +82,7 @@ ForEachMacros:
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- 'cxl_port_foreach'
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- 'cxl_decoder_foreach'
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- 'cxl_target_foreach'
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+ - 'cxl_dport_foreach'
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- 'cxl_endpoint_foreach'
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- 'daxctl_dev_foreach'
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- 'daxctl_mapping_foreach'
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diff --git a/Documentation/cxl/cxl-list.txt b/Documentation/cxl/cxl-list.txt
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index 20ff2cb..e1299d9 100644
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--- a/Documentation/cxl/cxl-list.txt
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+++ b/Documentation/cxl/cxl-list.txt
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@@ -272,7 +272,23 @@ OPTIONS
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-T::
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--targets::
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- Extend decoder listings with downstream port target information.
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+ Extend decoder listings with downstream port target information, and /
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+ or port and bus listings with the downstream port information.
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+----
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+# cxl list -BTu -b ACPI.CXL
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+{
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+ "bus":"root0",
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+ "provider":"ACPI.CXL",
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+ "nr_dports":1,
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+ "dports":[
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+ {
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+ "dport":"ACPI0016:00",
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+ "alias":"pci0000:34",
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+ "id":"0"
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+ }
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+ ]
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+}
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+----
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--debug::
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If the cxl tool was built with debug enabled, turn on debug
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diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt
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index a68a58b..2e8570d 100644
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--- a/Documentation/cxl/lib/libcxl.txt
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+++ b/Documentation/cxl/lib/libcxl.txt
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@@ -245,6 +245,7 @@ bool cxl_port_is_root(struct cxl_port *port);
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bool cxl_port_is_switch(struct cxl_port *port);
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bool cxl_port_is_endpoint(struct cxl_port *port);
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bool cxl_port_hosts_memdev(struct cxl_port *port, struct cxl_memdev *memdev);
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+int cxl_port_get_nr_dports(struct cxl_port *port);
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----
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The port type is communicated via cxl_port_is_<type>(). An 'enabled' port
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is one that has succeeded in discovering the CXL component registers in
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@@ -256,6 +257,32 @@ of intervening switch ports, and a terminal endpoint port.
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cxl_port_hosts_memdev() returns true if the port's host appears in the
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memdev host's device topology ancestry.
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+==== DPORTS
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+A CXL dport object represents a CXL / PCIe Switch Downstream Port, or a
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+CXL / PCIe host bridge.
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+
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+===== DPORT: Enumeration
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+----
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+struct cxl_dport *cxl_dport_get_first(struct cxl_port *port);
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+struct cxl_dport *cxl_dport_get_next(struct cxl_dport *dport);
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+
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+#define cxl_dport_foreach(port, dport) \
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+ for (dport = cxl_dport_get_first(port); dport != NULL; \
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+ dport = cxl_dport_get_next(dport))
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+
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+----
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+
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+===== DPORT: Attributes
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+----
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+const char *cxl_dport_get_devname(struct cxl_dport *dport);
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+const char *cxl_dport_get_physical_node(struct cxl_dport *dport);
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+int cxl_dport_get_id(struct cxl_dport *dport);
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+----
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+The id of a dport is the hardware idenfifier used by an upstream port to
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+reference a downstream port. The physical node of a dport is only
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+available for platform firmware defined downstream ports and alias the
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+companion object, like a PCI host bridge, in the PCI device hierarchy.
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+
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ENDPOINTS
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---------
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CXL endpoint objects encapsulate the set of host-managed device-memory
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diff --git a/cxl/json.c b/cxl/json.c
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index d81aed8..4fb5eec 100644
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--- a/cxl/json.c
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+++ b/cxl/json.c
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@@ -241,6 +241,58 @@ struct json_object *util_cxl_memdev_to_json(struct cxl_memdev *memdev,
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return jdev;
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}
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+static struct json_object *util_cxl_dports_to_json(struct json_object *jport,
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+ struct cxl_port *port,
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+ unsigned long flags)
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+{
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+ struct json_object *jobj, *jdports;
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+ struct cxl_dport *dport;
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+ int val;
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+
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+ val = cxl_port_get_nr_dports(port);
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+ if (!val || !(flags & UTIL_JSON_TARGETS))
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+ return jport;
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+
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+ jobj = json_object_new_int(val);
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+ if (jobj)
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+ json_object_object_add(jport, "nr_dports", jobj);
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+
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+ jdports = json_object_new_array();
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+ if (!jdports)
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+ return jport;
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+
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+ cxl_dport_foreach(port, dport) {
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+ struct json_object *jdport;
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+ const char *phys_node;
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+
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+ jdport = json_object_new_object();
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+ if (!jdport)
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+ continue;
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+
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+ jobj = json_object_new_string(cxl_dport_get_devname(dport));
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+ if (jobj)
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+ json_object_object_add(jdport, "dport", jobj);
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+
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+ phys_node = cxl_dport_get_physical_node(dport);
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+ if (phys_node) {
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+ jobj = json_object_new_string(phys_node);
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+ if (jobj)
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+ json_object_object_add(jdport, "alias", jobj);
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+ }
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+
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+ val = cxl_dport_get_id(dport);
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+ jobj = util_json_object_hex(val, flags);
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+ if (jobj)
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+ json_object_object_add(jdport, "id", jobj);
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+
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+ json_object_array_add(jdports, jdport);
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+ }
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+
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+ json_object_object_add(jport, "dports", jdports);
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+
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+ return jport;
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+}
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+
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struct json_object *util_cxl_bus_to_json(struct cxl_bus *bus,
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unsigned long flags)
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{
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@@ -259,7 +311,7 @@ struct json_object *util_cxl_bus_to_json(struct cxl_bus *bus,
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if (jobj)
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json_object_object_add(jbus, "provider", jobj);
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- return jbus;
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+ return util_cxl_dports_to_json(jbus, cxl_bus_get_port(bus), flags);
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}
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struct json_object *util_cxl_decoder_to_json(struct cxl_decoder *decoder,
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@@ -403,7 +455,7 @@ static struct json_object *__util_cxl_port_to_json(struct cxl_port *port,
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json_object_object_add(jport, "state", jobj);
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}
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- return jport;
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+ return util_cxl_dports_to_json(jport, port, flags);
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}
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struct json_object *util_cxl_port_to_json(struct cxl_port *port,
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diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c
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index 7bf7949..d7a3f10 100644
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--- a/cxl/lib/libcxl.c
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+++ b/cxl/lib/libcxl.c
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@@ -89,13 +89,24 @@ static void free_decoder(struct cxl_decoder *decoder, struct list_head *head)
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free(decoder);
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}
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+static void free_dport(struct cxl_dport *dport, struct list_head *head)
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+{
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+ if (head)
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+ list_del_from(head, &dport->list);
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+ free(dport->dev_buf);
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+ free(dport->dev_path);
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+ free(dport->phys_path);
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+ free(dport);
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+}
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+
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static void free_port(struct cxl_port *port, struct list_head *head);
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static void free_endpoint(struct cxl_endpoint *endpoint, struct list_head *head);
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static void __free_port(struct cxl_port *port, struct list_head *head)
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{
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- struct cxl_port *child, *_c;
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struct cxl_endpoint *endpoint, *_e;
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struct cxl_decoder *decoder, *_d;
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+ struct cxl_dport *dport, *_dp;
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+ struct cxl_port *child, *_c;
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if (head)
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list_del_from(head, &port->list);
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@@ -105,6 +116,8 @@ static void __free_port(struct cxl_port *port, struct list_head *head)
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free_endpoint(endpoint, &port->endpoints);
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list_for_each_safe(&port->decoders, decoder, _d, list)
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free_decoder(decoder, &port->decoders);
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+ list_for_each_safe(&port->dports, dport, _dp, list)
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+ free_dport(dport , &port->dports);
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kmod_module_unref(port->module);
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free(port->dev_buf);
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free(port->dev_path);
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@@ -701,6 +714,7 @@ static int cxl_port_init(struct cxl_port *port, struct cxl_port *parent_port,
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list_head_init(&port->child_ports);
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list_head_init(&port->endpoints);
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list_head_init(&port->decoders);
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+ list_head_init(&port->dports);
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port->dev_path = strdup(cxlport_base);
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if (!port->dev_path)
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@@ -1332,6 +1346,99 @@ CXL_EXPORT struct cxl_bus *cxl_port_to_bus(struct cxl_port *port)
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return container_of(port, struct cxl_bus, port);
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}
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+static void *add_cxl_dport(void *parent, int id, const char *cxldport_base)
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+{
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+ const char *devname = devpath_to_devname(cxldport_base);
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+ struct cxl_dport *dport, *dport_dup;
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+ struct cxl_port *port = parent;
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+ struct cxl_ctx *ctx = cxl_port_get_ctx(port);
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+
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+ dbg(ctx, "%s: base: \'%s\'\n", devname, cxldport_base);
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+
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+ dport = calloc(1, sizeof(*dport));
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+ if (!dport)
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+ return NULL;
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+
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+ dport->id = id;
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+ dport->port = port;
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+
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+ dport->dev_path = realpath(cxldport_base, NULL);
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+ if (!dport->dev_path)
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+ goto err;
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+
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+ dport->dev_buf = calloc(1, strlen(cxldport_base) + 50);
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+ if (!dport->dev_buf)
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+ goto err;
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+ dport->buf_len = strlen(cxldport_base) + 50;
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+
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+ sprintf(dport->dev_buf, "%s/physical_node", cxldport_base);
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+ dport->phys_path = realpath(dport->dev_buf, NULL);
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+
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+ cxl_dport_foreach(port, dport_dup)
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+ if (dport_dup->id == dport->id) {
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+ free_dport(dport, NULL);
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+ return dport_dup;
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+ }
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+
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+ port->nr_dports++;
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+ list_add(&port->dports, &dport->list);
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+ return dport;
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+
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+err:
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+ free_dport(dport, NULL);
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+ return NULL;
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+}
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+
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+static void cxl_dports_init(struct cxl_port *port)
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+{
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+ struct cxl_ctx *ctx = cxl_port_get_ctx(port);
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+
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+ if (port->dports_init)
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+ return;
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+
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+ port->dports_init = 1;
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+
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+ sysfs_device_parse(ctx, port->dev_path, "dport", port, add_cxl_dport);
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+}
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+
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+CXL_EXPORT int cxl_port_get_nr_dports(struct cxl_port *port)
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+{
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+ if (!port->dports_init)
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+ cxl_dports_init(port);
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+ return port->nr_dports;
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+}
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+
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+CXL_EXPORT struct cxl_dport *cxl_dport_get_first(struct cxl_port *port)
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+{
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+ cxl_dports_init(port);
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+
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+ return list_top(&port->dports, struct cxl_dport, list);
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+}
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+
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+CXL_EXPORT struct cxl_dport *cxl_dport_get_next(struct cxl_dport *dport)
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+{
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+ struct cxl_port *port = dport->port;
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+
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+ return list_next(&port->dports, dport, list);
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+}
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+
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+CXL_EXPORT const char *cxl_dport_get_devname(struct cxl_dport *dport)
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+{
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+ return devpath_to_devname(dport->dev_path);
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+}
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+
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+CXL_EXPORT const char *cxl_dport_get_physical_node(struct cxl_dport *dport)
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+{
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+ if (!dport->phys_path)
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+ return NULL;
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+ return devpath_to_devname(dport->phys_path);
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+}
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+
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+CXL_EXPORT int cxl_dport_get_id(struct cxl_dport *dport)
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+{
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+ return dport->id;
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+}
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+
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static void *add_cxl_bus(void *parent, int id, const char *cxlbus_base)
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{
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const char *devname = devpath_to_devname(cxlbus_base);
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diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym
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index ce01298..0190b13 100644
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--- a/cxl/lib/libcxl.sym
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+++ b/cxl/lib/libcxl.sym
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@@ -101,6 +101,8 @@ global:
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cxl_port_get_host;
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cxl_port_get_bus;
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cxl_port_hosts_memdev;
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+ cxl_port_get_nr_dports;
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+ cxl_port_get_next_all;
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cxl_endpoint_get_first;
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cxl_endpoint_get_next;
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cxl_endpoint_get_devname;
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@@ -142,4 +144,9 @@ global:
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cxl_target_get_devname;
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cxl_target_maps_memdev;
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cxl_target_get_physical_node;
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+ cxl_dport_get_first;
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+ cxl_dport_get_next;
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+ cxl_dport_get_devname;
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+ cxl_dport_get_physical_node;
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+ cxl_dport_get_id;
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} LIBCXL_1;
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diff --git a/cxl/lib/private.h b/cxl/lib/private.h
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index 7e7742d..f483c30 100644
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--- a/cxl/lib/private.h
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+++ b/cxl/lib/private.h
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@@ -38,6 +38,16 @@ struct cxl_memdev {
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struct cxl_endpoint *endpoint;
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};
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+struct cxl_dport {
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+ int id;
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+ void *dev_buf;
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+ size_t buf_len;
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+ char *dev_path;
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+ char *phys_path;
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+ struct cxl_port *port;
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+ struct list_node list;
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+};
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+
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enum cxl_port_type {
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CXL_PORT_ROOT,
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CXL_PORT_SWITCH,
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@@ -53,6 +63,8 @@ struct cxl_port {
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int ports_init;
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int endpoints_init;
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int decoders_init;
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+ int dports_init;
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+ int nr_dports;
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struct cxl_ctx *ctx;
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struct cxl_bus *bus;
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enum cxl_port_type type;
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@@ -62,6 +74,7 @@ struct cxl_port {
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struct list_head child_ports;
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struct list_head endpoints;
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struct list_head decoders;
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+ struct list_head dports;
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};
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struct cxl_bus {
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diff --git a/cxl/libcxl.h b/cxl/libcxl.h
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index 0e484cc..07f4a31 100644
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--- a/cxl/libcxl.h
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+++ b/cxl/libcxl.h
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@@ -93,11 +93,23 @@ bool cxl_port_is_endpoint(struct cxl_port *port);
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struct cxl_bus *cxl_port_get_bus(struct cxl_port *port);
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const char *cxl_port_get_host(struct cxl_port *port);
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bool cxl_port_hosts_memdev(struct cxl_port *port, struct cxl_memdev *memdev);
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+int cxl_port_get_nr_dports(struct cxl_port *port);
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#define cxl_port_foreach(parent, port) \
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for (port = cxl_port_get_first(parent); port != NULL; \
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port = cxl_port_get_next(port))
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+struct cxl_dport;
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+struct cxl_dport *cxl_dport_get_first(struct cxl_port *port);
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+struct cxl_dport *cxl_dport_get_next(struct cxl_dport *dport);
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+const char *cxl_dport_get_devname(struct cxl_dport *dport);
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+const char *cxl_dport_get_physical_node(struct cxl_dport *dport);
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+int cxl_dport_get_id(struct cxl_dport *dport);
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+
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+#define cxl_dport_foreach(port, dport) \
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+ for (dport = cxl_dport_get_first(port); dport != NULL; \
|
|
+ dport = cxl_dport_get_next(dport))
|
|
+
|
|
struct cxl_decoder;
|
|
struct cxl_decoder *cxl_decoder_get_first(struct cxl_port *port);
|
|
struct cxl_decoder *cxl_decoder_get_next(struct cxl_decoder *decoder);
|
|
diff --git a/cxl/list.c b/cxl/list.c
|
|
index 27c963a..de96ff9 100644
|
|
--- a/cxl/list.c
|
|
+++ b/cxl/list.c
|
|
@@ -42,7 +42,7 @@ static const struct option options[] = {
|
|
OPT_BOOLEAN('D', "decoders", ¶m.decoders,
|
|
"include CXL decoder info"),
|
|
OPT_BOOLEAN('T', "targets", ¶m.targets,
|
|
- "include CXL target data with decoders"),
|
|
+ "include CXL target data with decoders or ports"),
|
|
OPT_BOOLEAN('i', "idle", ¶m.idle, "include disabled devices"),
|
|
OPT_BOOLEAN('u', "human", ¶m.human,
|
|
"use human friendly number formats "),
|
|
--
|
|
2.27.0
|
|
|