2c91dc1bcd
This includes support for the CXL commands, and adds the following packages: cxl-cli, cxl-devel, cxl-libs. Resolves: rhbz#2132167
330 lines
11 KiB
Diff
330 lines
11 KiB
Diff
From b90fc91e1034668cfde06f0fd8a7293df8b7690d Mon Sep 17 00:00:00 2001
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From: Dan Williams <dan.j.williams@intel.com>
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Date: Sun, 23 Jan 2022 16:53:50 -0800
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Subject: [PATCH 109/217] cxl/list: Filter memdev by ancestry
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Whenever a memdev filter is specified limit output of buses, ports and
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endpoints to those that are in the memdev's ancestry.
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Link: https://lore.kernel.org/r/164298563039.3021641.5253222797042241091.stgit@dwillia2-desk3.amr.corp.intel.com
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Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
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---
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Documentation/cxl/cxl-list.txt | 19 +++++++++
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Documentation/cxl/lib/libcxl.txt | 11 +++++
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cxl/filter.c | 69 ++++++++++++++++++++++++++++++++
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cxl/lib/libcxl.c | 36 +++++++++++++++++
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cxl/lib/libcxl.sym | 5 +++
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cxl/libcxl.h | 4 ++
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6 files changed, 144 insertions(+)
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diff --git a/Documentation/cxl/cxl-list.txt b/Documentation/cxl/cxl-list.txt
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index 1751868..bac27c7 100644
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--- a/Documentation/cxl/cxl-list.txt
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+++ b/Documentation/cxl/cxl-list.txt
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@@ -39,6 +39,25 @@ they are combined as an 'AND' filter. So, "-m mem0,mem1,mem2 -p port10"
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would only list objects that are beneath port10 AND map mem0, mem1, OR
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mem2.
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+Given that many topology queries seek to answer questions relative to a
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+given memdev, buses, ports, and endpoints can be filtered by one or more
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+memdevs. For example:
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+----
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+# cxl list -P -p switch,endpoint -m mem0
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+[
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+ {
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+ "port":"port1",
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+ "host":"ACPI0016:00",
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+ "endpoints:port1":[
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+ {
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+ "endpoint":"endpoint2",
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+ "host":"mem0"
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+ }
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+ ]
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+ }
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+]
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+----
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+
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The --human option in addition to reformatting some fields to more human
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friendly strings also unwraps the array to reduce the number of lines of
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output.
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diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt
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index 73b0fb9..b0253d7 100644
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--- a/Documentation/cxl/lib/libcxl.txt
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+++ b/Documentation/cxl/lib/libcxl.txt
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@@ -150,11 +150,18 @@ cxl_bus'.
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----
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struct cxl_bus *cxl_bus_get_first(struct cxl_ctx *ctx);
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struct cxl_bus *cxl_bus_get_next(struct cxl_bus *bus);
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+struct cxl_ctx *cxl_bus_get_ctx(struct cxl_bus *bus);
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+struct cxl_bus *cxl_memdev_get_bus(struct cxl_memdev *memdev);
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+struct cxl_bus *cxl_endpoint_get_bus(struct cxl_endpoint *endpoint);
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#define cxl_bus_foreach(ctx, bus) \
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for (bus = cxl_bus_get_first(ctx); bus != NULL; \
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bus = cxl_bus_get_next(bus))
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----
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+When a memdev is active it has established a CXL port hierarchy between
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+itself and the root of its associated CXL topology. The
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+cxl_{memdev,endpoint}_get_bus() helpers walk that topology to retrieve
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+the associated bus object.
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=== BUS: Attributes
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----
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@@ -209,6 +216,7 @@ int cxl_port_is_enabled(struct cxl_port *port);
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bool cxl_port_is_root(struct cxl_port *port);
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bool cxl_port_is_switch(struct cxl_port *port);
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bool cxl_port_is_endpoint(struct cxl_port *port);
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+bool cxl_port_hosts_memdev(struct cxl_port *port, struct cxl_memdev *memdev);
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----
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The port type is communicated via cxl_port_is_<type>(). An 'enabled' port
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is one that has succeeded in discovering the CXL component registers in
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@@ -217,6 +225,9 @@ memdev to be enabled for CXL memory operation all CXL ports in its
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ancestry must also be enabled including a root port, an arbitrary number
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of intervening switch ports, and a terminal endpoint port.
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+cxl_port_hosts_memdev() returns true if the port's host appears in the
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+memdev host's device topology ancestry.
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+
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ENDPOINTS
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---------
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CXL endpoint objects encapsulate the set of host-managed device-memory
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diff --git a/cxl/filter.c b/cxl/filter.c
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index 2130816..6dc61a1 100644
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--- a/cxl/filter.c
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+++ b/cxl/filter.c
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@@ -297,6 +297,66 @@ struct cxl_memdev *util_cxl_memdev_filter(struct cxl_memdev *memdev,
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return NULL;
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}
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+static struct cxl_bus *util_cxl_bus_filter_by_memdev(struct cxl_bus *bus,
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+ const char *ident,
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+ const char *serial)
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+{
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+ struct cxl_ctx *ctx = cxl_bus_get_ctx(bus);
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+ struct cxl_memdev *memdev;
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+
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+ if (!ident && !serial)
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+ return bus;
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+
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+ cxl_memdev_foreach(ctx, memdev) {
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+ if (!util_cxl_memdev_filter(memdev, ident, serial))
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+ continue;
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+ if (cxl_memdev_get_bus(memdev) == bus)
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+ return bus;
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+ }
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+
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+ return NULL;
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+}
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+
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+static struct cxl_endpoint *
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+util_cxl_endpoint_filter_by_memdev(struct cxl_endpoint *endpoint,
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+ const char *ident, const char *serial)
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+{
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+ struct cxl_ctx *ctx = cxl_endpoint_get_ctx(endpoint);
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+ struct cxl_memdev *memdev;
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+
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+ if (!ident && !serial)
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+ return endpoint;
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+
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+ cxl_memdev_foreach(ctx, memdev) {
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+ if (!util_cxl_memdev_filter(memdev, ident, serial))
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+ continue;
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+ if (cxl_memdev_get_endpoint(memdev) == endpoint)
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+ return endpoint;
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+ }
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+
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+ return NULL;
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+}
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+
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+static struct cxl_port *util_cxl_port_filter_by_memdev(struct cxl_port *port,
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+ const char *ident,
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+ const char *serial)
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+{
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+ struct cxl_ctx *ctx = cxl_port_get_ctx(port);
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+ struct cxl_memdev *memdev;
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+
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+ if (!ident && !serial)
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+ return port;
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+
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+ cxl_memdev_foreach(ctx, memdev) {
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+ if (!util_cxl_memdev_filter(memdev, ident, serial))
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+ continue;
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+ if (cxl_port_hosts_memdev(port, memdev))
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+ return port;
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+ }
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+
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+ return NULL;
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+}
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+
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static unsigned long params_to_flags(struct cxl_filter_params *param)
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{
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unsigned long flags = 0;
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@@ -399,6 +459,9 @@ static void walk_endpoints(struct cxl_port *port, struct cxl_filter_params *p,
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if (!util_cxl_endpoint_filter_by_port(endpoint, p->port_filter,
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pf_mode(p)))
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continue;
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+ if (!util_cxl_endpoint_filter_by_memdev(
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+ endpoint, p->memdev_filter, p->serial_filter))
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+ continue;
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if (!p->idle && !cxl_endpoint_is_enabled(endpoint))
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continue;
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if (p->endpoints) {
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@@ -450,6 +513,9 @@ static void walk_child_ports(struct cxl_port *parent_port,
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struct json_object *jchildports = NULL;
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struct json_object *jchildeps = NULL;
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+ if (!util_cxl_port_filter_by_memdev(port, p->memdev_filter,
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+ p->serial_filter))
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+ continue;
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if (!util_cxl_port_filter(port, p->port_filter, pf_mode(p)))
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goto walk_children;
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if (!util_cxl_port_filter_by_bus(port, p->bus_filter))
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@@ -573,6 +639,9 @@ int cxl_filter_walk(struct cxl_ctx *ctx, struct cxl_filter_params *p)
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struct cxl_port *port = cxl_bus_get_port(bus);
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const char *devname = cxl_bus_get_devname(bus);
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+ if (!util_cxl_bus_filter_by_memdev(bus, p->memdev_filter,
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+ p->serial_filter))
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+ continue;
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if (!util_cxl_bus_filter(bus, p->bus_filter))
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goto walk_children;
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if (!util_cxl_port_filter(port, p->port_filter, pf_mode(p)))
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diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c
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index 4523ca6..0065f6b 100644
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--- a/cxl/lib/libcxl.c
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+++ b/cxl/lib/libcxl.c
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@@ -455,6 +455,15 @@ CXL_EXPORT const char *cxl_memdev_get_host(struct cxl_memdev *memdev)
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return memdev->host;
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}
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+CXL_EXPORT struct cxl_bus *cxl_memdev_get_bus(struct cxl_memdev *memdev)
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+{
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+ struct cxl_endpoint *endpoint = cxl_memdev_get_endpoint(memdev);
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+
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+ if (!endpoint)
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+ return NULL;
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+ return cxl_endpoint_get_bus(endpoint);
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+}
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+
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CXL_EXPORT int cxl_memdev_get_major(struct cxl_memdev *memdev)
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{
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return memdev->major;
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@@ -724,6 +733,13 @@ CXL_EXPORT const char *cxl_endpoint_get_host(struct cxl_endpoint *endpoint)
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return cxl_port_get_host(&endpoint->port);
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}
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+CXL_EXPORT struct cxl_bus *cxl_endpoint_get_bus(struct cxl_endpoint *endpoint)
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+{
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+ struct cxl_port *port = &endpoint->port;
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+
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+ return cxl_port_get_bus(port);
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+}
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+
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CXL_EXPORT int cxl_endpoint_is_enabled(struct cxl_endpoint *endpoint)
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{
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return cxl_port_is_enabled(&endpoint->port);
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@@ -875,6 +891,21 @@ CXL_EXPORT const char *cxl_port_get_host(struct cxl_port *port)
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return devpath_to_devname(port->uport);
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}
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+CXL_EXPORT bool cxl_port_hosts_memdev(struct cxl_port *port,
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+ struct cxl_memdev *memdev)
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+{
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+ struct cxl_endpoint *endpoint = cxl_memdev_get_endpoint(memdev);
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+ struct cxl_port *iter;
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+
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+ if (!endpoint)
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+ return false;
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+
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+ iter = cxl_endpoint_get_port(endpoint);
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+ while (iter && iter != port)
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+ iter = iter->parent;
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+ return iter != NULL;
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+}
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+
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CXL_EXPORT int cxl_port_is_enabled(struct cxl_port *port)
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{
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struct cxl_ctx *ctx = cxl_port_get_ctx(port);
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@@ -985,6 +1016,11 @@ CXL_EXPORT const char *cxl_bus_get_provider(struct cxl_bus *bus)
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return devname;
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}
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+CXL_EXPORT struct cxl_ctx *cxl_bus_get_ctx(struct cxl_bus *bus)
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+{
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+ return cxl_port_get_ctx(&bus->port);
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+}
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+
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CXL_EXPORT void cxl_cmd_unref(struct cxl_cmd *cmd)
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{
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if (!cmd)
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diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym
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index 321acac..29f3498 100644
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--- a/cxl/lib/libcxl.sym
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+++ b/cxl/lib/libcxl.sym
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@@ -84,6 +84,7 @@ global:
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cxl_bus_get_devname;
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cxl_bus_get_id;
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cxl_bus_get_port;
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+ cxl_bus_get_ctx;
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cxl_port_get_first;
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cxl_port_get_next;
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cxl_port_get_devname;
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@@ -97,6 +98,8 @@ global:
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cxl_port_is_endpoint;
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cxl_port_get_bus;
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cxl_port_get_host;
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+ cxl_port_get_bus;
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+ cxl_port_hosts_memdev;
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cxl_endpoint_get_first;
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cxl_endpoint_get_next;
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cxl_endpoint_get_devname;
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@@ -107,6 +110,8 @@ global:
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cxl_endpoint_get_port;
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cxl_endpoint_get_host;
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cxl_endpoint_get_memdev;
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+ cxl_endpoint_get_bus;
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cxl_memdev_get_endpoint;
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cxl_memdev_is_enabled;
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+ cxl_memdev_get_bus;
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} LIBCXL_1;
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diff --git a/cxl/libcxl.h b/cxl/libcxl.h
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index 790ece8..e7b675e 100644
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--- a/cxl/libcxl.h
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+++ b/cxl/libcxl.h
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@@ -39,6 +39,7 @@ int cxl_memdev_get_id(struct cxl_memdev *memdev);
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unsigned long long cxl_memdev_get_serial(struct cxl_memdev *memdev);
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const char *cxl_memdev_get_devname(struct cxl_memdev *memdev);
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const char *cxl_memdev_get_host(struct cxl_memdev *memdev);
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+struct cxl_bus *cxl_memdev_get_bus(struct cxl_memdev *memdev);
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int cxl_memdev_get_major(struct cxl_memdev *memdev);
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int cxl_memdev_get_minor(struct cxl_memdev *memdev);
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struct cxl_ctx *cxl_memdev_get_ctx(struct cxl_memdev *memdev);
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@@ -68,6 +69,7 @@ const char *cxl_bus_get_provider(struct cxl_bus *bus);
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const char *cxl_bus_get_devname(struct cxl_bus *bus);
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int cxl_bus_get_id(struct cxl_bus *bus);
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struct cxl_port *cxl_bus_get_port(struct cxl_bus *bus);
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+struct cxl_ctx *cxl_bus_get_ctx(struct cxl_bus *bus);
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#define cxl_bus_foreach(ctx, bus) \
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for (bus = cxl_bus_get_first(ctx); bus != NULL; \
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@@ -87,6 +89,7 @@ struct cxl_bus *cxl_port_to_bus(struct cxl_port *port);
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bool cxl_port_is_endpoint(struct cxl_port *port);
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struct cxl_bus *cxl_port_get_bus(struct cxl_port *port);
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const char *cxl_port_get_host(struct cxl_port *port);
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+bool cxl_port_hosts_memdev(struct cxl_port *port, struct cxl_memdev *memdev);
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#define cxl_port_foreach(parent, port) \
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for (port = cxl_port_get_first(parent); port != NULL; \
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@@ -102,6 +105,7 @@ int cxl_endpoint_is_enabled(struct cxl_endpoint *endpoint);
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struct cxl_port *cxl_endpoint_get_parent(struct cxl_endpoint *endpoint);
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struct cxl_port *cxl_endpoint_get_port(struct cxl_endpoint *endpoint);
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const char *cxl_endpoint_get_host(struct cxl_endpoint *endpoint);
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+struct cxl_bus *cxl_endpoint_get_bus(struct cxl_endpoint *endpoint);
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struct cxl_memdev *cxl_endpoint_get_memdev(struct cxl_endpoint *endpoint);
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int cxl_memdev_is_enabled(struct cxl_memdev *memdev);
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--
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2.27.0
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