Tool to transform and deploy CPU microcode update for x86.
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Eugene Syromiatnikov 735fed49e1 Update Intel CPU microcode to microcode-20241112 release
- Update Intel CPU microcode to microcode-20241112 release, addresses
  CVE-2024-21820, CVE-2024-21853, CVE-2024-23918, CVE-2024-23984:
  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
    intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b0005c0
    up to 0x2b000603;
  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
    intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
    intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
    intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
    intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
    intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b0005c0
    up to 0x2b000603;
  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
    intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
    intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
    intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
    intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
    intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision
    0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
    intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
    intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
    intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
    intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
    intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision
    0x2b0005c0 up to 0x2b000603;
  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision
    0x36 up to 0x37;
  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
    intel-ucode/06-97-02) from revision 0x36 up to 0x37;
  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
    from revision 0x36 up to 0x37;
  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
    from revision 0x36 up to 0x37;
  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
    intel-ucode/06-97-05) from revision 0x36 up to 0x37;
  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x36
    up to 0x37;
  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
    from revision 0x36 up to 0x37;
  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
    from revision 0x36 up to 0x37;
  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision
    0x434 up to 0x435;
  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in
    intel-ucode/06-9a-03) from revision 0x434 up to 0x435;
  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in
    intel-ucode/06-9a-04) from revision 0x434 up to 0x435;
  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x434
    up to 0x435;
  - Update of 06-aa-04/0xe6 (MTL-H/U C0) microcode from revision 0x1f
    up to 0x20;
  - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x129 up
    to 0x12b;
  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision
    0x4122 up to 0x4123;
  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
    intel-ucode/06-ba-02) from revision 0x4122 up to 0x4123;
  - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) from
    revision 0x4122 up to 0x4123;
  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
    intel-ucode/06-ba-03) from revision 0x4122 up to 0x4123;
  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4122
    up to 0x4123;
  - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) from
    revision 0x4122 up to 0x4123;
  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
    intel-ucode/06-ba-08) from revision 0x4122 up to 0x4123;
  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
    intel-ucode/06-ba-08) from revision 0x4122 up to 0x4123;
  - Update of 06-ba-08/0xe0 microcode from revision 0x4122 up to 0x4123;
  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
    intel-ucode/06-bf-02) from revision 0x36 up to 0x37;
  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
    intel-ucode/06-bf-02) from revision 0x36 up to 0x37;
  - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x36 up
    to 0x37;
  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02)
    from revision 0x36 up to 0x37;
  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
    intel-ucode/06-bf-05) from revision 0x36 up to 0x37;
  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
    intel-ucode/06-bf-05) from revision 0x36 up to 0x37;
  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05)
    from revision 0x36 up to 0x37;
  - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x36 up
    to 0x37;
  - Update of 06-cf-01/0x87 (EMR-SP A0) microcode from revision 0x21000230
    up to 0x21000283;
  - Update of 06-cf-02/0x87 (EMR-SP A1) microcode (in
    intel-ucode/06-cf-01) from revision 0x21000230 up to 0x21000283;
  - Update of 06-cf-01/0x87 (EMR-SP A0) microcode (in
    intel-ucode/06-cf-02) from revision 0x21000230 up to 0x21000283;
  - Update of 06-cf-02/0x87 (EMR-SP A1) microcode from revision 0x21000230
    up to 0x21000283.

* .gitignore: Replace /microcode-20240910.tar.gz entry
with /microcode-20241112.tar.gz.
* microcode_ctl.spec (intel_ucode_version): Bump to 20241112.
(Release): Reset to 1.
(%changelog): Add a record, fix a typo in the previous one.
* sources: Replace microcode-20240910.tar.gz record with
microcode-20241112.tar.gz.

Resolves: RHEL-67335
Signed-off-by: Eugene Syromiatnikov <esyr@redhat.com>
2025-01-02 15:07:37 +01:00
.gitignore Update Intel CPU microcode to microcode-20241112 release 2025-01-02 15:07:37 +01:00
01-microcode.conf Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
06-4f-01_config Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
06-4f-01_disclaimer Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
06-4f-01_readme Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
99-microcode-override.conf Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
check_caveats Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
codenames.list Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
dracut_99microcode_ctl-fw_dir_override_module_init.sh Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
gating.yaml Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
gen_provides.sh Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
gen_updates2.py Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
intel_config Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
intel_disclaimer Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
intel_readme Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
microcode_ctl.spec Update Intel CPU microcode to microcode-20241112 release 2025-01-02 15:07:37 +01:00
microcode.service Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
README Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
README.caveats Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
reload_microcode Bring in RHEL-specific packaging bits 2024-07-29 19:58:41 +02:00
sources Update Intel CPU microcode to microcode-20241112 release 2025-01-02 15:07:37 +01:00
update_ucode update_ucode: typo fix 2024-09-23 17:19:39 +02:00

The microcode_ctl package contains microcode files (vendor-provided binary data
and/or code in proprietary format that affects behaviour of a device) for Intel
CPUs that may be loaded into the CPU during boot.

This directory contains information regarding various aspects of the provided
microcode files and their usage.

 * LICENSE.intel-ucode
   "license" file from the Intel x86 CPU microcode archive.
 * README
   This file.
 * README.caveats
   Caveats (mechanism for enabling/disabling usage of sets of microcode files
   based on caveat configuration and user preferences) documentation.
   Also contains general information about microcode update behaviour and links
   with additional information about the relevant microarchitectural
   vulnerabilities.
 * README.intel-ucode
   "README.md" file from the Intel x86 CPU microcode archive.
 * RELEASE_NOTES.intel-ucode
   "releasenote.md" file from the Intel x86 CPU microcode archive.
 * SECURITY.intel-ucode
   "security.md" file from the Intel x86 CPU microcode archive.
 * SUMMARY.intel-ucode
   Information about supplied microcode files extracted from their headers,
   in a table form.  Columns have the following meaning:
    * "Path": path to the microcode file under one of the following directories:
       * /usr/share/microcode_ctl/ucode_with_caveats/intel
       * /usr/share/microcode_ctl/ucode_with_caveats
       * /usr/share/microcode_ctl
       * /lib/firmware
       * /etc/firmware
    * "Offset": offset of the microcode blob within the micocode file in bytes.
    * "Ext. Offset": offset of the extended signature header within
      the microcode file in bytes.
    * "Data Size": size of microcode data in bytes.  0 means 2000 bytes.
    * "Total Size": size of microcode blob in bytes, incuding headers.
      0 means 2048 bytes.
    * "CPUID": CPU ID signature (in format returned by the CPUID instruction).
    * "Platform ID Mask": mask of suitable Platform IDs (provided in bits
      52..50 of MSR 0x17).
    * "Revision": microcode revision.
    * "Date": microcode creation date.
    * "Checksum": sum (in base 1<< 32) of all 32-bit values comprising
      the microcode (from Offset up to Offset + Total Size).
    * "Codenames": list of known CPU codenames associated with the CPUID
      and Platform ID Mask combination.
   Please refer to README.cavets, section "Microcode file structure"
   for additional information regarding microcode header fields.
 * caveats
   Directory that contains readme files for each specific caveat.