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			61 lines
		
	
	
		
			3.0 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| Some Intel Tiger Lake-UP3/UP4 CPU models (TGL, family 6, model 140, stepping 1)
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| had reports of system hangs when a microcode update, that was included
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| since microcode-20201110 update, was applied[1].  In order to address this,
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| microcode update had been disabled by default on these systems.  The revision
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| 0x88 seems to have fixed the aforementioned issue, hence it is enabled
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| by default (but can be disabled explicitly; see below).
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| 
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| [1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/44
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| 
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| For the reference, SHA1 checksums of 06-8c-01 microcode files containing
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| microcode revisions in question are listed below:
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|  * 06-8c-01, revision 0x68: 2204a6dee1688980cd228268fdf4b6ed5904fe04
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|  * 06-8c-01, revision 0x88: 61b6590feb2769046d5b0c394179beaf2df51290
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|  * 06-8c-01, revision 0x9a: 48b3ae8d27d8138b5b47052d2f8184bf555ad18e
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|  * 06-8c-01, revision 0xa4: 70753f54f5be84376bdebeb710595e4dc2f6d92f
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| 
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| Please contact your system vendor for a BIOS/firmware update that contains
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| the latest microcode version.  For the information regarding microcode versions
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| required for mitigating specific side-channel cache attacks, please refer
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| to the following knowledge base articles:
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|  * CVE-2020-8695 (Information disclosure issue in Intel SGX via RAPL interface),
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|    CVE-2020-8696 (Vector Register Leakage-Active),
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|    CVE-2020-8698 (Fast Forward Store Predictor):
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|    https://access.redhat.com/articles/5569051
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|  * CVE-2020-24489 (VT-d-related Privilege Escalation),
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|    CVE-2020-24511 (Improper Isolation of Shared Resources),
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|    CVE-2020-24512 (Observable Timing Discrepancy),
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|    CVE-2020-24513 (Information Disclosure on Some Intel Atom Processors):
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|    https://access.redhat.com/articles/6101171
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|  * CVE-2021-0145 (Fast store forward predictor - Cross Domain Training):
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|    https://access.redhat.com/articles/6716541
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|  * CVE-2022-21123 (Shared Buffers Data Read):
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|    https://access.redhat.com/articles/6963124
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| 
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| The information regarding disabling microcode update is provided below.
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| 
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| To disable 06-8c-01 microcode updates for a specific kernel
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| version, please create a file "disallow-intel-06-8c-01" inside
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| /lib/firmware/<kernel_version> directory, run
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| "/usr/libexec/microcode_ctl/update_ucode" to remove it from the firmware
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| directory where microcode is available for late microcode update, and run
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| "dracut -f --kver <kernel_version>", so initramfs for this kernel version
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| is regenerated, for example:
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| 
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|     touch /lib/firmware/3.10.0-862.9.1/disallow-intel-06-8c-01
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|     /usr/libexec/microcode_ctl/update_ucode
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|     dracut -f --kver 3.10.0-862.9.1
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| 
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| To avoid addition of this microcode for all kernels, please create file
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| "/etc/microcode_ctl/ucode_with_caveats/disallow-intel-06-8c-01", run
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| "/usr/libexec/microcode_ctl/update_ucode" for late microcode updates,
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| and "dracut -f --regenerate-all" for early microcode updates:
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| 
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|     mkdir -p /etc/microcode_ctl/ucode_with_caveats
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|     touch /etc/microcode_ctl/ucode_with_caveats/disallow-intel-06-8c-01
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|     /usr/libexec/microcode_ctl/update_ucode
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|     dracut -f --regenerate-all
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| 
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| Please refer to /usr/share/doc/microcode_ctl/README.caveats for additional
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| information.
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