Tool to transform and deploy CPU microcode update for x86.
- Update Intel CPU microcode to microcode-20240531 release, addresses
CVE-2023-22655, CVE-2023-23583. CVE-2023-28746, CVE-2023-38575,
CVE-2023-39368, CVE-2023-42667, CVE-2023-43490, CVE-2023-45733,
CVE-2023-46103, CVE-2023-49141:
- Addition of 06-aa-04/0xe6 (MTL-H/U C0) microcode at revision 0x1c;
- Addition of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) at
revision 0x4121;
- Addition of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) at
revision 0x4121;
- Addition of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
intel-ucode/06-ba-08) at revision 0x4121;
- Addition of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
intel-ucode/06-ba-08) at revision 0x4121;
- Addition of 06-ba-08/0xe0 microcode at revision 0x4121;
- Addition of 06-cf-01/0x87 (EMR-SP A0) microcode at revision
0x21000230;
- Addition of 06-cf-02/0x87 (EMR-SP A1) microcode (in
intel-ucode/06-cf-01) at revision 0x21000230;
- Addition of 06-cf-01/0x87 (EMR-SP A0) microcode (in
intel-ucode/06-cf-02) at revision 0x21000230;
- Addition of 06-cf-02/0x87 (EMR-SP A1) microcode at revision
0x21000230;
- Removal of 06-8f-04/0x10 microcode at revision 0x2c000290;
- Removal of 06-8f-04/0x87 (SPR-SP E0/S1) microcode at revision
0x2b0004d0;
- Removal of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
intel-ucode/06-8f-04) at revision 0x2c000290;
- Removal of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-ucode/06-8f-04) at revision 0x2b0004d0;
- Removal of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) at
revision 0x2c000290;
- Removal of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-ucode/06-8f-04) at revision 0x2b0004d0;
- Removal of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
intel-ucode/06-8f-04) at revision 0x2b0004d0;
- Removal of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
intel-ucode/06-8f-04) at revision 0x2c000290;
- Removal of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-ucode/06-8f-04) at revision 0x2b0004d0;
- Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode (in
intel-06-8c-01/intel-ucode/06-8c-01) from revision 0xb4 up to 0xb6;
- Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0)
microcode (in intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0c) from
revision 0xf8 up to 0xfa;
- Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-09) from revision 0xf4 up
to 0xf8;
- Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0a) from revision 0xf4 up
to 0xf6;
- Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0c) from revision 0xf4 up
to 0xf6;
- Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0d) from revision 0xfa up
to 0xfc;
- Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000181
up to 0x1000191;
- Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003604
up to 0x4003605;
- Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision
0x5003604 up to 0x5003605;
- Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002703
up to 0x7002802;
- Update of 06-56-05/0x10 (BDX-NS A0/A1, HWL A1) microcode from revision
0xe000014 up to 0xe000015;
- Update of 06-5f-01/0x01 (DNV B0) microcode from revision 0x38 up
to 0x3e;
- Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd0003b9
up to 0xd0003d1;
- Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x1000268
up to 0x1000290;
- Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x3e up
to 0x42;
- Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x22 up
to 0x24;
- Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xc2
up to 0xc4;
- Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x34 up
to 0x36;
- Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x4e up
to 0x50;
- Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from
revision 0x2c000290 up to 0x2c000390;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-05) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision
0x2c000290 up to 0x2c000390;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b0004d0
up to 0x2b0005c0;
- Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) from
revision 0x2c000290 up to 0x2c000390;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-ucode/06-8f-05) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
intel-ucode/06-8f-05) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
intel-ucode/06-8f-05) from revision 0x2c000290 up to 0x2c000390;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-ucode/06-8f-05) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from
revision 0x2c000290 up to 0x2c000390;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-06) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
intel-ucode/06-8f-06) from revision 0x2c000290 up to 0x2c000390;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-ucode/06-8f-06) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-06/0x10 microcode from revision 0x2c000290 up to
0x2c000390;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b0004d0
up to 0x2b0005c0;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
intel-ucode/06-8f-06) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
intel-ucode/06-8f-06) from revision 0x2c000290 up to 0x2c000390;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-ucode/06-8f-06) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-07) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-ucode/06-8f-07) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-ucode/06-8f-07) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision
0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-ucode/06-8f-07) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from
revision 0x2c000290 up to 0x2c000390;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-08) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
intel-ucode/06-8f-08) from revision 0x2c000290 up to 0x2c000390;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-ucode/06-8f-08) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from
revision 0x2c000290 up to 0x2c000390;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-ucode/06-8f-08) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
intel-ucode/06-8f-08) from revision 0x2b0004d0 up to 0x2b0005c0;
- Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision
0x2c000290 up to 0x2c000390;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision
0x2b0004d0 up to 0x2b0005c0;
- Update of 06-96-01/0x01 (EHL B1) microcode from revision 0x17 up
to 0x19;
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision
0x32 up to 0x35;
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
intel-ucode/06-97-02) from revision 0x32 up to 0x35;
- Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
from revision 0x32 up to 0x35;
- Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
from revision 0x32 up to 0x35;
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
intel-ucode/06-97-05) from revision 0x32 up to 0x35;
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x32
up to 0x35;
- Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
from revision 0x32 up to 0x35;
- Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
from revision 0x32 up to 0x35;
- Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision
0x430 up to 0x433;
- Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in
intel-ucode/06-9a-03) from revision 0x430 up to 0x433;
- Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in
intel-ucode/06-9a-04) from revision 0x430 up to 0x433;
- Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x430
up to 0x433;
- Update of 06-9a-04/0x40 (AZB A0) microcode from revision 0x5 up
to 0x7;
- Update of 06-9c-00/0x01 (JSL A0/A1) microcode from revision 0x24000024
up to 0x24000026;
- Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf8 up
to 0xfa;
- Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf8
up to 0xfa;
- Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf8
up to 0xfa;
- Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf8
up to 0xfa;
- Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision
0xf8 up to 0xfa;
- Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x5d up
to 0x5e;
- Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x11d up
to 0x123;
- Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision
0x411c up to 0x4121;
- Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
intel-ucode/06-ba-02) from revision 0x411c up to 0x4121;
- Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
intel-ucode/06-ba-03) from revision 0x411c up to 0x4121;
- Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x411c
up to 0x4121;
- Update of 06-be-00/0x11 (ADL-N A0) microcode from revision 0x12 up
to 0x17;
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
intel-ucode/06-bf-02) from revision 0x32 up to 0x35;
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
intel-ucode/06-bf-02) from revision 0x32 up to 0x35;
- Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x32 up
to 0x35;
- Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02)
from revision 0x32 up to 0x35;
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
intel-ucode/06-bf-05) from revision 0x32 up to 0x35;
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
intel-ucode/06-bf-05) from revision 0x32 up to 0x35;
- Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05)
from revision 0x32 up to 0x35;
- Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x32 up
to 0x35.
* .gitignore: Replace /microcode-20231009.tar.gz entry
with /microcode-20240531.tar.gz.
* 0001-releasenote.md-eliminate-usage-of-U-0080.patch
* 0002-releasenote.md-eliminate-most-of-the-trailing-whites.patch: Remove.
* 0003-releasenote.md-remove-excess-Release-Notes-headers.patch: Likewise.
* 0004-releasenote.md-sort-the-entries-of-the-20230808-rele.patch: Likewise.
* 0005-releasenote.md-fix-incorrect-platform-mask-for-RPL-H.patch: Likewise.
* 0006-releasenote.md-fix-stepping-for-RPL-S.patch: Likewise.
* 0007-releasenote.md-add-missing-06-ba-03-e0-to-the-new-mi.patch: Likewise.
* 0008-releasenote.md-remove-the-duplicating-06-9e-0c-22-re.patch: Likewise.
* 0009-releasenote.md-fix-old-revisions-for-06-8e-09-10-and.patch: Likewise.
* 0010-releasenote.md-add-old-revisions-for-06-be-00-11-06-.patch: Likewise.
* 0011-releasenote.md-add-stub-release-notes-for-microcode-.patch: Likewise.
* 06-8c-01_readme: Add a checksum for revision 0xb6.
* 06-8e-9e-0x-0xca_readme: Add checksum for new microcode revisions
of 06-8e-0c and 06-9e-0[9acd] CPUIDs.
* 06-8e-9e-0x-dell_readme: Likewise.
* codenames.list: Add descriptors for signatures a06a4 (06-aa-04, MTL),
c06f1 (06-cf-01, EMR-SP A0), and c06f2 (06-cf-02, EMR-SP A1).
* microcode_ctl.spec (intel_ucode_version): Bump to 20240531.
(Source0): Add the URL back.
(Patch0001, Patch0002, Patch0003, Patch0004, Patch0005, Patch0006,
Patch0007, Patch0008, Patch0009, Patch0010, Patch0011): Remove.
(%prep): Don't apply the patches.
(%changelog): Add a record.
* sources: Replace microcode-20231009.tar.gz record with
microcode-20240531.tar.gz.
* update_ucode: Also check for symvers.xz in addition to symvers.gz.
Resolves: RHEL-30859
Resolves: RHEL-30862
Resolves: RHEL-30865
Resolves: RHEL-30868
Resolves: RHEL-30871
Resolves: RHEL-41093
Resolves: RHEL-41108
Signed-off-by: Eugene Syromiatnikov <esyr@redhat.com>
|
||
|---|---|---|
| .gitignore | ||
| 01-microcode.conf | ||
| 06-2d-07_config | ||
| 06-2d-07_disclaimer | ||
| 06-2d-07_readme | ||
| 06-4e-03_config | ||
| 06-4e-03_disclaimer | ||
| 06-4e-03_readme | ||
| 06-4f-01_config | ||
| 06-4f-01_disclaimer | ||
| 06-4f-01_readme | ||
| 06-5e-03_config | ||
| 06-5e-03_disclaimer | ||
| 06-5e-03_readme | ||
| 06-8c-01_config | ||
| 06-8c-01_disclaimer | ||
| 06-8c-01_readme | ||
| 06-8e-9e-0x-0xca_config | ||
| 06-8e-9e-0x-0xca_disclaimer | ||
| 06-8e-9e-0x-0xca_readme | ||
| 06-8e-9e-0x-dell_config | ||
| 06-8e-9e-0x-dell_disclaimer | ||
| 06-8e-9e-0x-dell_readme | ||
| 06-55-04_config | ||
| 06-55-04_disclaimer | ||
| 06-55-04_readme | ||
| 99-microcode-override.conf | ||
| check_caveats | ||
| codenames.list | ||
| dracut_99microcode_ctl-fw_dir_override_module_init.sh | ||
| gating.yaml | ||
| gen_provides.sh | ||
| gen_updates2.py | ||
| intel_config | ||
| intel_disclaimer | ||
| intel_readme | ||
| microcode_ctl.spec | ||
| microcode.service | ||
| README | ||
| README.caveats | ||
| reload_microcode | ||
| sources | ||
| update_ucode | ||
The microcode_ctl package contains microcode files (vendor-provided binary data
and/or code in proprietary format that affects behaviour of a device) for Intel
CPUs that may be loaded into the CPU during boot.
This directory contains information regarding various aspects of the provided
microcode files and their usage.
* LICENSE.intel-ucode
"license" file from the Intel x86 CPU microcode archive.
* README
This file.
* README.caveats
Caveats (mechanism for enabling/disabling usage of sets of microcode files
based on caveat configuration and user preferences) documentation.
Also contains general information about microcode update behaviour and links
with additional information about the relevant microarchitectural
vulnerabilities.
* README.intel-ucode
"README.md" file from the Intel x86 CPU microcode archive.
* RELEASE_NOTES.intel-ucode
"releasenote.md" file from the Intel x86 CPU microcode archive.
* SECURITY.intel-ucode
"security.md" file from the Intel x86 CPU microcode archive.
* SUMMARY.intel-ucode
Information about supplied microcode files extracted from their headers,
in a table form. Columns have the following meaning:
* "Path": path to the microcode file under one of the following directories:
* /usr/share/microcode_ctl/ucode_with_caveats/intel
* /usr/share/microcode_ctl/ucode_with_caveats
* /usr/share/microcode_ctl
* /lib/firmware
* /etc/firmware
* "Offset": offset of the microcode blob within the micocode file in bytes.
* "Ext. Offset": offset of the extended signature header within
the microcode file in bytes.
* "Data Size": size of microcode data in bytes. 0 means 2000 bytes.
* "Total Size": size of microcode blob in bytes, incuding headers.
0 means 2048 bytes.
* "CPUID": CPU ID signature (in format returned by the CPUID instruction).
* "Platform ID Mask": mask of suitable Platform IDs (provided in bits
52..50 of MSR 0x17).
* "Revision": microcode revision.
* "Date": microcode creation date.
* "Checksum": sum (in base 1<< 32) of all 32-bit values comprising
the microcode (from Offset up to Offset + Total Size).
* "Codenames": list of known CPU codenames associated with the CPUID
and Platform ID Mask combination.
Please refer to README.cavets, section "Microcode file structure"
for additional information regarding microcode header fields.
* caveats
Directory that contains readme files for each specific caveat.