Tool to transform and deploy CPU microcode update for x86.
- Add a caveat to provide ability to persistently disable SPR-EE updates
beyond 0x2b0005c0 on systems where absence of latency spikes
is more important than lack of the latest CVE mitigations (RHEL-95245)
- Update Intel CPU microcode to microcode-20250512 release, addresses
CVE-2024-28956, CVE-2025-20103, CVE-2025-20054, CVE-2024-43420,
CVE-2025-20623, CVE-2024-45332, CVE-2025-24495, CVE-2025-20012
(RHEL-92231)
- Addition of 06-8f-04/0x10 microcode (in
intel-06-8f-08/intel-ucode/06-8f-08) at revision 0x2c0003f7;
- Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-06-8f-08/intel-ucode/06-8f-08) at revision 0x2b000639;
- Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
intel-06-8f-08/intel-ucode/06-8f-08) at revision 0x2c0003f7;
- Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-06-8f-08/intel-ucode/06-8f-08) at revision 0x2b000639;
- Addition of 06-8f-06/0x10 microcode (in
intel-06-8f-08/intel-ucode/06-8f-08) at revision 0x2c0003f7;
- Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-06-8f-08/intel-ucode/06-8f-08) at revision 0x2b000639;
- Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
intel-06-8f-08/intel-ucode/06-8f-08) at revision 0x2b000639;
- Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
intel-06-8f-08/intel-ucode/06-8f-08) at revision 0x2c0003f7;
- Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-06-8f-08/intel-ucode/06-8f-08) at revision 0x2b000639;
- Addition of 06-ad-01/0x20 (GNR-AP/SP H0) microcode at revision
0xa0000d1;
- Addition of 06-ad-01/0x95 (GNR-AP/SP B0) microcode at revision
0x10003a2;
- Addition of 06-b5-00/0x80 (ARL-U A1) microcode at revision 0xa;
- Addition of 06-bd-01/0x80 (LNL B0) microcode at revision 0x11f;
- Addition of 06-c5-02/0x82 (ARL-H A1) microcode at revision 0x118;
- Addition of 06-c6-02/0x82 (ARL-HX 8P/S B0) microcode (in
intel-ucode/06-c5-02) at revision 0x118;
- Addition of 06-c6-04/0x82 microcode (in intel-ucode/06-c5-02) at
revision 0x118;
- Addition of 06-ca-02/0x82 microcode (in intel-ucode/06-c5-02) at
revision 0x118;
- Addition of 06-c5-02/0x82 (ARL-H A1) microcode (in
intel-ucode/06-c6-02) at revision 0x118;
- Addition of 06-c6-02/0x82 (ARL-HX 8P/S B0) microcode at revision
0x118;
- Addition of 06-c6-04/0x82 microcode (in intel-ucode/06-c6-02) at
revision 0x118;
- Addition of 06-ca-02/0x82 microcode (in intel-ucode/06-c6-02) at
revision 0x118;
- Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode (in
intel-06-8c-01/intel-ucode/06-8c-01) from revision 0xb8 up to 0xbc;
- Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0)
microcode (in intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0c) from
revision 0xfc up to 0x100;
- Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0d) from revision 0x102 up
to 0x104;
- Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision
0x5003707 up to 0x5003901;
- Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002904
up to 0x7002b01;
- Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd0003f5
up to 0xd000404;
- Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x10002c0
up to 0x10002d0;
- Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x24 up
to 0x26;
- Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xc6
up to 0xca;
- Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x38 up
to 0x3c;
- Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x52 up
to 0x56;
- Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from
revision 0x2c0003e0 up to 0x2c0003f7;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-05) from revision 0x2b000620 up to 0x2b000639;
- Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision
0x2c0003e0 up to 0x2c0003f7;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b000620
up to 0x2b000639;
- Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) from
revision 0x2c0003e0 up to 0x2c0003f7;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-ucode/06-8f-05) from revision 0x2b000620 up to 0x2b000639;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
intel-ucode/06-8f-05) from revision 0x2b000620 up to 0x2b000639;
- Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
intel-ucode/06-8f-05) from revision 0x2c0003e0 up to 0x2c0003f7;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-ucode/06-8f-05) from revision 0x2b000620 up to 0x2b000639;
- Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from
revision 0x2c0003e0 up to 0x2c0003f7;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-06) from revision 0x2b000620 up to 0x2b000639;
- Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
intel-ucode/06-8f-06) from revision 0x2c0003e0 up to 0x2c0003f7;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-ucode/06-8f-06) from revision 0x2b000620 up to 0x2b000639;
- Update of 06-8f-06/0x10 microcode from revision 0x2c0003e0 up to
0x2c0003f7;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b000620
up to 0x2b000639;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
intel-ucode/06-8f-06) from revision 0x2b000620 up to 0x2b000639;
- Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
intel-ucode/06-8f-06) from revision 0x2c0003e0 up to 0x2c0003f7;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-ucode/06-8f-06) from revision 0x2b000620 up to 0x2b000639;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-07) from revision 0x2b000620 up to 0x2b000639;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-ucode/06-8f-07) from revision 0x2b000620 up to 0x2b000639;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-ucode/06-8f-07) from revision 0x2b000620 up to 0x2b000639;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision
0x2b000620 up to 0x2b000639;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-ucode/06-8f-07) from revision 0x2b000620 up to 0x2b000639;
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision
0x38 up to 0x3a;
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
intel-ucode/06-97-02) from revision 0x38 up to 0x3a;
- Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
from revision 0x38 up to 0x3a;
- Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
from revision 0x38 up to 0x3a;
- Update of 06-bf-06/0x07 microcode (in intel-ucode/06-97-02) from
revision 0x38 up to 0x3a;
- Update of 06-bf-07/0x07 microcode (in intel-ucode/06-97-02) from
revision 0x38 up to 0x3a;
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
intel-ucode/06-97-05) from revision 0x38 up to 0x3a;
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x38
up to 0x3a;
- Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
from revision 0x38 up to 0x3a;
- Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
from revision 0x38 up to 0x3a;
- Update of 06-bf-06/0x07 microcode (in intel-ucode/06-97-05) from
revision 0x38 up to 0x3a;
- Update of 06-bf-07/0x07 microcode (in intel-ucode/06-97-05) from
revision 0x38 up to 0x3a;
- Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision
0x436 up to 0x437;
- Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in
intel-ucode/06-9a-03) from revision 0x436 up to 0x437;
- Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in
intel-ucode/06-9a-04) from revision 0x436 up to 0x437;
- Update of 06-9a-04/0x40 (AZB A0) microcode from revision 0x9 up
to 0xa;
- Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x436
up to 0x437;
- Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xfc up
to 0x100;
- Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xfc
up to 0x100;
- Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xfc
up to 0x100;
- Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xfe
up to 0x102;
- Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision
0xfc up to 0x100;
- Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x63 up
to 0x64;
- Update of 06-aa-04/0xe6 (MTL-H/U C0) microcode from revision 0x20
up to 0x24;
- Update of 06-af-03/0x01 (SRF-SP C0) microcode from revision 0x3000330
up to 0x3000341;
- Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x12c up
to 0x12f;
- Update of 06-b7-04/0x32 microcode (in intel-ucode/06-b7-01) from
revision 0x12c up to 0x12f;
- Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision
0x4124 up to 0x4128;
- Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
intel-ucode/06-ba-02) from revision 0x4124 up to 0x4128;
- Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) from
revision 0x4124 up to 0x4128;
- Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
intel-ucode/06-ba-03) from revision 0x4124 up to 0x4128;
- Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4124
up to 0x4128;
- Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) from
revision 0x4124 up to 0x4128;
- Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
intel-ucode/06-ba-08) from revision 0x4124 up to 0x4128;
- Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
intel-ucode/06-ba-08) from revision 0x4124 up to 0x4128;
- Update of 06-ba-08/0xe0 microcode from revision 0x4124 up to 0x4128;
- Update of 06-be-00/0x19 (ADL-N A0) microcode from revision 0x1c up
to 0x1d;
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
intel-ucode/06-bf-02) from revision 0x38 up to 0x3a;
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
intel-ucode/06-bf-02) from revision 0x38 up to 0x3a;
- Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x38 up
to 0x3a;
- Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02)
from revision 0x38 up to 0x3a;
- Update of 06-bf-06/0x07 microcode (in intel-ucode/06-bf-02) from
revision 0x38 up to 0x3a;
- Update of 06-bf-07/0x07 microcode (in intel-ucode/06-bf-02) from
revision 0x38 up to 0x3a;
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
intel-ucode/06-bf-05) from revision 0x38 up to 0x3a;
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
intel-ucode/06-bf-05) from revision 0x38 up to 0x3a;
- Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05)
from revision 0x38 up to 0x3a;
- Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x38 up
to 0x3a;
- Update of 06-bf-06/0x07 microcode (in intel-ucode/06-bf-05) from
revision 0x38 up to 0x3a;
- Update of 06-bf-07/0x07 microcode (in intel-ucode/06-bf-05) from
revision 0x38 up to 0x3a;
- Update of 06-cf-01/0x87 (EMR-SP A0) microcode from revision 0x21000291
up to 0x210002a9;
- Update of 06-cf-02/0x87 (EMR-SP A1) microcode (in
intel-ucode/06-cf-01) from revision 0x21000291 up to 0x210002a9;
- Update of 06-cf-01/0x87 (EMR-SP A0) microcode (in
intel-ucode/06-cf-02) from revision 0x21000291 up to 0x210002a9;
- Update of 06-cf-02/0x87 (EMR-SP A1) microcode from revision 0x21000291
up to 0x210002a9.
Resolves: RHEL-92231, RHEL-95245
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
|
||
|---|---|---|
| .gitignore | ||
| 01-microcode.conf | ||
| 06-2d-07_config | ||
| 06-2d-07_disclaimer | ||
| 06-2d-07_readme | ||
| 06-4e-03_config | ||
| 06-4e-03_disclaimer | ||
| 06-4e-03_readme | ||
| 06-4f-01_config | ||
| 06-4f-01_disclaimer | ||
| 06-4f-01_readme | ||
| 06-5e-03_config | ||
| 06-5e-03_disclaimer | ||
| 06-5e-03_readme | ||
| 06-8c-01_config | ||
| 06-8c-01_disclaimer | ||
| 06-8c-01_readme | ||
| 06-8e-9e-0x-0xca_config | ||
| 06-8e-9e-0x-0xca_disclaimer | ||
| 06-8e-9e-0x-0xca_readme | ||
| 06-8e-9e-0x-dell_config | ||
| 06-8e-9e-0x-dell_disclaimer | ||
| 06-8e-9e-0x-dell_readme | ||
| 06-8f-08_config | ||
| 06-8f-08_disclaimer | ||
| 06-8f-08_readme | ||
| 06-55-04_config | ||
| 06-55-04_disclaimer | ||
| 06-55-04_readme | ||
| 99-microcode-override.conf | ||
| 0001-releasenote.md-cleanup-eliminated-usage-of-U-0080.patch | ||
| 0002-releasenote.md-remove-excess-Release-Notes-headers.patch | ||
| 0003-releasenote.md-sort-the-entries-of-the-20230808-rele.patch | ||
| 0004-releasenote.md-fix-incorrect-platform-mask-for-RPL-H.patch | ||
| 0005-releasenote.md-fix-stepping-for-RPL-S.patch | ||
| 0006-releasenote.md-add-missing-06-ba-03-e0-to-the-new-mi.patch | ||
| 0007-releasenote.md-remove-the-duplicating-06-9e-0c-22-re.patch | ||
| 0008-releasenote.md-fix-old-revisions-for-06-8e-09-10-and.patch | ||
| 0009-releasenote.md-add-old-revisions-for-06-be-00-11-06-.patch | ||
| 0010-releasenote.md-eliminate-trailing-white-space.patch | ||
| 0011-releasenote.md-add-information-about-updates-and-rem.patch | ||
| 0012-releasenote.md-add-information-about-06-ba-08-microc.patch | ||
| 0013-releasenote.md-fix-whitespace-in-microcode-20240531-.patch | ||
| 0014-releasenote.md-use-None-for-the-empty-list-of-new-pl.patch | ||
| 0015-releasenote.md-add-missing-old-revision-in-microcode.patch | ||
| 0016-releasenote.md-use-new-lines-consistently.patch | ||
| 0017-releasenote.md-add-information-about-removal-of-CLX-.patch | ||
| 0101-releasenote.md-drop-Removed-Platforms-from-microcode.patch | ||
| check_caveats | ||
| codenames.list | ||
| dracut_99microcode_ctl-fw_dir_override_module_init.sh | ||
| gating.yaml | ||
| gen_provides.sh | ||
| gen_updates2.py | ||
| intel_config | ||
| intel_disclaimer | ||
| intel_readme | ||
| microcode_ctl.spec | ||
| microcode.service | ||
| README | ||
| README.caveats | ||
| reload_microcode | ||
| sources | ||
| update_ucode | ||
The microcode_ctl package contains microcode files (vendor-provided binary data
and/or code in proprietary format that affects behaviour of a device) for Intel
CPUs that may be loaded into the CPU during boot.
This directory contains information regarding various aspects of the provided
microcode files and their usage.
* LICENSE.intel-ucode
"license" file from the Intel x86 CPU microcode archive.
* README
This file.
* README.caveats
Caveats (mechanism for enabling/disabling usage of sets of microcode files
based on caveat configuration and user preferences) documentation.
Also contains general information about microcode update behaviour and links
with additional information about the relevant microarchitectural
vulnerabilities.
* README.intel-ucode
"README.md" file from the Intel x86 CPU microcode archive.
* RELEASE_NOTES.intel-ucode
"releasenote.md" file from the Intel x86 CPU microcode archive.
* SECURITY.intel-ucode
"security.md" file from the Intel x86 CPU microcode archive.
* SUMMARY.intel-ucode
Information about supplied microcode files extracted from their headers,
in a table form. Columns have the following meaning:
* "Path": path to the microcode file under one of the following directories:
* /usr/share/microcode_ctl/ucode_with_caveats/intel
* /usr/share/microcode_ctl/ucode_with_caveats
* /usr/share/microcode_ctl
* /lib/firmware
* /etc/firmware
* "Offset": offset of the microcode blob within the micocode file in bytes.
* "Ext. Offset": offset of the extended signature header within
the microcode file in bytes.
* "Data Size": size of microcode data in bytes. 0 means 2000 bytes.
* "Total Size": size of microcode blob in bytes, incuding headers.
0 means 2048 bytes.
* "CPUID": CPU ID signature (in format returned by the CPUID instruction).
* "Platform ID Mask": mask of suitable Platform IDs (provided in bits
52..50 of MSR 0x17).
* "Revision": microcode revision.
* "Date": microcode creation date.
* "Checksum": sum (in base 1<< 32) of all 32-bit values comprising
the microcode (from Offset up to Offset + Total Size).
* "Codenames": list of known CPU codenames associated with the CPUID
and Platform ID Mask combination.
Please refer to README.cavets, section "Microcode file structure"
for additional information regarding microcode header fields.
* caveats
Directory that contains readme files for each specific caveat.