Tool to transform and deploy CPU microcode update for x86.
- Update Intel CPU microcode to microcode-20250812 release
- Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000404
up to 0xd000410;
- Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x10002d0
up to 0x10002e0;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-07) from revision 0x2b000639 up to 0x2b000643;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-ucode/06-8f-07) from revision 0x2b000639 up to 0x2b000643;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-ucode/06-8f-07) from revision 0x2b000639 up to 0x2b000643;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision
0x2b000639 up to 0x2b000643;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-ucode/06-8f-07) from revision 0x2b000639 up to 0x2b000643;
- Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from
revision 0x2c0003f7 up to 0x2c000401;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-08) from revision 0x2b000639 up to 0x2b000643;
- Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
intel-ucode/06-8f-08) from revision 0x2c0003f7 up to 0x2c000401;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-ucode/06-8f-08) from revision 0x2b000639 up to 0x2b000643;
- Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from
revision 0x2c0003f7 up to 0x2c000401;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-ucode/06-8f-08) from revision 0x2b000639 up to 0x2b000643;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
intel-ucode/06-8f-08) from revision 0x2b000639 up to 0x2b000643;
- Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision
0x2c0003f7 up to 0x2c000401;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision
0x2b000639 up to 0x2b000643;
- Update of 06-aa-04/0xe6 (MTL-H/U C0) microcode from revision 0x24
up to 0x25;
- Update of 06-ad-01/0x20 (GNR-AP/SP H0) microcode from revision
0xa0000d1 up to 0xa000100;
- Update of 06-ad-01/0x95 (GNR-AP/SP B0) microcode from revision
0x10003a2 up to 0x10003d0;
- Update of 06-af-03/0x01 (SRF-SP C0) microcode from revision 0x3000341
up to 0x3000362;
- Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision
0x4128 up to 0x4129;
- Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
intel-ucode/06-ba-02) from revision 0x4128 up to 0x4129;
- Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) from
revision 0x4128 up to 0x4129;
- Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
intel-ucode/06-ba-03) from revision 0x4128 up to 0x4129;
- Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4128
up to 0x4129;
- Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) from
revision 0x4128 up to 0x4129;
- Update of 06-bd-01/0x80 (LNL B0) microcode from revision 0x11f up
to 0x123;
- Update of 06-c5-02/0x82 (ARL-H A1) microcode from revision 0x118 up
to 0x119;
- Update of 06-c6-02/0x82 (ARL-HX 8P/S B0) microcode (in
intel-ucode/06-c5-02) from revision 0x118 up to 0x119;
- Update of 06-c6-04/0x82 microcode (in intel-ucode/06-c5-02) from
revision 0x118 up to 0x119;
- Update of 06-ca-02/0x82 microcode (in intel-ucode/06-c5-02) from
revision 0x118 up to 0x119;
- Update of 06-c5-02/0x82 (ARL-H A1) microcode (in intel-ucode/06-c6-02)
from revision 0x118 up to 0x119;
- Update of 06-c6-02/0x82 (ARL-HX 8P/S B0) microcode from revision
0x118 up to 0x119;
- Update of 06-c6-04/0x82 microcode (in intel-ucode/06-c6-02) from
revision 0x118 up to 0x119;
- Update of 06-ca-02/0x82 microcode (in intel-ucode/06-c6-02) from
revision 0x118 up to 0x119;
- Update of 06-cf-01/0x87 (EMR-SP A0) microcode (in
intel-ucode/06-cf-02) from revision 0x210002a9 up to 0x210002b3;
- Update of 06-cf-02/0x87 (EMR-SP A1) microcode from revision 0x210002a9
up to 0x210002b3.
Resolves: RHEL-110661
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
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|---|---|---|
| .gitignore | ||
| 01-microcode.conf | ||
| 06-2d-07_config | ||
| 06-2d-07_disclaimer | ||
| 06-2d-07_readme | ||
| 06-4e-03_config | ||
| 06-4e-03_disclaimer | ||
| 06-4e-03_readme | ||
| 06-4f-01_config | ||
| 06-4f-01_disclaimer | ||
| 06-4f-01_readme | ||
| 06-5e-03_config | ||
| 06-5e-03_disclaimer | ||
| 06-5e-03_readme | ||
| 06-8c-01_config | ||
| 06-8c-01_disclaimer | ||
| 06-8c-01_readme | ||
| 06-8e-9e-0x-0xca_config | ||
| 06-8e-9e-0x-0xca_disclaimer | ||
| 06-8e-9e-0x-0xca_readme | ||
| 06-8e-9e-0x-dell_config | ||
| 06-8e-9e-0x-dell_disclaimer | ||
| 06-8e-9e-0x-dell_readme | ||
| 06-8f-08_config | ||
| 06-8f-08_disclaimer | ||
| 06-8f-08_readme | ||
| 06-55-04_config | ||
| 06-55-04_disclaimer | ||
| 06-55-04_readme | ||
| 99-microcode-override.conf | ||
| 0001-releasenote.md-cleanup-eliminated-usage-of-U-0080.patch | ||
| 0002-releasenote.md-remove-excess-Release-Notes-headers.patch | ||
| 0003-releasenote.md-sort-the-entries-of-the-20230808-rele.patch | ||
| 0004-releasenote.md-fix-incorrect-platform-mask-for-RPL-H.patch | ||
| 0005-releasenote.md-fix-stepping-for-RPL-S.patch | ||
| 0006-releasenote.md-add-missing-06-ba-03-e0-to-the-new-mi.patch | ||
| 0007-releasenote.md-remove-the-duplicating-06-9e-0c-22-re.patch | ||
| 0008-releasenote.md-fix-old-revisions-for-06-8e-09-10-and.patch | ||
| 0009-releasenote.md-add-old-revisions-for-06-be-00-11-06-.patch | ||
| 0010-releasenote.md-eliminate-trailing-white-space.patch | ||
| 0011-releasenote.md-add-information-about-updates-and-rem.patch | ||
| 0012-releasenote.md-add-information-about-06-ba-08-microc.patch | ||
| 0013-releasenote.md-fix-whitespace-in-microcode-20240531-.patch | ||
| 0014-releasenote.md-use-None-for-the-empty-list-of-new-pl.patch | ||
| 0015-releasenote.md-add-missing-old-revision-in-microcode.patch | ||
| 0016-releasenote.md-use-new-lines-consistently.patch | ||
| 0017-releasenote.md-add-information-about-removal-of-CLX-.patch | ||
| 0101-releasenote.md-drop-Removed-Platforms-from-microcode.patch | ||
| check_caveats | ||
| codenames.list | ||
| dracut_99microcode_ctl-fw_dir_override_module_init.sh | ||
| gating.yaml | ||
| gen_provides.sh | ||
| gen_updates2.py | ||
| intel_config | ||
| intel_disclaimer | ||
| intel_readme | ||
| microcode_ctl.spec | ||
| microcode.service | ||
| README | ||
| README.caveats | ||
| reload_microcode | ||
| sources | ||
| update_ucode | ||
The microcode_ctl package contains microcode files (vendor-provided binary data
and/or code in proprietary format that affects behaviour of a device) for Intel
CPUs that may be loaded into the CPU during boot.
This directory contains information regarding various aspects of the provided
microcode files and their usage.
* LICENSE.intel-ucode
"license" file from the Intel x86 CPU microcode archive.
* README
This file.
* README.caveats
Caveats (mechanism for enabling/disabling usage of sets of microcode files
based on caveat configuration and user preferences) documentation.
Also contains general information about microcode update behaviour and links
with additional information about the relevant microarchitectural
vulnerabilities.
* README.intel-ucode
"README.md" file from the Intel x86 CPU microcode archive.
* RELEASE_NOTES.intel-ucode
"releasenote.md" file from the Intel x86 CPU microcode archive.
* SECURITY.intel-ucode
"security.md" file from the Intel x86 CPU microcode archive.
* SUMMARY.intel-ucode
Information about supplied microcode files extracted from their headers,
in a table form. Columns have the following meaning:
* "Path": path to the microcode file under one of the following directories:
* /usr/share/microcode_ctl/ucode_with_caveats/intel
* /usr/share/microcode_ctl/ucode_with_caveats
* /usr/share/microcode_ctl
* /lib/firmware
* /etc/firmware
* "Offset": offset of the microcode blob within the micocode file in bytes.
* "Ext. Offset": offset of the extended signature header within
the microcode file in bytes.
* "Data Size": size of microcode data in bytes. 0 means 2000 bytes.
* "Total Size": size of microcode blob in bytes, incuding headers.
0 means 2048 bytes.
* "CPUID": CPU ID signature (in format returned by the CPUID instruction).
* "Platform ID Mask": mask of suitable Platform IDs (provided in bits
52..50 of MSR 0x17).
* "Revision": microcode revision.
* "Date": microcode creation date.
* "Checksum": sum (in base 1<< 32) of all 32-bit values comprising
the microcode (from Offset up to Offset + Total Size).
* "Codenames": list of known CPU codenames associated with the CPUID
and Platform ID Mask combination.
Please refer to README.cavets, section "Microcode file structure"
for additional information regarding microcode header fields.
* caveats
Directory that contains readme files for each specific caveat.