Tool to transform and deploy CPU microcode update for x86.
- Update Intel CPU microcode to microcode-20230808 release, addresses
CVE-2022-40982, CVE-2022-41804, CVE-2023-23908:
- Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode (in
intel-06-55-04/intel-ucode/06-55-04) from revision 0x2006f05 up
to 0x2007006;
- Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode (in
intel-06-8c-01/intel-ucode/06-8c-01) from revision 0xaa up to 0xac;
- Update of 06-8e-09/0xc0 (KBL-U/U 2+3e/Y H0/J1) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-8e-09) from revision 0xf2 up
to 0xf4;
- Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-8e-09) from revision 0xf2 up
to 0xf4;
- Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0a) from revision 0xf2 up
to 0xf4;
- Update of 06-8e-0b/0xd0 (WHL-U W0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0b) from revision 0xf2 up
to 0xf4;
- Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0)
microcode (in intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0c) from
revision 0xf6 up to 0xf8;
- Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-09) from revision 0xf2 up
to 0xf4;
- Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0a) from revision 0xf2 up
to 0xf4;
- Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0b) from revision 0xf2 up
to 0xf4;
- Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0c) from revision 0xf2 up
to 0xf4;
- Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode (in
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0d) from revision 0xf8 up
to 0xfa;
- Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000171
up to 0x1000181;
- Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003501
up to 0x4003604;
- Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision
0x5003501 up to 0x5003604;
- Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002601
up to 0x7002703;
- Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000390
up to 0xd0003a5;
- Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xba
up to 0xbc;
- Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x2a up
to 0x2c;
- Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x44 up
to 0x46;
- Update of 06-8f-04/0x10 microcode from revision 0x2c0001d1 up to
0x2c000271;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode from revision
0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
intel-ucode/06-8f-04) from revision 0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) from
revision 0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
intel-ucode/06-8f-04) from revision 0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-ucode/06-8f-04) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from
revision 0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision
0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b000461
up to 0x2b0004b1;
- Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) from
revision 0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
intel-ucode/06-8f-05) from revision 0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-ucode/06-8f-05) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from
revision 0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
intel-ucode/06-8f-06) from revision 0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-06/0x10 microcode from revision 0x2c0001d1 up to
0x2c000271;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b000461
up to 0x2b0004b1;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
intel-ucode/06-8f-06) from revision 0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-ucode/06-8f-06) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision
0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
intel-ucode/06-8f-07) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from
revision 0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
intel-ucode/06-8f-08) from revision 0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from
revision 0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
intel-ucode/06-8f-08) from revision 0x2b000461 up to 0x2b0004b1;
- Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision
0x2c0001d1 up to 0x2c000271;
- Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision
0x2b000461 up to 0x2b0004b1;
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision
0x2c up to 0x2e;
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
intel-ucode/06-97-02) from revision 0x2c up to 0x2e;
- Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
from revision 0x2c up to 0x2e;
- Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
from revision 0x2c up to 0x2e;
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
intel-ucode/06-97-05) from revision 0x2c up to 0x2e;
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x2c
up to 0x2e;
- Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
from revision 0x2c up to 0x2e;
- Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
from revision 0x2c up to 0x2e;
- Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision
0x42a up to 0x42c;
- Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in
intel-ucode/06-9a-03) from revision 0x42a up to 0x42c;
- Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in
intel-ucode/06-9a-04) from revision 0x42a up to 0x42c;
- Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x42a
up to 0x42c;
- Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf6 up
to 0xf8;
- Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf6
up to 0xf8;
- Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf6
up to 0xf8;
- Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf6
up to 0xf8;
- Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision
0xf6 up to 0xf8;
- Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x58 up
to 0x59;
- Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x113 up
to 0x119;
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
intel-ucode/06-bf-02) from revision 0x2c up to 0x2e;
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
intel-ucode/06-bf-02) from revision 0x2c up to 0x2e;
- Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x2c up
to 0x2e;
- Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02)
from revision 0x2c up to 0x2e;
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
intel-ucode/06-bf-05) from revision 0x2c up to 0x2e;
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
intel-ucode/06-bf-05) from revision 0x2c up to 0x2e;
- Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05)
from revision 0x2c up to 0x2e;
- Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x2c up
to 0x2e;
- Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision
0x4112 up to 0x4119 (old pf 0xc0);
- Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
intel-ucode/06-ba-02) from revision 0x4112 up to 0x4119 (old pf 0xc0);
- Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
intel-ucode/06-ba-03) from revision 0x4112 up to 0x4119 (old pf 0xc0);
- Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4112
up to 0x4119 (old pf 0xc0);
- Update of 06-be-00/0x11 (ADL-N A0) microcode from revision 0x10 up
to 0x11 (old pf 0x1).
* .gitignore: Replace /microcode-20230516.tar.gz entry
with /microcode-20230808.tar.gz.
* 0001-releasenote.md-eliminate-usage-of-U-0080.patch: New file.
* 0002-releasenote.md-eliminate-most-of-the-trailing-whites.patch: Likewise.
* 0003-releasenote.md-remove-excess-Release-Notes-headers.patch: Likewise.
* 0004-releasenote.md-sort-the-entries-of-the-20230808-rele.patch: Likewise.
* 0005-releasenote.md-fix-incorrect-platform-mask-for-RPL-H.patch: Likewise.
* 0006-releasenote.md-fix-stepping-for-RPL-S.patch: Likewise.
* 0007-releasenote.md-add-missing-06-ba-03-e0-to-the-new-mi.patch: Likewise.
* 0008-releasenote.md-remove-the-duplicating-06-9e-0c-22-re.patch: Likewise.
* 0009-releasenote.md-fix-old-revisions-for-06-8e-09-10-and.patch: Likewise.
* 0010-releasenote.md-add-old-revisions-for-06-be-00-11-06-.patch: Likewise.
* 06-55-04_readme: Add a checksum for revision 0x2007006.
* 06-8c-01_readme: Add a checksum for revision 0xac.
* 06-8e-9e-0x-0xca_readme: Add a checksum for revision 0xf4 of 06-9e-0d
microcode, a part of microcode-20221108 release, and checksums revision
0xf4/0xf8/0xfa, fix revision of 06-9e-0d micorocde (0xf8 instead 0xf2
in microcode-20230516).
* 06-8e-9e-0x-dell_readme: Likewise.
* microcode_ctl.spec (intel_ucode_version): Bump to 20230808.
(Patch0001, Patch0002, Patch0003, Patch0004, Patch0005, Patch0006, Patch0007,
Patch0008, Patch0009, Patch0010): New patches.
(%prep): Apply them.
(%changelog): Add a record.
* sources: Replace microcode-20230516.tar.gz record with
microcode-20230808.tar.gz.
Resolves: #2223992
Signed-off-by: Eugene Syromiatnikov <esyr@redhat.com>
|
||
|---|---|---|
| .gitignore | ||
| 01-microcode.conf | ||
| 06-2d-07_config | ||
| 06-2d-07_disclaimer | ||
| 06-2d-07_readme | ||
| 06-4e-03_config | ||
| 06-4e-03_disclaimer | ||
| 06-4e-03_readme | ||
| 06-4f-01_config | ||
| 06-4f-01_disclaimer | ||
| 06-4f-01_readme | ||
| 06-5e-03_config | ||
| 06-5e-03_disclaimer | ||
| 06-5e-03_readme | ||
| 06-8c-01_config | ||
| 06-8c-01_disclaimer | ||
| 06-8c-01_readme | ||
| 06-8e-9e-0x-0xca_config | ||
| 06-8e-9e-0x-0xca_disclaimer | ||
| 06-8e-9e-0x-0xca_readme | ||
| 06-8e-9e-0x-dell_config | ||
| 06-8e-9e-0x-dell_disclaimer | ||
| 06-8e-9e-0x-dell_readme | ||
| 06-55-04_config | ||
| 06-55-04_disclaimer | ||
| 06-55-04_readme | ||
| 99-microcode-override.conf | ||
| 0001-releasenote.md-eliminate-usage-of-U-0080.patch | ||
| 0002-releasenote.md-eliminate-most-of-the-trailing-whites.patch | ||
| 0003-releasenote.md-remove-excess-Release-Notes-headers.patch | ||
| 0004-releasenote.md-sort-the-entries-of-the-20230808-rele.patch | ||
| 0005-releasenote.md-fix-incorrect-platform-mask-for-RPL-H.patch | ||
| 0006-releasenote.md-fix-stepping-for-RPL-S.patch | ||
| 0007-releasenote.md-add-missing-06-ba-03-e0-to-the-new-mi.patch | ||
| 0008-releasenote.md-remove-the-duplicating-06-9e-0c-22-re.patch | ||
| 0009-releasenote.md-fix-old-revisions-for-06-8e-09-10-and.patch | ||
| 0010-releasenote.md-add-old-revisions-for-06-be-00-11-06-.patch | ||
| check_caveats | ||
| codenames.list | ||
| dracut_99microcode_ctl-fw_dir_override_module_init.sh | ||
| gating.yaml | ||
| gen_provides.sh | ||
| gen_updates2.py | ||
| intel_config | ||
| intel_disclaimer | ||
| intel_readme | ||
| microcode_ctl.spec | ||
| microcode.service | ||
| README | ||
| README.caveats | ||
| reload_microcode | ||
| sources | ||
| update_ucode | ||
The microcode_ctl package contains microcode files (vendor-provided binary data
and/or code in proprietary format that affects behaviour of a device) for Intel
CPUs that may be loaded into the CPU during boot.
This directory contains information regarding various aspects of the provided
microcode files and their usage.
* LICENSE.intel-ucode
"license" file from the Intel x86 CPU microcode archive.
* README
This file.
* README.caveats
Caveats (mechanism for enabling/disabling usage of sets of microcode files
based on caveat configuration and user preferences) documentation.
Also contains general information about microcode update behaviour and links
with additional information about the relevant microarchitectural
vulnerabilities.
* README.intel-ucode
"README.md" file from the Intel x86 CPU microcode archive.
* RELEASE_NOTES.intel-ucode
"releasenote.md" file from the Intel x86 CPU microcode archive.
* SECURITY.intel-ucode
"security.md" file from the Intel x86 CPU microcode archive.
* SUMMARY.intel-ucode
Information about supplied microcode files extracted from their headers,
in a table form. Columns have the following meaning:
* "Path": path to the microcode file under one of the following directories:
* /usr/share/microcode_ctl/ucode_with_caveats/intel
* /usr/share/microcode_ctl/ucode_with_caveats
* /usr/share/microcode_ctl
* /lib/firmware
* /etc/firmware
* "Offset": offset of the microcode blob within the micocode file in bytes.
* "Ext. Offset": offset of the extended signature header within
the microcode file in bytes.
* "Data Size": size of microcode data in bytes. 0 means 2000 bytes.
* "Total Size": size of microcode blob in bytes, incuding headers.
0 means 2048 bytes.
* "CPUID": CPU ID signature (in format returned by the CPUID instruction).
* "Platform ID Mask": mask of suitable Platform IDs (provided in bits
52..50 of MSR 0x17).
* "Revision": microcode revision.
* "Date": microcode creation date.
* "Checksum": sum (in base 1<< 32) of all 32-bit values comprising
the microcode (from Offset up to Offset + Total Size).
* "Codenames": list of known CPU codenames associated with the CPUID
and Platform ID Mask combination.
Please refer to README.cavets, section "Microcode file structure"
for additional information regarding microcode header fields.
* caveats
Directory that contains readme files for each specific caveat.