Tool to transform and deploy CPU microcode update for x86.
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Eugene Syromiatnikov 4f40bcbef1 Update Intel CPU microcode to microcode-20220510 release
- Update Intel CPU microcode to microcode-20220510 release, addresses
  CVE-2022-0005, CVE-2022-21131, CVE-2022-21136, CVE-2022-21151 (#2086743):
  - Addition of 06-97-02/0x03 (ADL-HX C0) microcode at revision 0x1f;
  - Addition of 06-97-05/0x03 (ADL-S 6+0 K0) microcode (in
    intel-ucode/06-97-02) at revision 0x1f;
  - Addition of 06-bf-02/0x03 (ADL C0) microcode (in intel-ucode/06-97-02)
    at revision 0x1f;
  - Addition of 06-bf-05/0x03 (ADL C0) microcode (in intel-ucode/06-97-02)
    at revision 0x1f;
  - Addition of 06-97-02/0x03 (ADL-HX C0) microcode (in
    intel-ucode/06-97-05) at revision 0x1f;
  - Addition of 06-97-05/0x03 (ADL-S 6+0 K0) microcode at revision 0x1f;
  - Addition of 06-bf-02/0x03 (ADL C0) microcode (in intel-ucode/06-97-05)
    at revision 0x1f;
  - Addition of 06-bf-05/0x03 (ADL C0) microcode (in intel-ucode/06-97-05)
    at revision 0x1f;
  - Addition of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode at
    revision 0x41c;
  - Addition of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in
    intel-ucode/06-9a-03) at revision 0x41c;
  - Addition of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in
    intel-ucode/06-9a-04) at revision 0x41c;
  - Addition of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode at revision 0x41c;
  - Addition of 06-97-02/0x03 (ADL-HX C0) microcode (in
    intel-ucode/06-bf-02) at revision 0x1f;
  - Addition of 06-97-05/0x03 (ADL-S 6+0 K0) microcode (in
    intel-ucode/06-bf-02) at revision 0x1f;
  - Addition of 06-bf-02/0x03 (ADL C0) microcode at revision 0x1f;
  - Addition of 06-bf-05/0x03 (ADL C0) microcode (in intel-ucode/06-bf-02)
    at revision 0x1f;
  - Addition of 06-97-02/0x03 (ADL-HX C0) microcode (in
    intel-ucode/06-bf-05) at revision 0x1f;
  - Addition of 06-97-05/0x03 (ADL-S 6+0 K0) microcode (in
    intel-ucode/06-bf-05) at revision 0x1f;
  - Addition of 06-bf-02/0x03 (ADL C0) microcode (in intel-ucode/06-bf-05)
    at revision 0x1f;
  - Addition of 06-bf-05/0x03 (ADL C0) microcode at revision 0x1f;
  - Update of 06-4e-03/0xc0 (SKL-U/U 2+3e/Y D0/K1) microcode (in
    intel-06-4e-03/intel-ucode/06-4e-03) from revision 0xec up to 0xf0;
  - Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode (in
    intel-06-55-04/intel-ucode/06-55-04) from revision 0x2006c0a up
    to 0x2006d05;
  - Update of 06-5e-03/0x36 (SKL-H/S/Xeon E3 N0/R0/S0) microcode (in
    intel-06-5e-03/intel-ucode/06-5e-03) from revision 0xec up to 0xf0;
  - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode (in
    intel-06-8c-01/intel-ucode/06-8c-01) from revision 0x9a up to 0xa4;
  - Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode (in
    intel-06-8e-9e-0x-dell/intel-ucode/06-8e-09) from revision 0xec up
    to 0xf0;
  - Update of 06-8e-09/0xc0 (KBL-U/U 2+3e/Y H0/J1) microcode (in
    intel-06-8e-9e-0x-dell/intel-ucode/06-8e-09) from revision 0xec up
    to 0xf0;
  - Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode (in
    intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0a) from revision 0xec up
    to 0xf0;
  - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode (in
    intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0b) from revision 0xec up
    to 0xf0;
  - Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0)
    microcode (in intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0c) from
    revision 0xec up to 0xf0;
  - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode (in
    intel-06-8e-9e-0x-dell/intel-ucode/06-9e-09) from revision 0xec up
    to 0xf0;
  - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode (in
    intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0a) from revision 0xec up
    to 0xf0;
  - Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode (in
    intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0b) from revision 0xec up
    to 0xf0;
  - Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode (in
    intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0c) from revision 0xec up
    to 0xf0;
  - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode (in
    intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0d) from revision 0xec up
    to 0xf0;
  - Update of 06-37-09/0x0f (VLV D0) microcode from revision 0x90c up
    to 0x90d;
  - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x100015c
    up to 0x100015d;
  - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400320a
    up to 0x4003302;
  - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision
    0x500320a up to 0x5003302;
  - Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002402
    up to 0x7002501;
  - Update of 06-5c-09/0x03 (APL D0) microcode from revision 0x46 up
    to 0x48;
  - Update of 06-5c-0a/0x03 (APL B1/F1) microcode from revision 0x24 up
    to 0x28;
  - Update of 06-5f-01/0x01 (DNV B0) microcode from revision 0x36 up
    to 0x38;
  - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000331
    up to 0xd000363;
  - Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x38 up
    to 0x3a;
  - Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x1c up
    to 0x1e;
  - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xa8
    up to 0xb0;
  - Update of 06-8a-01/0x10 (LKF B2/B3) microcode from revision 0x2d up
    to 0x31;
  - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x22 up
    to 0x26;
  - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x3c up
    to 0x3e;
  - Update of 06-96-01/0x01 (EHL B1) microcode from revision 0x15 up
    to 0x16;
  - Update of 06-9c-00/0x01 (JSL A0/A1) microcode from revision 0x2400001f
    up to 0x24000023;
  - Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xec up
    to 0xf0;
  - Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xec
    up to 0xf0;
  - Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xee
    up to 0xf0;
  - Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xea
    up to 0xf0;
  - Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision
    0xec up to 0xf0;
  - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x50 up
    to 0x53.

* .gitignore: Replace /microcode-20220207.tar.gz entry with
/microcode-20220510.tar.gz.
* 0001-releasenote.md-changes-summary-fixes-for-microcode-2.patch: New
patch.
* 06-4e-03_readme: Add a checksum for revision 0xf0, add the link
to the 2022.1 IPU KB article.
* 06-55-04_readme: Add a checksum for revision 0x2006d05, add the link
to the 2022.1 IPU KB article.
* 06-5e-03_readme: Add a checksum for revision 0xf0, add the link
to the 2022.1 IPU KB article.
* 06-8c-01_readme: Add a checksum for revision 0xa4, add the link
to the 2022.1 IPU KB article.
* 06-8e-9e-0x-0xca_readme: Add checksums for revision 0xf0, add the link
to the 2022.1 IPU KB article.
* 06-8e-9e-0x-dell_readme: Likewise.
* codenames.list: Add an entry for CPU signatures 90672 (ADL-S/HX C0),
90675 (ADL-S K0), 906a3 (ADL-P L0, ADL-U R0), 906a4 (ADL-P R0),
b06f2 (ADL C0), and b06f5 (ADL C0).
* microcode_ctl.spec (intel_ucode_version): Bump to 20220510.
(Patch1001): New patch (fixes in releasenote.md).
(%prep): Apply it.
(%changelog): Add a record.
* sources: Replace microcode-20220207.tar.gz record with
microcode-20220510.tar.gz.

Resolves: #2090248
Resolves: #2090261
Resolves: #2086751
Resolves: #2040069
Signed-off-by: Eugene Syromiatnikov <esyr@redhat.com>
2022-06-14 18:04:13 +02:00
.gitignore Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
01-microcode.conf Import RHEL packaging 2021-07-26 18:44:11 +02:00
0001-releasenote.md-changes-summary-fixes-for-microcode-2.patch Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
06-2d-07_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-2d-07_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-2d-07_readme Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-4e-03_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-4e-03_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-4e-03_readme Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
06-4f-01_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-4f-01_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-4f-01_readme Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-5e-03_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-5e-03_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-5e-03_readme Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
06-8c-01_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-8c-01_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-8c-01_readme Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
06-8e-9e-0x-0xca_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-8e-9e-0x-0xca_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-8e-9e-0x-0xca_readme Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
06-8e-9e-0x-dell_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-8e-9e-0x-dell_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-8e-9e-0x-dell_readme Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
06-55-04_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-55-04_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-55-04_readme Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
99-microcode-override.conf Import RHEL packaging 2021-07-26 18:44:11 +02:00
README Import RHEL packaging 2021-07-26 18:44:11 +02:00
README.caveats Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
check_caveats Import RHEL packaging 2021-07-26 18:44:11 +02:00
codenames.list Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
dracut_99microcode_ctl-fw_dir_override_module_init.sh Import RHEL packaging 2021-07-26 18:44:11 +02:00
gating.yaml add RHEL9 gating.yaml file 2021-06-30 14:42:43 -05:00
gen_provides.sh gen_provides.sh: make microcode header decoding endianness-agnostic 2021-07-26 23:18:05 +02:00
gen_updates2.py gen_updates2.py: consistently specify endianness in struct.unpack formats 2021-07-26 23:18:05 +02:00
intel_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
intel_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
intel_readme Import RHEL packaging 2021-07-26 18:44:11 +02:00
microcode.service Import RHEL packaging 2021-07-26 18:44:11 +02:00
microcode_ctl.spec Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
reload_microcode Import RHEL packaging 2021-07-26 18:44:11 +02:00
sources Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
update_ucode Import RHEL packaging 2021-07-26 18:44:11 +02:00

README

The microcode_ctl package contains microcode files (vendor-provided binary data
and/or code in proprietary format that affects behaviour of a device) for Intel
CPUs that may be loaded into the CPU during boot.

This directory contains information regarding various aspects of the provided
microcode files and their usage.

 * LICENSE.intel-ucode
   "license" file from the Intel x86 CPU microcode archive.
 * README
   This file.
 * README.caveats
   Caveats (mechanism for enabling/disabling usage of sets of microcode files
   based on caveat configuration and user preferences) documentation.
   Also contains general information about microcode update behaviour and links
   with additional information about the relevant microarchitectural
   vulnerabilities.
 * README.intel-ucode
   "README.md" file from the Intel x86 CPU microcode archive.
 * RELEASE_NOTES.intel-ucode
   "releasenote.md" file from the Intel x86 CPU microcode archive.
 * SECURITY.intel-ucode
   "security.md" file from the Intel x86 CPU microcode archive.
 * SUMMARY.intel-ucode
   Information about supplied microcode files extracted from their headers,
   in a table form.  Columns have the following meaning:
    * "Path": path to the microcode file under one of the following directories:
       * /usr/share/microcode_ctl/ucode_with_caveats/intel
       * /usr/share/microcode_ctl/ucode_with_caveats
       * /usr/share/microcode_ctl
       * /lib/firmware
       * /etc/firmware
    * "Offset": offset of the microcode blob within the micocode file in bytes.
    * "Ext. Offset": offset of the extended signature header within
      the microcode file in bytes.
    * "Data Size": size of microcode data in bytes.  0 means 2000 bytes.
    * "Total Size": size of microcode blob in bytes, incuding headers.
      0 means 2048 bytes.
    * "CPUID": CPU ID signature (in format returned by the CPUID instruction).
    * "Platform ID Mask": mask of suitable Platform IDs (provided in bits
      52..50 of MSR 0x17).
    * "Revision": microcode revision.
    * "Date": microcode creation date.
    * "Checksum": sum (in base 1<< 32) of all 32-bit values comprising
      the microcode (from Offset up to Offset + Total Size).
    * "Codenames": list of known CPU codenames associated with the CPUID
      and Platform ID Mask combination.
   Please refer to README.cavets, section "Microcode file structure"
   for additional information regarding microcode header fields.
 * caveats
   Directory that contains readme files for each specific caveat.