Tool to transform and deploy CPU microcode update for x86.
3d9fdc9449
- Update Intel CPU microcode to microcode-20231009 release, addresses CVE-2023-23583 - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode (in intel-06-8c-01/intel-ucode/06-8c-01) from revision 0xac up to 0xb4; - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd0003a5 up to 0xd0003b9; - Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x1000230 up to 0x1000268; - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xbc up to 0xc2; - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x2c up to 0x34; - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x46 up to 0x4e; - Update of 06-8f-04/0x10 microcode from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-04) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-04) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-05) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-06) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-06/0x10 microcode from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-06) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-08) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision 0x2c000271 up to 0x2c000290; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision 0x2b0004b1 up to 0x2b0004d0; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision 0x2e up to 0x32; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-97-02) from revision 0x2e up to 0x32; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x2e up to 0x32; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x2e up to 0x32; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x2e up to 0x32; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x2e up to 0x32; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x2e up to 0x32; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x2e up to 0x32; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision 0x42c up to 0x430; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in intel-ucode/06-9a-03) from revision 0x42c up to 0x430; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in intel-ucode/06-9a-04) from revision 0x42c up to 0x430; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x42c up to 0x430; - Update of 06-9a-04/0x40 (AZB A0) microcode from revision 0x4 up to 0x5; - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x59 up to 0x5d; - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x119 up to 0x11d; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision 0x4119 up to 0x411c; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-02) from revision 0x4119 up to 0x411c; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-03) from revision 0x4119 up to 0x411c; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4119 up to 0x411c; - Update of 06-be-00/0x11 (ADL-N A0) microcode from revision 0x11 up to 0x12; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-02) from revision 0x2e up to 0x32; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-02) from revision 0x2e up to 0x32; - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x2e up to 0x32; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) from revision 0x2e up to 0x32; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x2e up to 0x32; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-05) from revision 0x2e up to 0x32; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) from revision 0x2e up to 0x32; - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x2e up to 0x32. * .gitignore: Replace /microcode-20230808.tar.gz entry with /microcode-20231009.tar.gz. * 0011-releasenote.md-add-stub-release-notes-for-microcode-.patch: New file. * 06-8c-01_readme: Add a checksum for revision 0xb4. * microcode_ctl.spec (intel_ucode_version): Bump to 20231009. (Release): Reset to 1. (Patch0011): New patch. (%prep): Apply it. (%changelog): Add a record. * sources: Replace microcode-20230808.tar.gz record with microcode-20231009.tar.gz. Resolves: RHEL-41108 Signed-off-by: Eugene Syromiatnikov <esyr@redhat.com> |
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.gitignore | ||
01-microcode.conf | ||
06-2d-07_config | ||
06-2d-07_disclaimer | ||
06-2d-07_readme | ||
06-4e-03_config | ||
06-4e-03_disclaimer | ||
06-4e-03_readme | ||
06-4f-01_config | ||
06-4f-01_disclaimer | ||
06-4f-01_readme | ||
06-5e-03_config | ||
06-5e-03_disclaimer | ||
06-5e-03_readme | ||
06-8c-01_config | ||
06-8c-01_disclaimer | ||
06-8c-01_readme | ||
06-8e-9e-0x-0xca_config | ||
06-8e-9e-0x-0xca_disclaimer | ||
06-8e-9e-0x-0xca_readme | ||
06-8e-9e-0x-dell_config | ||
06-8e-9e-0x-dell_disclaimer | ||
06-8e-9e-0x-dell_readme | ||
06-55-04_config | ||
06-55-04_disclaimer | ||
06-55-04_readme | ||
99-microcode-override.conf | ||
0001-releasenote.md-eliminate-usage-of-U-0080.patch | ||
0002-releasenote.md-eliminate-most-of-the-trailing-whites.patch | ||
0003-releasenote.md-remove-excess-Release-Notes-headers.patch | ||
0004-releasenote.md-sort-the-entries-of-the-20230808-rele.patch | ||
0005-releasenote.md-fix-incorrect-platform-mask-for-RPL-H.patch | ||
0006-releasenote.md-fix-stepping-for-RPL-S.patch | ||
0007-releasenote.md-add-missing-06-ba-03-e0-to-the-new-mi.patch | ||
0008-releasenote.md-remove-the-duplicating-06-9e-0c-22-re.patch | ||
0009-releasenote.md-fix-old-revisions-for-06-8e-09-10-and.patch | ||
0010-releasenote.md-add-old-revisions-for-06-be-00-11-06-.patch | ||
0011-releasenote.md-add-stub-release-notes-for-microcode-.patch | ||
check_caveats | ||
codenames.list | ||
dracut_99microcode_ctl-fw_dir_override_module_init.sh | ||
gating.yaml | ||
gen_provides.sh | ||
gen_updates2.py | ||
intel_config | ||
intel_disclaimer | ||
intel_readme | ||
microcode_ctl.spec | ||
microcode.service | ||
README | ||
README.caveats | ||
reload_microcode | ||
sources | ||
update_ucode |
The microcode_ctl package contains microcode files (vendor-provided binary data and/or code in proprietary format that affects behaviour of a device) for Intel CPUs that may be loaded into the CPU during boot. This directory contains information regarding various aspects of the provided microcode files and their usage. * LICENSE.intel-ucode "license" file from the Intel x86 CPU microcode archive. * README This file. * README.caveats Caveats (mechanism for enabling/disabling usage of sets of microcode files based on caveat configuration and user preferences) documentation. Also contains general information about microcode update behaviour and links with additional information about the relevant microarchitectural vulnerabilities. * README.intel-ucode "README.md" file from the Intel x86 CPU microcode archive. * RELEASE_NOTES.intel-ucode "releasenote.md" file from the Intel x86 CPU microcode archive. * SECURITY.intel-ucode "security.md" file from the Intel x86 CPU microcode archive. * SUMMARY.intel-ucode Information about supplied microcode files extracted from their headers, in a table form. Columns have the following meaning: * "Path": path to the microcode file under one of the following directories: * /usr/share/microcode_ctl/ucode_with_caveats/intel * /usr/share/microcode_ctl/ucode_with_caveats * /usr/share/microcode_ctl * /lib/firmware * /etc/firmware * "Offset": offset of the microcode blob within the micocode file in bytes. * "Ext. Offset": offset of the extended signature header within the microcode file in bytes. * "Data Size": size of microcode data in bytes. 0 means 2000 bytes. * "Total Size": size of microcode blob in bytes, incuding headers. 0 means 2048 bytes. * "CPUID": CPU ID signature (in format returned by the CPUID instruction). * "Platform ID Mask": mask of suitable Platform IDs (provided in bits 52..50 of MSR 0x17). * "Revision": microcode revision. * "Date": microcode creation date. * "Checksum": sum (in base 1<< 32) of all 32-bit values comprising the microcode (from Offset up to Offset + Total Size). * "Codenames": list of known CPU codenames associated with the CPUID and Platform ID Mask combination. Please refer to README.cavets, section "Microcode file structure" for additional information regarding microcode header fields. * caveats Directory that contains readme files for each specific caveat.