Tool to transform and deploy CPU microcode update for x86.
308f3271d0
- Update Intel CPU microcode to microcode-20230214 release, addresses CVE-2022-21216, CVE-2022-33196, CVE-2022-33972, CVE-2022-38090: - Addition of 06-6c-01/0x10 (ICL-D B0) microcode at revision 0x1000211; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode at revision 0x2b000181; - Addition of 06-8f-04/0x10 microcode at revision 0x2c000170; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-04) at revision 0x2b000181; - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-04) at revision 0x2c000170; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-04) at revision 0x2b000181; - Addition of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) at revision 0x2c000170; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-04) at revision 0x2b000181; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-04) at revision 0x2b000181; - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-04) at revision 0x2c000170; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-05) at revision 0x2b000181; - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) at revision 0x2c000170; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode at revision 0x2b000181; - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode at revision 0x2c000170; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-05) at revision 0x2b000181; - Addition of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) at revision 0x2c000170; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-05) at revision 0x2b000181; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-05) at revision 0x2b000181; - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-05) at revision 0x2c000170; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-06) at revision 0x2b000181; - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) at revision 0x2c000170; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-06) at revision 0x2b000181; - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-06) at revision 0x2c000170; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode at revision 0x2b000181; - Addition of 06-8f-06/0x10 microcode at revision 0x2c000170; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-06) at revision 0x2b000181; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-06) at revision 0x2b000181; - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-06) at revision 0x2c000170; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-07) at revision 0x2b000181; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-07) at revision 0x2b000181; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-07) at revision 0x2b000181; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode at revision 0x2b000181; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-07) at revision 0x2b000181; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-08) at revision 0x2b000181; - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) at revision 0x2c000170; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-08) at revision 0x2b000181; - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-08) at revision 0x2c000170; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-08) at revision 0x2b000181; - Addition of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) at revision 0x2c000170; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-08) at revision 0x2b000181; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode at revision 0x2b000181; - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode at revision 0x2c000170; - Addition of 06-b7-01/0x32 (RPL-S S0) microcode at revision 0x112; - Addition of 06-ba-02/0xc0 microcode at revision 0x410e; - Addition of 06-ba-03/0xc0 microcode (in intel-ucode/06-ba-02) at revision 0x410e; - Addition of 06-ba-02/0xc0 microcode (in intel-ucode/06-ba-03) at revision 0x410e; - Addition of 06-ba-03/0xc0 microcode at revision 0x410e; - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode (in intel-06-8c-01/intel-ucode/06-8c-01) from revision 0xa4 up to 0xa6; - Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0) microcode (in intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0c) from revision 0xf0 up to 0xf4; - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode (in intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0d) from revision 0xf0 up to 0xf4; - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x100015e up to 0x1000161; - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003302 up to 0x4003303; - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision 0x5003302 up to 0x5003303; - Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002501 up to 0x7002503; - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000375 up to 0xd000389; - Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x3c up to 0x3e; - Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x20 up to 0x22; - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xb2 up to 0xb8; - Update of 06-8a-01/0x10 (LKF B2/B3) microcode from revision 0x31 up to 0x32; - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x40 up to 0x42; - Update of 06-96-01/0x01 (EHL B1) microcode from revision 0x16 up to 0x17; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-97-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision 0x421 up to 0x429; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in intel-ucode/06-9a-03) from revision 0x421 up to 0x429; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in intel-ucode/06-9a-04) from revision 0x421 up to 0x429; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x421 up to 0x429; - Update of 06-9c-00/0x01 (JSL A0/A1) microcode from revision 0x24000023 up to 0x24000024; - Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf0 up to 0xf4; - Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf0 up to 0xf4; - Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf0 up to 0xf4; - Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf0 up to 0xf4; - Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision 0xf0 up to 0xf4; - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x54 up to 0x57; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x22 up to 0x2c (old pf 0x3). * .gitignore: Replace /microcode-20220809.tar.gz entry with /microcode-20230214.tar.gz. * codenames.list: Add entries for CPU signatures 606c1 (ICL-D B0), 806f4 (SPR-SP E0/S1), 806f5 (SPR-HBM B1, SPR-SP E2), 806f6 (SPR-SP E3), 806f7 (SPR-SP E4/S2), 806f8 (SPR-HBM B3, SPR-SP E5/S3), b0671 (RPL-S S0), 806a2 (SPR-P 6+8/H 6+8 J0), and 806a3 (SPR-U 2+8 Q0). * microcode_ctl.spec (intel_ucode_version): Bump to 20230214. (Release): Reset to 1. (%changelog): Add a record. * sources: Replace microcode-20220809.tar.gz record with microcode-20230214.tar.gz. Resolves: #2171234 Resolves: #2171259 Signed-off-by: Eugene Syromiatnikov <esyr@redhat.com> |
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.gitignore | ||
01-microcode.conf | ||
06-2d-07_config | ||
06-2d-07_disclaimer | ||
06-2d-07_readme | ||
06-4e-03_config | ||
06-4e-03_disclaimer | ||
06-4e-03_readme | ||
06-4f-01_config | ||
06-4f-01_disclaimer | ||
06-4f-01_readme | ||
06-5e-03_config | ||
06-5e-03_disclaimer | ||
06-5e-03_readme | ||
06-8c-01_config | ||
06-8c-01_disclaimer | ||
06-8c-01_readme | ||
06-8e-9e-0x-0xca_config | ||
06-8e-9e-0x-0xca_disclaimer | ||
06-8e-9e-0x-0xca_readme | ||
06-8e-9e-0x-dell_config | ||
06-8e-9e-0x-dell_disclaimer | ||
06-8e-9e-0x-dell_readme | ||
06-55-04_config | ||
06-55-04_disclaimer | ||
06-55-04_readme | ||
99-microcode-override.conf | ||
check_caveats | ||
codenames.list | ||
dracut_99microcode_ctl-fw_dir_override_module_init.sh | ||
gating.yaml | ||
gen_provides.sh | ||
gen_updates2.py | ||
intel_config | ||
intel_disclaimer | ||
intel_readme | ||
microcode_ctl.spec | ||
microcode.service | ||
README | ||
README.caveats | ||
reload_microcode | ||
sources | ||
update_ucode |
The microcode_ctl package contains microcode files (vendor-provided binary data and/or code in proprietary format that affects behaviour of a device) for Intel CPUs that may be loaded into the CPU during boot. This directory contains information regarding various aspects of the provided microcode files and their usage. * LICENSE.intel-ucode "license" file from the Intel x86 CPU microcode archive. * README This file. * README.caveats Caveats (mechanism for enabling/disabling usage of sets of microcode files based on caveat configuration and user preferences) documentation. Also contains general information about microcode update behaviour and links with additional information about the relevant microarchitectural vulnerabilities. * README.intel-ucode "README.md" file from the Intel x86 CPU microcode archive. * RELEASE_NOTES.intel-ucode "releasenote.md" file from the Intel x86 CPU microcode archive. * SECURITY.intel-ucode "security.md" file from the Intel x86 CPU microcode archive. * SUMMARY.intel-ucode Information about supplied microcode files extracted from their headers, in a table form. Columns have the following meaning: * "Path": path to the microcode file under one of the following directories: * /usr/share/microcode_ctl/ucode_with_caveats/intel * /usr/share/microcode_ctl/ucode_with_caveats * /usr/share/microcode_ctl * /lib/firmware * /etc/firmware * "Offset": offset of the microcode blob within the micocode file in bytes. * "Ext. Offset": offset of the extended signature header within the microcode file in bytes. * "Data Size": size of microcode data in bytes. 0 means 2000 bytes. * "Total Size": size of microcode blob in bytes, incuding headers. 0 means 2048 bytes. * "CPUID": CPU ID signature (in format returned by the CPUID instruction). * "Platform ID Mask": mask of suitable Platform IDs (provided in bits 52..50 of MSR 0x17). * "Revision": microcode revision. * "Date": microcode creation date. * "Checksum": sum (in base 1<< 32) of all 32-bit values comprising the microcode (from Offset up to Offset + Total Size). * "Codenames": list of known CPU codenames associated with the CPUID and Platform ID Mask combination. Please refer to README.cavets, section "Microcode file structure" for additional information regarding microcode header fields. * caveats Directory that contains readme files for each specific caveat.