Tool to transform and deploy CPU microcode update for x86.
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Eugene Syromiatnikov 0960594467 Update Intel CPU microcode to microcode-20241112 release
- Update Intel CPU microcode to microcode-20241112 release, addresses
  CVE-2024-21820, CVE-2024-21853, CVE-2024-23918, CVE-2024-23984:
  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
    intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b0005c0
    up to 0x2b000603;
  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
    intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
    intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
    intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
    intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
    intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b0005c0
    up to 0x2b000603;
  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
    intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
    intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
    intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
    intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
    intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision
    0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
    intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
    intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
    intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
    intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
    intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603;
  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision
    0x2b0005c0 up to 0x2b000603;
  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision
    0x36 up to 0x37;
  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
    intel-ucode/06-97-02) from revision 0x36 up to 0x37;
  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
    from revision 0x36 up to 0x37;
  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
    from revision 0x36 up to 0x37;
  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
    intel-ucode/06-97-05) from revision 0x36 up to 0x37;
  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x36
    up to 0x37;
  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
    from revision 0x36 up to 0x37;
  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
    from revision 0x36 up to 0x37;
  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision
    0x434 up to 0x435;
  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in
    intel-ucode/06-9a-03) from revision 0x434 up to 0x435;
  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in
    intel-ucode/06-9a-04) from revision 0x434 up to 0x435;
  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x434
    up to 0x435;
  - Update of 06-aa-04/0xe6 (MTL-H/U C0) microcode from revision 0x1f
    up to 0x20;
  - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x129 up
    to 0x12b;
  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision
    0x4122 up to 0x4123;
  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
    intel-ucode/06-ba-02) from revision 0x4122 up to 0x4123;
  - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) from
    revision 0x4122 up to 0x4123;
  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
    intel-ucode/06-ba-03) from revision 0x4122 up to 0x4123;
  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4122
    up to 0x4123;
  - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) from
    revision 0x4122 up to 0x4123;
  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
    intel-ucode/06-ba-08) from revision 0x4122 up to 0x4123;
  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
    intel-ucode/06-ba-08) from revision 0x4122 up to 0x4123;
  - Update of 06-ba-08/0xe0 microcode from revision 0x4122 up to 0x4123;
  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
    intel-ucode/06-bf-02) from revision 0x36 up to 0x37;
  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
    intel-ucode/06-bf-02) from revision 0x36 up to 0x37;
  - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x36 up
    to 0x37;
  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02)
    from revision 0x36 up to 0x37;
  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
    intel-ucode/06-bf-05) from revision 0x36 up to 0x37;
  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
    intel-ucode/06-bf-05) from revision 0x36 up to 0x37;
  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05)
    from revision 0x36 up to 0x37;
  - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x36 up
    to 0x37;
  - Update of 06-cf-01/0x87 (EMR-SP A0) microcode from revision 0x21000230
    up to 0x21000283;
  - Update of 06-cf-02/0x87 (EMR-SP A1) microcode (in
    intel-ucode/06-cf-01) from revision 0x21000230 up to 0x21000283;
  - Update of 06-cf-01/0x87 (EMR-SP A0) microcode (in
    intel-ucode/06-cf-02) from revision 0x21000230 up to 0x21000283;
  - Update of 06-cf-02/0x87 (EMR-SP A1) microcode from revision 0x21000230
    up to 0x21000283.

* .gitignore: Replace /microcode-20240910.tar.gz entry
with /microcode-20241112.tar.gz.
* microcode_ctl.spec (intel_ucode_version): Bump to 20241112.
(%changelog): Add a record, fix a typo in the previous one.
* sources: Replace microcode-20240910.tar.gz record with
microcode-20241112.tar.gz.

Resolves: RHEL-67336
Signed-off-by: Eugene Syromiatnikov <esyr@redhat.com>
2025-01-02 15:10:33 +01:00
.gitignore Update Intel CPU microcode to microcode-20241112 release 2025-01-02 15:10:33 +01:00
01-microcode.conf Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-2d-07_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-2d-07_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-2d-07_readme Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-4e-03_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-4e-03_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-4e-03_readme Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
06-4f-01_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-4f-01_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-4f-01_readme Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-5e-03_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-5e-03_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-5e-03_readme Update Intel CPU microcode to microcode-20220510 release 2022-06-14 18:04:13 +02:00
06-8c-01_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-8c-01_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-8c-01_readme Update Intel CPU microcode to microcode-20240910 release 2024-09-25 22:43:02 +02:00
06-8e-9e-0x-0xca_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-8e-9e-0x-0xca_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-8e-9e-0x-0xca_readme Update Intel CPU microcode to microcode-20240910 release 2024-09-25 22:43:02 +02:00
06-8e-9e-0x-dell_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-8e-9e-0x-dell_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-8e-9e-0x-dell_readme Update Intel CPU microcode to microcode-20240910 release 2024-09-25 22:43:02 +02:00
06-55-04_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-55-04_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
06-55-04_readme Update Intel CPU microcode to microcode-20230808 release 2023-08-22 21:34:50 +02:00
99-microcode-override.conf Import RHEL packaging 2021-07-26 18:44:11 +02:00
check_caveats check_caveats, reload_microcode, update_ucode: reset locale to C 2023-08-09 09:59:48 +02:00
codenames.list Update Intel CPU microcode to microcode-20240531 release 2024-07-31 05:15:57 +02:00
dracut_99microcode_ctl-fw_dir_override_module_init.sh dracut_99microcode_ctl-fw_dir_override_module_init.sh: add new default fw_dir 2023-08-23 01:46:41 +02:00
gating.yaml add RHEL9 gating.yaml file 2021-06-30 14:42:43 -05:00
gen_provides.sh gen_provides.sh: make microcode header decoding endianness-agnostic 2021-07-26 23:18:05 +02:00
gen_updates2.py gen_updates2.py: consistently specify endianness in struct.unpack formats 2021-07-26 23:18:05 +02:00
intel_config Import RHEL packaging 2021-07-26 18:44:11 +02:00
intel_disclaimer Import RHEL packaging 2021-07-26 18:44:11 +02:00
intel_readme Import RHEL packaging 2021-07-26 18:44:11 +02:00
microcode_ctl.spec Update Intel CPU microcode to microcode-20241112 release 2025-01-02 15:10:33 +01:00
microcode.service Import RHEL packaging 2021-07-26 18:44:11 +02:00
README Import RHEL packaging 2021-07-26 18:44:11 +02:00
README.caveats Update Intel CPU microcode to microcode-20220809 release 2022-09-20 07:28:04 +02:00
reload_microcode check_caveats, reload_microcode, update_ucode: reset locale to C 2023-08-09 09:59:48 +02:00
sources Update Intel CPU microcode to microcode-20241112 release 2025-01-02 15:10:33 +01:00
update_ucode Update Intel CPU microcode to microcode-20240531 release 2024-07-31 05:15:57 +02:00

The microcode_ctl package contains microcode files (vendor-provided binary data
and/or code in proprietary format that affects behaviour of a device) for Intel
CPUs that may be loaded into the CPU during boot.

This directory contains information regarding various aspects of the provided
microcode files and their usage.

 * LICENSE.intel-ucode
   "license" file from the Intel x86 CPU microcode archive.
 * README
   This file.
 * README.caveats
   Caveats (mechanism for enabling/disabling usage of sets of microcode files
   based on caveat configuration and user preferences) documentation.
   Also contains general information about microcode update behaviour and links
   with additional information about the relevant microarchitectural
   vulnerabilities.
 * README.intel-ucode
   "README.md" file from the Intel x86 CPU microcode archive.
 * RELEASE_NOTES.intel-ucode
   "releasenote.md" file from the Intel x86 CPU microcode archive.
 * SECURITY.intel-ucode
   "security.md" file from the Intel x86 CPU microcode archive.
 * SUMMARY.intel-ucode
   Information about supplied microcode files extracted from their headers,
   in a table form.  Columns have the following meaning:
    * "Path": path to the microcode file under one of the following directories:
       * /usr/share/microcode_ctl/ucode_with_caveats/intel
       * /usr/share/microcode_ctl/ucode_with_caveats
       * /usr/share/microcode_ctl
       * /lib/firmware
       * /etc/firmware
    * "Offset": offset of the microcode blob within the micocode file in bytes.
    * "Ext. Offset": offset of the extended signature header within
      the microcode file in bytes.
    * "Data Size": size of microcode data in bytes.  0 means 2000 bytes.
    * "Total Size": size of microcode blob in bytes, incuding headers.
      0 means 2048 bytes.
    * "CPUID": CPU ID signature (in format returned by the CPUID instruction).
    * "Platform ID Mask": mask of suitable Platform IDs (provided in bits
      52..50 of MSR 0x17).
    * "Revision": microcode revision.
    * "Date": microcode creation date.
    * "Checksum": sum (in base 1<< 32) of all 32-bit values comprising
      the microcode (from Offset up to Offset + Total Size).
    * "Codenames": list of known CPU codenames associated with the CPUID
      and Platform ID Mask combination.
   Please refer to README.cavets, section "Microcode file structure"
   for additional information regarding microcode header fields.
 * caveats
   Directory that contains readme files for each specific caveat.