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Import microcode_ctl-20251111-1.el9

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eabdullin 2026-01-29 16:40:43 +03:00
parent b4d077aea7
commit eec4725a25
7 changed files with 40 additions and 17 deletions
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2
.gitignore vendored
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@ -6,4 +6,4 @@ SOURCES/06-5e-03
SOURCES/06-8f-08
SOURCES/microcode-20190918.tar.gz
SOURCES/microcode-20191115.tar.gz
SOURCES/microcode-20250812.tar.gz
SOURCES/microcode-20251111.tar.gz

2
.microcode_ctl.metadata
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@ -6,4 +6,4 @@ bcf2173cd3dd499c37defbc2533703cfa6ec2430 SOURCES/06-2d-07
adf8b6aa2718ff16f3d19d34ec389270073d2b5e SOURCES/06-8f-08
bc20d6789e6614b9d9f88ee321ab82bed220f26f SOURCES/microcode-20190918.tar.gz
774636f4d440623b0ee6a2dad65260e81208074d SOURCES/microcode-20191115.tar.gz
8ea689fb524531a4fa84a1830090d8c4bdb6162b SOURCES/microcode-20250812.tar.gz
4b9344bde5546651b445ca9f9f82c796a13bad33 SOURCES/microcode-20251111.tar.gz

8
SOURCES/0016-releasenote.md-use-new-lines-consistently.patch
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@ -19,14 +19,6 @@ diff --git a/releasenote.md b/releasenote.md
index 0cdfa20..3c700b5 100644
--- a/releasenote.md
+++ b/releasenote.md
@@ -156,6 +156,7 @@
|:---------------|:---------|:------------|:---------|:---------|:---------
| CFL-H/S | P0 | 06-9e-0c/22 | 000000f6 | 000000f8 | Core Gen9
+
## [microcode-20241112](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20241112)
### Purpose
@@ -164,6 +165,7 @@
- Security updates for [INTEL-SA-01079](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01079.html)
- Updated security updates for [INTEL-SA-01097](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01097.html)

2
SOURCES/0017-releasenote.md-add-information-about-removal-of-CLX-.patch
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@ -31,7 +31,7 @@ index 3c700b5..d42e9ad 100644
+| CLX-SP | B0 | 06-55-06/bf | 04003605 | | Xeon Scalable Gen2
+| EMR-SP | A0 | 06-cf-01/87 | 21000291 | | Xeon Scalable Gen5
+
# Release Notes
## [microcode-20250211](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20250211)
--

6
SOURCES/0101-releasenote.md-drop-Removed-Platforms-from-microcode.patch
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@ -17,7 +17,7 @@ diff --git a/releasenote.md b/releasenote.md
index d42e9ad..e46f6f0 100644
--- a/releasenote.md
+++ b/releasenote.md
@@ -85,13 +85,6 @@
@@ -188,13 +188,6 @@
| TWL | N0 | 06-be-00/19 | 0000001c | 0000001d | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E
| WHL-U | V0 | 06-8e-0c/94 | 000000fc | 00000100 | Core Gen8 Mobile
@ -28,10 +28,10 @@ index d42e9ad..e46f6f0 100644
-| CLX-SP | B0 | 06-55-06/bf | 04003605 | | Xeon Scalable Gen2
-| EMR-SP | A0 | 06-cf-01/87 | 21000291 | | Xeon Scalable Gen5
-
# Release Notes
## [microcode-20250211](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20250211)
@@ -149,14 +142,6 @@
@@ -252,14 +245,6 @@
| SPR-SP | E5/S3 | 06-8f-08/87 | 2b000603 | 2b000620 | Xeon Scalable Gen4
| TWL | N0 | 06-be-00/19 | 0000001a | 0000001c | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E

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SOURCES/06-8f-08_config
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@ -1,5 +1,5 @@
model GenuineIntel 06-8f-08
path intel-ucode/06-87-08
path intel-ucode/06-8f-08
## A possible way to disable 0x2b000603 and newer microcode on SPR-EE by default
## Based on https://cdrdv2.intel.com/v1/dl/getcontent/772415
## and https://cdrdv2.intel.com/v1/dl/getcontent/784461

35
SPECS/microcode_ctl.spec
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@ -1,4 +1,4 @@
%define intel_ucode_version 20250812
%define intel_ucode_version 20251111
%define caveat_dir %{_datarootdir}/microcode_ctl/ucode_with_caveats
%define microcode_ctl_libexec %{_libexecdir}/microcode_ctl
@ -636,6 +636,38 @@ rm -rf %{buildroot}
%changelog
* Mon Nov 24 2025 Denys Vlasenko <dvlasenk@redhat.com> - 4:20251111-1
- Fix typo in /usr/share/microcode_ctl/ucode_with_caveats/intel-06-8f-08/config
- Update Intel CPU microcode to microcode-20251111 release (RHEL-128199)
- New microcode files (in hex):
06-ae-01: Granite Rapids-D: revision 1000273
- Microcode files (/platform_mask shown) with revision updates (in hex):
06-8f-07/87: Sapphire Rapids: 2b000643 to 2b000650
06-8f-08/10: Sapphire Rapids with HBM: 2c000401 to 2c000410
06-8f-08/87: Sapphire Rapids: 2b000643 to 2b000650
06-97-02/07: Alder Lake: 003a to 003d
06-97-05/07: Alder Lake: 003a to 003d
06-9a-03/80: Alder Lake-L: 0437 to 043a
06-9a-04/80: Alder Lake-L: 0437 to 043a
06-9a-04/40: Arizona Beach (Atom C11xx): 000a to 000b
06-ad-01/95: Granite Rapids-X: 10003d0 to 10003f0
06-ad-01/20: Granite Rapids-X: a000100 to a000124
06-af-03/01: Crestmont (Sierra Forest): 3000362 to 3000382
06-b7-01/32: Raptor Lake: 012f to 0132
06-ba-02/e0: Raptor Lake-P: 4129 to 6133
06-ba-03/e0: Raptor Lake-P: 4129 to 6133
06-bd-01/80: Lunar Lake: 0123 to 0125
06-be-00/19: Gracemont (Alder Lake-N): 001d to 001e
06-bf-02/07: Raptor Lake-S: 003a to 003d
06-bf-05/07: Raptor Lake-S: 003a to 003d
06-c5-02/82: Arrow Lake-H: 0119 to 011a
06-c6-02/82: Arrow Lake: 0119 to 011a
06-cf-02/87: Emerald Rapids: 210002b3 to 210002c0
- Fixes errata RPL070/ADL083/LNL047/ARL054/SPR154/EMR147:
"REP SCASB, REP CMPSB may return incorrect results when racing
memory access with another core or thread" on Raptor Lake,
Alder Lake, Lunar Lake, Arrow Lake, Sapphire Rapids, Emerald Rapids.
* Wed Aug 20 2025 Denys Vlasenko <dvlasenk@redhat.com> - 4:20250812-1
- Update Intel CPU microcode to microcode-20250812 release
- Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000404
@ -3312,4 +3344,3 @@ rm -rf %{buildroot}
* Sat Dec 18 2004 Dave Jones <davej@redhat.com>
- Initial packaging, based upon kernel-utils.