import CS8 microcode_ctl-20230214-1.el8

2023-07-13 12:50:16 +00:00 · 2023-07-13 12:50:16 +00:00 · ed032fbea2
commit ed032fbea2
parent 2ae8ae86fe
4 changed files with 192 additions and 4 deletions
--- a/.gitignore
+++ b/.gitignore
@ -4,4 +4,4 @@ SOURCES/06-55-04
 SOURCES/06-5e-03
 SOURCES/microcode-20190918.tar.gz
 SOURCES/microcode-20191115.tar.gz
-SOURCES/microcode-20220809.tar.gz
+SOURCES/microcode-20230214.tar.gz
--- a/.microcode_ctl.metadata
+++ b/.microcode_ctl.metadata
@ -4,4 +4,4 @@ bcf2173cd3dd499c37defbc2533703cfa6ec2430 SOURCES/06-2d-07
 86c60ee7d5d0d7115a4962c1c61ceecb0fd3a95a SOURCES/06-5e-03
 bc20d6789e6614b9d9f88ee321ab82bed220f26f SOURCES/microcode-20190918.tar.gz
 774636f4d440623b0ee6a2dad65260e81208074d SOURCES/microcode-20191115.tar.gz
-13f53eed16b393325f1cf571113f102afb7ac27b SOURCES/microcode-20220809.tar.gz
+28bbd30591e0d62f441de019b2829ff265cd238d SOURCES/microcode-20230214.tar.gz
--- a/SOURCES/codenames.list
+++ b/SOURCES/codenames.list
@ -265,6 +265,7 @@ SOC;;XMM 7272 (SoFIA);;01;60650;;;XMM 7272
 Mobile;;Cannon Lake;D0;80;60663;CNL;U;Core Gen8 Mobile;
 Server;;Ice Lake;C0;87;606a5;ICX;SP;Xeon Scalable Gen3;
 Server;;Ice Lake;D0;87;606a6;ICX;SP;Xeon Scalable Gen3;
+Server;;Ice Lake;B0;10;606c1;ICL;D;;Xeon D-17xx, D-27xx
 SOC;;Gemini Lake;B0;01;706a1;GLK;;;Pentium J5005/N5000, Celeron J4005/J4105/N4000/N4100
 SOC;;Gemini Lake;R0;01;706a8;GLK;R;;Pentium J5040/N5030, Celeron J4125/J4025/N4020/N4120
 Mobile;;Ice Lake;D1;80;706e5;ICL;U,Y;Core Gen10 Mobile;
@ -286,6 +287,13 @@ Mobile;;Comet Lake;V0;94;806ec;CML;U 4+2;Core Gen10 Mobile;
 Mobile;;Whiskey Lake;W0;d0;806eb;WHL;U;Core Gen8 Mobile;
 Mobile;;Whiskey Lake;V0;94;806ec;WHL;U;Core Gen8 Mobile;
 Mobile;;Whiskey Lake;V0;94;806ed;WHL;U;Core Gen8 Mobile;
+Server;;Sapphire Rapids;E0,S1;87;806f4;SPR;SP;Xeon Scalable Gen4;
+Server;;Sapphire Rapids;B1;10;806f5;SPR;HBM;Xeon Max;
+Server;;Sapphire Rapids;E2;87;806f5;SPR;SP;Xeon Scalable Gen4;
+Server;;Sapphire Rapids;E3;87;806f6;SPR;SP;Xeon Scalable Gen4;
+Server;;Sapphire Rapids;E4,S2;87;806f7;SPR;SP;Xeon Scalable Gen4;
+Server;;Sapphire Rapids;B3;10;806f8;SPR;HBM;Xeon Max;
+Server;;Sapphire Rapids;E5,S3;87;806f8;SPR;SP;Xeon Scalable Gen4;
 SOC;;Elkhart Rate;B1;01;90661;EHL;;Pentium J6426/N6415, Celeron J6412/J6413/N6210/N6211, Atom x6000E;
 Desktop;;Alder Lake;C0;02;90672;ADL;S 8+8;Core Gen12;
 Mobile;;Alder Lake;C0;03;90672;ADL;HX;Core Gen12 Mobile;
@ -315,6 +323,9 @@ Desktop;;Comet Lake;Q0;22;a0655;CML;S 10+2;Core Gen10 Desktop;
 Mobile;;Comet Lake;A0;80;a0660;CML;U 6+2;Core Gen10 Mobile;
 Mobile;;Comet Lake;K1;80;a0661;CML;U 6+2 v2;Core Gen10 Mobile;
 Desktop;;Rocket Lake;B0;02;a0671;RKL;S;Core Gen11;
+Desktop;;Raptor Lake;S0;32;b0671;RPL;S;Core Gen13;
+Mobile;;Raptor Lake;J0;07;b06a2;RPL;P 6+8,H 6+8;Core Gen13;
+Mobile;;Raptor Lake;Q0;07;b06a3;RPL;U 2+8;Core Gen13;
 Desktop;;Alder Lake;C0;03;b06f2;ADL;;Core Gen12;
 Desktop;;Alder Lake;C0;03;b06f5;ADL;;Core Gen12;

--- a/SPECS/microcode_ctl.spec
+++ b/SPECS/microcode_ctl.spec
@ -1,4 +1,4 @@
-%define intel_ucode_version 20220809
+%define intel_ucode_version 20230214
 %global debug_package %{nil}

 %define caveat_dir %{_datarootdir}/microcode_ctl/ucode_with_caveats
@ -13,7 +13,7 @@
 Summary:        CPU microcode updates for Intel x86 processors
 Name:           microcode_ctl
 Version:        %{intel_ucode_version}
-Release:        2%{?dist}
+Release:        1%{?dist}
 Epoch:          4
 License:        CC0 and Redistributable, no modification permitted
 URL:            https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files
@ -544,6 +544,183 @@ rm -rf %{buildroot}


 %changelog
+* Wed Feb 15 2023 Eugene Syromiatnikov <esyr@redhat.com> - 4:20230214-1
+- Update Intel CPU microcode to microcode-20230214 release, addresses
+  CVE-2022-21216, CVE-2022-33196, CVE-2022-33972, CVE-2022-38090 (#2171234,
+  #2171259):
+  - Addition of 06-6c-01/0x10 (ICL-D B0) microcode at revision 0x1000211;
+  - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode at revision
+    0x2b000181;
+  - Addition of 06-8f-04/0x10 microcode at revision 0x2c000170;
+  - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2b000181;
+  - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2c000170;
+  - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2b000181;
+  - Addition of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) at
+    revision 0x2c000170;
+  - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2b000181;
+  - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2b000181;
+  - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2c000170;
+  - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-05) at revision 0x2b000181;
+  - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) at
+    revision 0x2c000170;
+  - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode at revision
+    0x2b000181;
+  - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode at revision
+    0x2c000170;
+  - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-05) at revision 0x2b000181;
+  - Addition of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) at
+    revision 0x2c000170;
+  - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-05) at revision 0x2b000181;
+  - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-05) at revision 0x2b000181;
+  - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
+    intel-ucode/06-8f-05) at revision 0x2c000170;
+  - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-06) at revision 0x2b000181;
+  - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) at
+    revision 0x2c000170;
+  - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-06) at revision 0x2b000181;
+  - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
+    intel-ucode/06-8f-06) at revision 0x2c000170;
+  - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode at revision
+    0x2b000181;
+  - Addition of 06-8f-06/0x10 microcode at revision 0x2c000170;
+  - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-06) at revision 0x2b000181;
+  - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-06) at revision 0x2b000181;
+  - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
+    intel-ucode/06-8f-06) at revision 0x2c000170;
+  - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-07) at revision 0x2b000181;
+  - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-07) at revision 0x2b000181;
+  - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-07) at revision 0x2b000181;
+  - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode at revision
+    0x2b000181;
+  - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-07) at revision 0x2b000181;
+  - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-08) at revision 0x2b000181;
+  - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) at
+    revision 0x2c000170;
+  - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-08) at revision 0x2b000181;
+  - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
+    intel-ucode/06-8f-08) at revision 0x2c000170;
+  - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-08) at revision 0x2b000181;
+  - Addition of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) at
+    revision 0x2c000170;
+  - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-08) at revision 0x2b000181;
+  - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode at revision
+    0x2b000181;
+  - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode at revision
+    0x2c000170;
+  - Addition of 06-b7-01/0x32 (RPL-S S0) microcode at revision 0x112;
+  - Addition of 06-ba-02/0xc0 microcode at revision 0x410e;
+  - Addition of 06-ba-03/0xc0 microcode (in intel-ucode/06-ba-02) at
+    revision 0x410e;
+  - Addition of 06-ba-02/0xc0 microcode (in intel-ucode/06-ba-03) at
+    revision 0x410e;
+  - Addition of 06-ba-03/0xc0 microcode at revision 0x410e;
+  - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode (in
+    intel-06-8c-01/intel-ucode/06-8c-01) from revision 0xa4 up to 0xa6;
+  - Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0)
+    microcode (in intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0c) from
+    revision 0xf0 up to 0xf4;
+  - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode (in
+    intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0d) from revision 0xf0 up
+    to 0xf4;
+  - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x100015e
+    up to 0x1000161;
+  - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003302
+    up to 0x4003303;
+  - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision
+    0x5003302 up to 0x5003303;
+  - Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002501
+    up to 0x7002503;
+  - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000375
+    up to 0xd000389;
+  - Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x3c up
+    to 0x3e;
+  - Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x20 up
+    to 0x22;
+  - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xb2
+    up to 0xb8;
+  - Update of 06-8a-01/0x10 (LKF B2/B3) microcode from revision 0x31 up
+    to 0x32;
+  - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x40 up
+    to 0x42;
+  - Update of 06-96-01/0x01 (EHL B1) microcode from revision 0x16 up
+    to 0x17;
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision
+    0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
+    intel-ucode/06-97-02) from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
+    from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
+    from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
+    intel-ucode/06-97-05) from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x22
+    up to 0x2c (old pf 0x3);
+  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
+    from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
+    from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision
+    0x421 up to 0x429;
+  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in
+    intel-ucode/06-9a-03) from revision 0x421 up to 0x429;
+  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in
+    intel-ucode/06-9a-04) from revision 0x421 up to 0x429;
+  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x421
+    up to 0x429;
+  - Update of 06-9c-00/0x01 (JSL A0/A1) microcode from revision 0x24000023
+    up to 0x24000024;
+  - Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf0 up
+    to 0xf4;
+  - Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf0
+    up to 0xf4;
+  - Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf0
+    up to 0xf4;
+  - Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf0
+    up to 0xf4;
+  - Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision
+    0xf0 up to 0xf4;
+  - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x54 up
+    to 0x57;
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
+    intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
+    intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x22 up to
+    0x2c (old pf 0x3);
+  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02)
+    from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
+    intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
+    intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05)
+    from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x22 up to
+    0x2c (old pf 0x3).
+
 * Tue Oct 25 2022 Eugene Syromiatnikov <esyr@redhat.com> - 4:20220809-2
 - Change the logger severity level to warning to align with the kmsg one
  (#2136224).