diff --git a/.gitignore b/.gitignore
index 768dbfd..012ee8c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -59,3 +59,4 @@ microcode-20100826.dat
 /microcode_ctl-2.1-37.tar.xz
 /microcode_ctl-2.1-40.tar.xz
 /microcode_ctl-2.1-41.tar.xz
+/microcode_ctl-2.1-42.tar.xz
diff --git a/microcode_ctl.spec b/microcode_ctl.spec
index f77442b..61e6b38 100644
--- a/microcode_ctl.spec
+++ b/microcode_ctl.spec
@@ -1,10 +1,10 @@
-%define upstream_version 2.1-41
+%define upstream_version 2.1-42
 %global debug_package %{nil}
 
 Summary:        Tool to transform and deploy CPU microcode update for x86
 Name:           microcode_ctl
 Version:        2.1
-Release:        57%{?dist}
+Release:        58%{?dist}
 Epoch:          2
 License:        GPLv2+ and Redistributable, no modification permitted
 URL:            https://pagure.io/microcode_ctl
@@ -35,6 +35,160 @@ make DESTDIR=%{buildroot} PREFIX=%{_prefix} INSDIR=/usr/sbin install clean
 
 
 %changelog
+* Thu Nov 14 2023 Eugene Syromiatnikov <esyr@redhat.com> 2:2.1-58
+- Update to upstream 2.1-42. 20231114
+  - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd0003a5
+    up to 0xd0003b9;
+  - Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x1000230
+    up to 0x1000268;
+  - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xbc
+    up to 0xc2;
+  - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode from revision
+    0xac up to 0xb4;
+  - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x2c up
+    to 0x34;
+  - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x46 up
+    to 0x4e;
+  - Update of 06-8f-04/0x10 microcode from revision 0x2c000271 up to
+    0x2c000290;
+  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode from revision
+    0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
+    intel-ucode/06-8f-04) from revision 0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) from
+    revision 0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
+    intel-ucode/06-8f-04) from revision 0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-04) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) from
+    revision 0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode from revision
+    0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b0004b1
+    up to 0x2b0004d0;
+  - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) from
+    revision 0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
+    intel-ucode/06-8f-05) from revision 0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-05) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) from
+    revision 0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
+    intel-ucode/06-8f-06) from revision 0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-06/0x10 microcode from revision 0x2c000271 up to
+    0x2c000290;
+  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b0004b1
+    up to 0x2b0004d0;
+  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
+    intel-ucode/06-8f-06) from revision 0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-06) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision
+    0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-07) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from
+    revision 0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from
+    revision 0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision
+    0x2c000271 up to 0x2c000290;
+  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision
+    0x2b0004b1 up to 0x2b0004d0;
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision
+    0x2e up to 0x32;
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
+    intel-ucode/06-97-02) from revision 0x2e up to 0x32;
+  - Update of 06-bf-02/0x07 (RPL-S 8+8 C0) microcode (in
+    intel-ucode/06-97-02) from revision 0x2e up to 0x32;
+  - Update of 06-bf-05/0x07 (RPL-S 6+0 C0) microcode (in
+    intel-ucode/06-97-02) from revision 0x2e up to 0x32;
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
+    intel-ucode/06-97-05) from revision 0x2e up to 0x32;
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x2e
+    up to 0x32;
+  - Update of 06-bf-02/0x07 (RPL-S 8+8 C0) microcode (in
+    intel-ucode/06-97-05) from revision 0x2e up to 0x32;
+  - Update of 06-bf-05/0x07 (RPL-S 6+0 C0) microcode (in
+    intel-ucode/06-97-05) from revision 0x2e up to 0x32;
+  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision
+    0x42c up to 0x430;
+  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in
+    intel-ucode/06-9a-03) from revision 0x42c up to 0x430;
+  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in
+    intel-ucode/06-9a-04) from revision 0x42c up to 0x430;
+  - Update of 06-9a-04/0x40 (AZB A0) microcode from revision 0x4 up
+    to 0x5;
+  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x42c
+    up to 0x430;
+  - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x59 up
+    to 0x5d;
+  - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x119 up
+    to 0x11d;
+  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision
+    0x4119 up to 0x411c;
+  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
+    intel-ucode/06-ba-02) from revision 0x4119 up to 0x411c;
+  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
+    intel-ucode/06-ba-03) from revision 0x4119 up to 0x411c;
+  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4119
+    up to 0x411c;
+  - Update of 06-be-00/0x11 (ADL-N A0) microcode from revision 0x11 up
+    to 0x12;
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
+    intel-ucode/06-bf-02) from revision 0x2e up to 0x32;
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
+    intel-ucode/06-bf-02) from revision 0x2e up to 0x32;
+  - Update of 06-bf-02/0x07 (RPL-S 8+8 C0) microcode from revision 0x2e
+    up to 0x32;
+  - Update of 06-bf-05/0x07 (RPL-S 6+0 C0) microcode (in
+    intel-ucode/06-bf-02) from revision 0x2e up to 0x32;
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
+    intel-ucode/06-bf-05) from revision 0x2e up to 0x32;
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
+    intel-ucode/06-bf-05) from revision 0x2e up to 0x32;
+  - Update of 06-bf-02/0x07 (RPL-S 8+8 C0) microcode (in
+    intel-ucode/06-bf-05) from revision 0x2e up to 0x32;
+  - Update of 06-bf-05/0x07 (RPL-S 6+0 C0) microcode from revision 0x2e
+    up to 0x32.
+- Addresses CVE-2023-23583
+
 * Thu Aug 10 2023 Eugene Syromiatnikov <esyr@redhat.com> 2:2.1-57
 - Update to upstream 2.1-41. 20230808
   - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000171
diff --git a/sources b/sources
index 6a142b5..26353f7 100644
--- a/sources
+++ b/sources
@@ -1 +1 @@
-SHA512 (microcode_ctl-2.1-41.tar.xz) = f10ebf7c1e4ca41f3b9639553e1104c8a9287002a6984485ca39b43012af9916371e5a08ad8025f8b5007f69ea4eeea020288c47d4f98a881c19bba23d8aef27
+SHA512 (microcode_ctl-2.1-42.tar.xz) = 63d8b0fe5191edaee512ff8c21dbabe2bd726453ec7b1750e7b45a166207e4795a6d8af7eb7ffab20cd619cc19310fe64695ec343e6cbde8a85564dccce441a4