import OL microcode_ctl-20220809-2.20230214.1.0.1.el9_2
This commit is contained in:
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SOURCES/06-2d-07
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SOURCES/06-4e-03
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SOURCES/06-55-04
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SOURCES/06-5e-03
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SOURCES/microcode-20190918.tar.gz
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SOURCES/microcode-20191115.tar.gz
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SOURCES/microcode-20220809.tar.gz
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SOURCES/microcode-20230214.tar.gz
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@ -1,7 +1,5 @@
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bcf2173cd3dd499c37defbc2533703cfa6ec2430 SOURCES/06-2d-07
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06432a25053c823b0e2a6b8e84e2e2023ee3d43e SOURCES/06-4e-03
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2e405644a145de0f55517b6a9de118eec8ec1e5a SOURCES/06-55-04
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86c60ee7d5d0d7115a4962c1c61ceecb0fd3a95a SOURCES/06-5e-03
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bc20d6789e6614b9d9f88ee321ab82bed220f26f SOURCES/microcode-20190918.tar.gz
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774636f4d440623b0ee6a2dad65260e81208074d SOURCES/microcode-20191115.tar.gz
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13f53eed16b393325f1cf571113f102afb7ac27b SOURCES/microcode-20220809.tar.gz
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28bbd30591e0d62f441de019b2829ff265cd238d SOURCES/microcode-20230214.tar.gz
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@ -1,3 +0,0 @@
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model GenuineIntel 06-2d-07
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path intel-ucode/06-2d-07
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dependency required intel
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@ -1,4 +0,0 @@
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MDS-related microcode update for Intel Sandy Bridge-EP (family 6, model 45,
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stepping 7; CPUID 0x206d7) CPUs is disabled.
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Please refer to /usr/share/doc/microcode_ctl/caveats/06-2d-07_readme
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and /usr/share/doc/microcode_ctl/README.caveats for details.
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@ -1,58 +0,0 @@
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Intel Sandy Bridge-E/EN/EP CPU models (SNB-EP, family 6, model 45, stepping 7)
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had issues with MDS-related microcode update that may lead to a system hang
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after a microcode update[1][2]. In order to address this, microcode update
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to the MDS-related revision 0x718 had been disabled, and the previously
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published microcode revision 0x714 is used by default for the OS-driven
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microcode update. The revision 0x71a of the microcode is intended to fix
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the aforementioned issue, hence it is enabled by default (but can be disabled
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explicitly; see below).
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[1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/15
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[2] https://access.redhat.com/solutions/4593951
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For the reference, SHA1 checksums of 06-2d-07 microcode files containing
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microcode revisions in question are listed below:
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* 06-2d-07, revision 0x714: bcf2173cd3dd499c37defbc2533703cfa6ec2430
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* 06-2d-07, revision 0x718: 837cfebbfc09b911151dfd179082ad99cf87e85d
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* 06-2d-07, revision 0x71a: 4512c8149e63e5ed15f45005d7fb5be0041f66f6
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Please contact your system vendor for a BIOS/firmware update that contains
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the latest microcode version. For the information regarding microcode versions
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required for mitigating specific side-channel cache attacks, please refer
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to the following knowledge base articles:
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* CVE-2017-5715 ("Spectre"):
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https://access.redhat.com/articles/3436091
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* CVE-2018-3639 ("Speculative Store Bypass"):
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https://access.redhat.com/articles/3540901
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* CVE-2018-3620, CVE-2018-3646 ("L1 Terminal Fault Attack"):
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https://access.redhat.com/articles/3562741
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* CVE-2018-12130, CVE-2018-12126, CVE-2018-12127, and CVE-2019-11091
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("Microarchitectural Data Sampling"):
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https://access.redhat.com/articles/4138151
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The information regarding disabling microcode update is provided below.
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To disable usage of the newer microcode revision for a specific kernel
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version, please create file "disallow-intel-06-2d-07" inside
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/lib/firmware/<kernel_version> directory, run
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"/usr/libexec/microcode_ctl/update_ucode" to add it to firmware directory
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where microcode will be available for late microcode update, and run
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"dracut -f --kver <kernel_version>", so initramfs for this kernel version
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is regenerated and the microcode can be loaded early, for example:
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touch /lib/firmware/3.10.0-862.9.1/disallow-intel-06-2d-07
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/usr/libexec/microcode_ctl/update_ucode
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dracut -f --kver 3.10.0-862.9.1
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To avoid addition of the newer microcode revision for all kernels, please create
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file "/etc/microcode_ctl/ucode_with_caveats/disallow-intel-06-2d-07", run
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"/usr/libexec/microcode_ctl/update_ucode" for late microcode updates,
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and "dracut -f --regenerate-all" for early microcode updates:
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mkdir -p /etc/microcode_ctl/ucode_with_caveats
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touch /etc/microcode_ctl/ucode_with_caveats/disallow-intel-06-2d-07
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/usr/libexec/microcode_ctl/update_ucode
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dracut -f --regenerate-all
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Please refer to /usr/share/doc/microcode_ctl/README.caveats for additional
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information.
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@ -1,15 +1,6 @@
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model GenuineIntel 06-4f-01
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path intel-ucode/06-4f-01
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kernel 4.17.0
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kernel 3.10.0-894
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kernel 3.10.0-862.6.1
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kernel 3.10.0-693.35.1
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kernel 3.10.0-514.52.1
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kernel 3.10.0-327.70.1
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kernel 2.6.32-754.1.1
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kernel 2.6.32-573.58.1
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kernel 2.6.32-504.71.1
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kernel 2.6.32-431.90.1
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kernel 2.6.32-358.90.1
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kernel 5.15.0
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kernel 5.14.0
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dependency required intel skip=success match-model-mode=off
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disable early late
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disable late
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@ -1,12 +0,0 @@
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model GenuineIntel 06-55-04
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path intel-ucode/06-55-04
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## Bug https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/21
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## affects only SKX-W/X (Workstation and HEDT segments); product segment
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## can be determined by checking bits 5..3 of the CAPID0 field in PCU registers
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## device (see https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-scalable-spec-update.pdf#page=13
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## for Server/FPGA/Fabric segments description; for SKX-W/X no public
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## documentation seems to be available). Specific device/function numbers
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## are provided for speeding up the search only, VID:DID is the real selector.
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## Commented out since revision 0x2006906 seems to fix the issue.
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#pci_config_val mode=success-all device=0x1e function=3 vid=0x8086 did=0x2083 offset=0x84 size=4 mask=0x38 val=0x38,0x18,0x8
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dependency required intel
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@ -1,5 +0,0 @@
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Microcode revisions 0x2000065 and higher for Intel Skylake-X/W (family 6,
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model 85, stepping 4; CPUID 0x50654) were disabled as they could cause system
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hangs on reboot, so the previous revision 0x2000064 was used instead.
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Please refer to /usr/share/doc/microcode_ctl/caveats/06-55-04_readme
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and /usr/share/doc/microcode_ctl/README.caveats for details.
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@ -1,97 +0,0 @@
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Intel Skylake Scalable Platform CPU models that belong to Workstation and HEDT
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(Basin Falls) segment (SKL-W/X, family 6, model 85, stepping 4) had reports
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of system hangs on reboot when revision 0x2000065 of microcode, that was included
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from microcode-20191112 update up to microcode-20200520 update, was applied[1].
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In order to address this, microcode update to the newer revision had been
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disabled by default on these systems, and the previously published microcode
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revision 0x2000064 is used by default for the OS-driven microcode update.
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Since revision 0x2006906 (included with the microcode-20200609 release)
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it is reported that the issue is no longer present, so the newer microcode
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revision is enabled by default now (but can be disabled explicitly; see below).
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[1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/21
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For the reference, SHA1 checksums of 06-55-04 microcode files containing
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microcode revisions in question are listed below:
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* 06-55-04, revision 0x2000064: 2e405644a145de0f55517b6a9de118eec8ec1e5a
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* 06-55-04, revision 0x2000065: f27f12b9d53f492c297afd856cdbc596786fad23
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* 06-55-04, revision 0x2006906: 5f18f985f6d5ad369b5f6549b7f3ee55acaef967
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* 06-55-04, revision 0x2006a08: 4059fb1f60370297454177f63cd7cc20b3fa1212
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* 06-55-04, revision 0x2006a0a: 7ec27025329c82de9553c14a78733ad1013e5462
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* 06-55-04, revision 0x2006b06: cb5bec976cb9754e3a22ab6828b3262a8f9eccf7
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* 06-55-04, revision 0x2006c0a: 76b641375d136c08f5feb46aacebee40468ac085
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* 06-55-04, revision 0x2006d05: dc4207cf4eb916ff34acbdddc474db0df781234f
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* 06-55-04, revision 0x2006e05: bc67d247ad1c9a834bec5e452606db1381d6bc7e
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Please contact your system vendor for a BIOS/firmware update that contains
|
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the latest microcode version. For the information regarding microcode versions
|
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required for mitigating specific side-channel cache attacks, please refer
|
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to the following knowledge base articles:
|
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* CVE-2017-5715 ("Spectre"):
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https://access.redhat.com/articles/3436091
|
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* CVE-2018-3639 ("Speculative Store Bypass"):
|
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https://access.redhat.com/articles/3540901
|
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* CVE-2018-3620, CVE-2018-3646 ("L1 Terminal Fault Attack"):
|
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https://access.redhat.com/articles/3562741
|
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* CVE-2018-12130, CVE-2018-12126, CVE-2018-12127, and CVE-2019-11091
|
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("Microarchitectural Data Sampling"):
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https://access.redhat.com/articles/4138151
|
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* CVE-2019-0117 (Intel SGX Information Leak),
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CVE-2019-0123 (Intel SGX Privilege Escalation),
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CVE-2019-11135 (TSX Asynchronous Abort),
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CVE-2019-11139 (Voltage Setting Modulation):
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https://access.redhat.com/solutions/2019-microcode-nov
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* CVE-2020-0543 (Special Register Buffer Data Sampling),
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CVE-2020-0548 (Vector Register Data Sampling),
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CVE-2020-0549 (L1D Cache Eviction Sampling):
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https://access.redhat.com/solutions/5142751
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* CVE-2020-8695 (Information disclosure issue in Intel SGX via RAPL interface),
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CVE-2020-8696 (Vector Register Leakage-Active),
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CVE-2020-8698 (Fast Forward Store Predictor):
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https://access.redhat.com/articles/5569051
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* CVE-2020-24489 (VT-d-related Privilege Escalation),
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CVE-2020-24511 (Improper Isolation of Shared Resources),
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CVE-2020-24512 (Observable Timing Discrepancy),
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CVE-2020-24513 (Information Disclosure on Some Intel Atom Processors):
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https://access.redhat.com/articles/6101171
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* CVE-2021-0127 (Intel Processor Breakpoint Control Flow):
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https://access.redhat.com/articles/6716541
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* CVE-2022-0005 (Informational disclosure via JTAG),
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CVE-2022-21123 (Shared Buffers Data Read),
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CVE-2022-21125 (Shared Buffers Data Sampling),
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CVE-2022-21127 (Update to Special Register Buffer Data Sampling),
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CVE-2022-21131 (Protected Processor Inventory Number (PPIN) access protection),
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CVE-2022-21136 (Overclocking service access protection),
|
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CVE-2022-21151 (Optimization Removal-Induced Informational Disclosure),
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CVE-2022-21166 (Device Register Partial Write):
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https://access.redhat.com/articles/6963124
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* CVE-2022-21233 (Stale Data Read from legacy xAPIC):
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https://access.redhat.com/articles/6976398
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The information regarding disabling microcode update is provided below.
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|
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To disable usage of the newer microcode revision for a specific kernel
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version, please create a file "disallow-intel-06-55-04" inside
|
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/lib/firmware/<kernel_version> directory, run
|
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"/usr/libexec/microcode_ctl/update_ucode" to update firmware directory
|
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used for late microcode updates, and run "dracut -f --kver <kernel_version>"
|
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so initramfs for this kernel version is regenerated, for example:
|
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|
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touch /lib/firmware/3.10.0-862.9.1/disallow-intel-06-55-04
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/usr/libexec/microcode_ctl/update_ucode
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dracut -f --kver 3.10.0-862.9.1
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To disable usage of the newer microcode revision for all kernels, please create
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file "/etc/microcode_ctl/ucode_with_caveats/disallow-intel-06-55-04", run
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"/usr/libexec/microcode_ctl/update_ucode" to update firmware directories
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used for late microcode updates, and run "dracut -f --regenerate-all"
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so initramfs images get regenerated, for example:
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mkdir -p /etc/microcode_ctl/ucode_with_caveats
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touch /etc/microcode_ctl/ucode_with_caveats/disallow-intel-06-55-04
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/usr/libexec/microcode_ctl/update_ucode
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dracut -f --regenerate-all
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Please refer to /usr/share/doc/microcode_ctl/README.caveats for additional
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information.
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@ -265,6 +265,7 @@ SOC;;XMM 7272 (SoFIA);;01;60650;;;XMM 7272
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Mobile;;Cannon Lake;D0;80;60663;CNL;U;Core Gen8 Mobile;
|
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Server;;Ice Lake;C0;87;606a5;ICX;SP;Xeon Scalable Gen3;
|
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Server;;Ice Lake;D0;87;606a6;ICX;SP;Xeon Scalable Gen3;
|
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Server;;Ice Lake;B0;10;606c1;ICL;D;;Xeon D-17xx, D-27xx
|
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SOC;;Gemini Lake;B0;01;706a1;GLK;;;Pentium J5005/N5000, Celeron J4005/J4105/N4000/N4100
|
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SOC;;Gemini Lake;R0;01;706a8;GLK;R;;Pentium J5040/N5030, Celeron J4125/J4025/N4020/N4120
|
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Mobile;;Ice Lake;D1;80;706e5;ICL;U,Y;Core Gen10 Mobile;
|
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@ -286,6 +287,13 @@ Mobile;;Comet Lake;V0;94;806ec;CML;U 4+2;Core Gen10 Mobile;
|
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Mobile;;Whiskey Lake;W0;d0;806eb;WHL;U;Core Gen8 Mobile;
|
||||
Mobile;;Whiskey Lake;V0;94;806ec;WHL;U;Core Gen8 Mobile;
|
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Mobile;;Whiskey Lake;V0;94;806ed;WHL;U;Core Gen8 Mobile;
|
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Server;;Sapphire Rapids;E0,S1;87;806f4;SPR;SP;Xeon Scalable Gen4;
|
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Server;;Sapphire Rapids;B1;10;806f5;SPR;HBM;Xeon Max;
|
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Server;;Sapphire Rapids;E2;87;806f5;SPR;SP;Xeon Scalable Gen4;
|
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Server;;Sapphire Rapids;E3;87;806f6;SPR;SP;Xeon Scalable Gen4;
|
||||
Server;;Sapphire Rapids;E4,S2;87;806f7;SPR;SP;Xeon Scalable Gen4;
|
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Server;;Sapphire Rapids;B3;10;806f8;SPR;HBM;Xeon Max;
|
||||
Server;;Sapphire Rapids;E5,S3;87;806f8;SPR;SP;Xeon Scalable Gen4;
|
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SOC;;Elkhart Rate;B1;01;90661;EHL;;Pentium J6426/N6415, Celeron J6412/J6413/N6210/N6211, Atom x6000E;
|
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Desktop;;Alder Lake;C0;02;90672;ADL;S 8+8;Core Gen12;
|
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Mobile;;Alder Lake;C0;03;90672;ADL;HX;Core Gen12 Mobile;
|
||||
@ -315,6 +323,9 @@ Desktop;;Comet Lake;Q0;22;a0655;CML;S 10+2;Core Gen10 Desktop;
|
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Mobile;;Comet Lake;A0;80;a0660;CML;U 6+2;Core Gen10 Mobile;
|
||||
Mobile;;Comet Lake;K1;80;a0661;CML;U 6+2 v2;Core Gen10 Mobile;
|
||||
Desktop;;Rocket Lake;B0;02;a0671;RKL;S;Core Gen11;
|
||||
Desktop;;Raptor Lake;S0;32;b0671;RPL;S;Core Gen13;
|
||||
Mobile;;Raptor Lake;J0;07;b06a2;RPL;P 6+8,H 6+8;Core Gen13;
|
||||
Mobile;;Raptor Lake;Q0;07;b06a3;RPL;U 2+8;Core Gen13;
|
||||
Desktop;;Alder Lake;C0;03;b06f2;ADL;;Core Gen12;
|
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Desktop;;Alder Lake;C0;03;b06f5;ADL;;Core Gen12;
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|
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|
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@ -1,8 +1,6 @@
|
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path intel-ucode/*
|
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vendor GenuineIntel
|
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kernel_early 4.10.0
|
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kernel_early 3.10.0-930
|
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kernel_early 3.10.0-862.14.1
|
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kernel_early 3.10.0-693.38.1
|
||||
kernel_early 3.10.0-514.57.1
|
||||
kernel_early 3.10.0-327.73.1
|
||||
kernel_early 5.15.0
|
||||
kernel_early 5.14.0
|
||||
kernel 5.15.0
|
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kernel 5.14.0
|
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|
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@ -1,4 +1,4 @@
|
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%define intel_ucode_version 20220809
|
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%define intel_ucode_version 20230214
|
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|
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%define caveat_dir %{_datarootdir}/microcode_ctl/ucode_with_caveats
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%define microcode_ctl_libexec %{_libexecdir}/microcode_ctl
|
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@ -11,19 +11,13 @@
|
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|
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Summary: CPU microcode updates for Intel x86 processors
|
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Name: microcode_ctl
|
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Version: %{intel_ucode_version}
|
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Release: 2%{?dist}
|
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Version: 20220809
|
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Release: 2.%{intel_ucode_version}.1.0.1%{?dist}
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Epoch: 4
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License: CC0 and Redistributable, no modification permitted
|
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URL: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files
|
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Source0: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/archive/microcode-%{intel_ucode_version}.tar.gz
|
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|
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# (Pre-MDS) revision 0x714 of 06-2d-07 microcode
|
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Source2: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/raw/microcode-20190514/intel-ucode/06-2d-07
|
||||
|
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# (Pre-20191112) revision 0x2000064 of 06-55-04 microcode
|
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Source3: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/raw/microcode-20190918/intel-ucode/06-55-04
|
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|
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# (Pre-20200609) revision 0xd6 of 06-4e-03/06-5e-03 microcode
|
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Source4: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/raw/microcode-20200520/intel-ucode/06-4e-03
|
||||
Source5: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/raw/microcode-20200520/intel-ucode/06-5e-03
|
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@ -66,19 +60,6 @@ Source110: intel_readme
|
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Source111: intel_config
|
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Source112: intel_disclaimer
|
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|
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# SNB-EP (CPUID 0x206d7) post-MDS hangs
|
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# https://bugzilla.redhat.com/show_bug.cgi?id=1758382
|
||||
# https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/15
|
||||
Source120: 06-2d-07_readme
|
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Source121: 06-2d-07_config
|
||||
Source122: 06-2d-07_disclaimer
|
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|
||||
# SKL-SP/W/X (CPUID 0x50654) post-20191112 hangs
|
||||
# https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/21
|
||||
Source130: 06-55-04_readme
|
||||
Source131: 06-55-04_config
|
||||
Source132: 06-55-04_disclaimer
|
||||
|
||||
# SKL-U/Y (CPUID 0x406e3) post-20200609 hangs
|
||||
# https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/31
|
||||
Source140: 06-4e-03_readme
|
||||
@ -150,14 +131,6 @@ is no longer used for microcode upload and, as a result, no longer provided.
|
||||
%setup -n "Intel-Linux-Processor-Microcode-Data-Files-microcode-%{intel_ucode_version}"
|
||||
|
||||
%build
|
||||
# replacing SNB-EP (CPUID 0x206d7) microcode with pre-MDS version
|
||||
mv intel-ucode/06-2d-07 intel-ucode-with-caveats/
|
||||
cp "%{SOURCE2}" intel-ucode/
|
||||
|
||||
# replacing SKL-SP/W/X (CPUID 0x50654) microcode with pre-20191112 version
|
||||
mv intel-ucode/06-55-04 intel-ucode-with-caveats/
|
||||
cp "%{SOURCE3}" intel-ucode/
|
||||
|
||||
# replacing SKL-U/Y (CPUID 0x4063e) microcode with pre-20200609 version
|
||||
mv intel-ucode/06-4e-03 intel-ucode-with-caveats/
|
||||
cp "%{SOURCE4}" intel-ucode/
|
||||
@ -228,7 +201,7 @@ install -m 644 releasenote.md \
|
||||
"%{buildroot}/%{_pkgdocdir}/RELEASE_NOTES.intel-ucode"
|
||||
|
||||
# caveats
|
||||
install -m 644 "%{SOURCE100}" "%{SOURCE110}" "%{SOURCE120}" "%{SOURCE130}" \
|
||||
install -m 644 "%{SOURCE100}" "%{SOURCE110}" \
|
||||
"%{SOURCE140}" "%{SOURCE150}" "%{SOURCE160}" "%{SOURCE170}" \
|
||||
"%{SOURCE180}" \
|
||||
-t "%{buildroot}/%{_pkgdocdir}/caveats/"
|
||||
@ -252,22 +225,6 @@ install -m 644 "%{SOURCE110}" "%{intel_inst_dir}/readme"
|
||||
install -m 644 "%{SOURCE111}" "%{intel_inst_dir}/config"
|
||||
install -m 644 "%{SOURCE112}" "%{intel_inst_dir}/disclaimer"
|
||||
|
||||
# SNB caveat
|
||||
%define snb_inst_dir %{buildroot}/%{caveat_dir}/intel-06-2d-07/
|
||||
install -m 755 -d "%{snb_inst_dir}/intel-ucode"
|
||||
install -m 644 intel-ucode-with-caveats/06-2d-07 -t "%{snb_inst_dir}/intel-ucode/"
|
||||
install -m 644 "%{SOURCE120}" "%{snb_inst_dir}/readme"
|
||||
install -m 644 "%{SOURCE121}" "%{snb_inst_dir}/config"
|
||||
install -m 644 "%{SOURCE122}" "%{snb_inst_dir}/disclaimer"
|
||||
|
||||
# SKL-SP caveat
|
||||
%define skl_sp_inst_dir %{buildroot}/%{caveat_dir}/intel-06-55-04/
|
||||
install -m 755 -d "%{skl_sp_inst_dir}/intel-ucode"
|
||||
install -m 644 intel-ucode-with-caveats/06-55-04 -t "%{skl_sp_inst_dir}/intel-ucode/"
|
||||
install -m 644 "%{SOURCE130}" "%{skl_sp_inst_dir}/readme"
|
||||
install -m 644 "%{SOURCE131}" "%{skl_sp_inst_dir}/config"
|
||||
install -m 644 "%{SOURCE132}" "%{skl_sp_inst_dir}/disclaimer"
|
||||
|
||||
# SKL-U/Y caveat
|
||||
%define skl_uy_inst_dir %{buildroot}/%{caveat_dir}/intel-06-4e-03/
|
||||
install -m 755 -d "%{skl_uy_inst_dir}/intel-ucode"
|
||||
@ -373,7 +330,7 @@ exit 0
|
||||
# of RPM name and it has its own versioning scheme both in NVR and uname.
|
||||
# And there's the kernel package split in RHEL 8, so one should look for *-core
|
||||
# and not the main package.
|
||||
pkgs="kernel-core kernel-debug-core kernel-rt-core kernel-rt-debug-core"
|
||||
pkgs="kernel-core kernel-debug-core kernel-rt-core kernel-rt-debug-core kernel-uek-core kernel-uek-debug-core"
|
||||
qf='%%{NAME} %%{VERSION}-%%{RELEASE}.%%{ARCH} %%{installtime}\n'
|
||||
: "${MICROCODE_RPM_KVER_LIMIT=2}"
|
||||
|
||||
@ -386,9 +343,12 @@ rpm -qa --qf "${qf}" ${pkgs} | sort -r -n -k'3,3' | {
|
||||
while read -r pkgname vra install_ts; do
|
||||
flavour=''
|
||||
|
||||
# For x86, only "debug" flavour exists in RHEL 8
|
||||
[ "x${pkgname%*-debug-core}" = "x${pkgname}" ] \
|
||||
|| flavour='+debug'
|
||||
# Fix the uname for debug kernels
|
||||
case "${pkgname}" in
|
||||
kernel-uek-debug-core) flavour='.debug';;
|
||||
kernel-debug-core) flavour='+debug';;
|
||||
*) ;;
|
||||
esac
|
||||
|
||||
kver_cnt="$((kver_cnt + 1))"
|
||||
kver_uname="${vra}${flavour}"
|
||||
@ -545,6 +505,191 @@ rm -rf %{buildroot}
|
||||
|
||||
|
||||
%changelog
|
||||
* Thu Jun 22 2023 Todd Vierling <todd.vierling@oracle.com> - 4:20220809-2.20230214.1.0.1
|
||||
- ensure UEK also rebuilds initramfs [Orabug: 34280058]
|
||||
- add support for UEK7 kernels
|
||||
- enable early update for 06-4f-01
|
||||
- remove no longer appropriate caveats for 06-2d-07 and 06-55-04
|
||||
- enable early and late load on RHCK
|
||||
|
||||
* Wed Feb 15 2023 Eugene Syromiatnikov <esyr@redhat.com> - 4:20220809-2.20230214.1
|
||||
- Update Intel CPU microcode to microcode-20230214 release, addresses
|
||||
CVE-2022-21216, CVE-2022-33196, CVE-2022-33972, CVE-2022-38090 (#2171236,
|
||||
#2171261):
|
||||
- Addition of 06-6c-01/0x10 (ICL-D B0) microcode at revision 0x1000211;
|
||||
- Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode at revision
|
||||
0x2b000181;
|
||||
- Addition of 06-8f-04/0x10 microcode at revision 0x2c000170;
|
||||
- Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
|
||||
intel-ucode/06-8f-04) at revision 0x2b000181;
|
||||
- Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
|
||||
intel-ucode/06-8f-04) at revision 0x2c000170;
|
||||
- Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
|
||||
intel-ucode/06-8f-04) at revision 0x2b000181;
|
||||
- Addition of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-04) at
|
||||
revision 0x2c000170;
|
||||
- Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
|
||||
intel-ucode/06-8f-04) at revision 0x2b000181;
|
||||
- Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
|
||||
intel-ucode/06-8f-04) at revision 0x2b000181;
|
||||
- Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
|
||||
intel-ucode/06-8f-04) at revision 0x2c000170;
|
||||
- Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
|
||||
intel-ucode/06-8f-05) at revision 0x2b000181;
|
||||
- Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) at
|
||||
revision 0x2c000170;
|
||||
- Addition of 06-8f-05/0x87 (SPR-SP E2) microcode at revision
|
||||
0x2b000181;
|
||||
- Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode at revision
|
||||
0x2c000170;
|
||||
- Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
|
||||
intel-ucode/06-8f-05) at revision 0x2b000181;
|
||||
- Addition of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-05) at
|
||||
revision 0x2c000170;
|
||||
- Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
|
||||
intel-ucode/06-8f-05) at revision 0x2b000181;
|
||||
- Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
|
||||
intel-ucode/06-8f-05) at revision 0x2b000181;
|
||||
- Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
|
||||
intel-ucode/06-8f-05) at revision 0x2c000170;
|
||||
- Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
|
||||
intel-ucode/06-8f-06) at revision 0x2b000181;
|
||||
- Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) at
|
||||
revision 0x2c000170;
|
||||
- Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
|
||||
intel-ucode/06-8f-06) at revision 0x2b000181;
|
||||
- Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
|
||||
intel-ucode/06-8f-06) at revision 0x2c000170;
|
||||
- Addition of 06-8f-06/0x87 (SPR-SP E3) microcode at revision
|
||||
0x2b000181;
|
||||
- Addition of 06-8f-06/0x10 microcode at revision 0x2c000170;
|
||||
- Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
|
||||
intel-ucode/06-8f-06) at revision 0x2b000181;
|
||||
- Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
|
||||
intel-ucode/06-8f-06) at revision 0x2b000181;
|
||||
- Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
|
||||
intel-ucode/06-8f-06) at revision 0x2c000170;
|
||||
- Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
|
||||
intel-ucode/06-8f-07) at revision 0x2b000181;
|
||||
- Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
|
||||
intel-ucode/06-8f-07) at revision 0x2b000181;
|
||||
- Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
|
||||
intel-ucode/06-8f-07) at revision 0x2b000181;
|
||||
- Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode at revision
|
||||
0x2b000181;
|
||||
- Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
|
||||
intel-ucode/06-8f-07) at revision 0x2b000181;
|
||||
- Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
|
||||
intel-ucode/06-8f-08) at revision 0x2b000181;
|
||||
- Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) at
|
||||
revision 0x2c000170;
|
||||
- Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
|
||||
intel-ucode/06-8f-08) at revision 0x2b000181;
|
||||
- Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
|
||||
intel-ucode/06-8f-08) at revision 0x2c000170;
|
||||
- Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
|
||||
intel-ucode/06-8f-08) at revision 0x2b000181;
|
||||
- Addition of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) at
|
||||
revision 0x2c000170;
|
||||
- Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
|
||||
intel-ucode/06-8f-08) at revision 0x2b000181;
|
||||
- Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode at revision
|
||||
0x2b000181;
|
||||
- Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode at revision
|
||||
0x2c000170;
|
||||
- Addition of 06-b7-01/0x32 (RPL-S S0) microcode at revision 0x112;
|
||||
- Addition of 06-ba-02/0xc0 microcode at revision 0x410e;
|
||||
- Addition of 06-ba-03/0xc0 microcode (in intel-ucode/06-ba-02) at
|
||||
revision 0x410e;
|
||||
- Addition of 06-ba-02/0xc0 microcode (in intel-ucode/06-ba-03) at
|
||||
revision 0x410e;
|
||||
- Addition of 06-ba-03/0xc0 microcode at revision 0x410e;
|
||||
- Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode (in
|
||||
intel-06-8c-01/intel-ucode/06-8c-01) from revision 0xa4 up to 0xa6;
|
||||
- Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0)
|
||||
microcode (in intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0c) from
|
||||
revision 0xf0 up to 0xf4;
|
||||
- Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode (in
|
||||
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0d) from revision 0xf0 up
|
||||
to 0xf4;
|
||||
- Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x100015e
|
||||
up to 0x1000161;
|
||||
- Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003302
|
||||
up to 0x4003303;
|
||||
- Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision
|
||||
0x5003302 up to 0x5003303;
|
||||
- Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002501
|
||||
up to 0x7002503;
|
||||
- Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000375
|
||||
up to 0xd000389;
|
||||
- Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x3c up
|
||||
to 0x3e;
|
||||
- Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x20 up
|
||||
to 0x22;
|
||||
- Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xb2
|
||||
up to 0xb8;
|
||||
- Update of 06-8a-01/0x10 (LKF B2/B3) microcode from revision 0x31 up
|
||||
to 0x32;
|
||||
- Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x40 up
|
||||
to 0x42;
|
||||
- Update of 06-96-01/0x01 (EHL B1) microcode from revision 0x16 up
|
||||
to 0x17;
|
||||
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision
|
||||
0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
|
||||
intel-ucode/06-97-02) from revision 0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
|
||||
from revision 0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
|
||||
from revision 0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
|
||||
intel-ucode/06-97-05) from revision 0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x22
|
||||
up to 0x2c (old pf 0x3);
|
||||
- Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
|
||||
from revision 0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
|
||||
from revision 0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision
|
||||
0x421 up to 0x429;
|
||||
- Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in
|
||||
intel-ucode/06-9a-03) from revision 0x421 up to 0x429;
|
||||
- Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in
|
||||
intel-ucode/06-9a-04) from revision 0x421 up to 0x429;
|
||||
- Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x421
|
||||
up to 0x429;
|
||||
- Update of 06-9c-00/0x01 (JSL A0/A1) microcode from revision 0x24000023
|
||||
up to 0x24000024;
|
||||
- Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf0 up
|
||||
to 0xf4;
|
||||
- Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf0
|
||||
up to 0xf4;
|
||||
- Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf0
|
||||
up to 0xf4;
|
||||
- Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf0
|
||||
up to 0xf4;
|
||||
- Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision
|
||||
0xf0 up to 0xf4;
|
||||
- Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x54 up
|
||||
to 0x57;
|
||||
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
|
||||
intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
|
||||
intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x22 up to
|
||||
0x2c (old pf 0x3);
|
||||
- Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02)
|
||||
from revision 0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
|
||||
intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
|
||||
intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05)
|
||||
from revision 0x22 up to 0x2c (old pf 0x3);
|
||||
- Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x22 up to
|
||||
0x2c (old pf 0x3).
|
||||
|
||||
>>>>>>> 762178550d1d (Import microcode_ctl-20220809-2.20230214.1.el9_2 for 9.2)
|
||||
* Tue Oct 25 2022 Eugene Syromiatnikov <esyr@redhat.com> - 4:20220809-2
|
||||
- Change the logger severity level to warning to align with the kmsg one
|
||||
(#2136506).
|
||||
|
||||
Loading…
Reference in New Issue
Block a user