From 9da931d46b0b4532d8599abc94d945c2bdd505a8 Mon Sep 17 00:00:00 2001 From: Denys Vlasenko Date: Wed, 3 Dec 2025 12:12:59 +0100 Subject: [PATCH] Update Intel CPU microcode to microcode-20251111 release - Fix typo in /usr/share/microcode_ctl/ucode_with_caveats/intel-06-8f-08/config - Update Intel CPU microcode to microcode-20251111 release (RHEL-128250) - New microcode files (in hex): 06-ae-01: Granite Rapids-D: revision 1000273 - Microcode files (/platform_mask shown) with revision updates (in hex): 06-8f-07/87: Sapphire Rapids: 2b000643 to 2b000650 06-8f-08/10: Sapphire Rapids with HBM: 2c000401 to 2c000410 06-8f-08/87: Sapphire Rapids: 2b000643 to 2b000650 06-97-02/07: Alder Lake: 003a to 003d 06-97-05/07: Alder Lake: 003a to 003d 06-9a-03/80: Alder Lake-L: 0437 to 043a 06-9a-04/80: Alder Lake-L: 0437 to 043a 06-9a-04/40: Arizona Beach (Atom C11xx): 000a to 000b 06-ad-01/95: Granite Rapids-X: 10003d0 to 10003f0 06-ad-01/20: Granite Rapids-X: a000100 to a000124 06-af-03/01: Crestmont (Sierra Forest): 3000362 to 3000382 06-b7-01/32: Raptor Lake: 012f to 0132 06-ba-02/e0: Raptor Lake-P: 4129 to 6133 06-ba-03/e0: Raptor Lake-P: 4129 to 6133 06-bd-01/80: Lunar Lake: 0123 to 0125 06-be-00/19: Gracemont (Alder Lake-N): 001d to 001e 06-bf-02/07: Raptor Lake-S: 003a to 003d 06-bf-05/07: Raptor Lake-S: 003a to 003d 06-c5-02/82: Arrow Lake-H: 0119 to 011a 06-c6-02/82: Arrow Lake: 0119 to 011a 06-cf-02/87: Emerald Rapids: 210002b3 to 210002c0 - Fixes errata RPL070/ADL083/LNL047/ARL054/SPR154/EMR147: "REP SCASB, REP CMPSB may return incorrect results when racing memory access with another core or thread" on Raptor Lake, Alder Lake, Lunar Lake, Arrow Lake, Sapphire Rapids, Emerald Rapids. Resolves: RHEL-128250 Signed-off-by: Denys Vlasenko --- ...senote.md-use-new-lines-consistently.patch | 8 ----- ...dd-information-about-removal-of-CLX-.patch | 2 +- ...rop-Removed-Platforms-from-microcode.patch | 6 ++-- 06-8f-08_config | 2 +- microcode_ctl.spec | 34 ++++++++++++++++++- sources | 2 +- 6 files changed, 39 insertions(+), 15 deletions(-) diff --git a/0016-releasenote.md-use-new-lines-consistently.patch b/0016-releasenote.md-use-new-lines-consistently.patch index 7d20c9a..e5e0dd3 100644 --- a/0016-releasenote.md-use-new-lines-consistently.patch +++ b/0016-releasenote.md-use-new-lines-consistently.patch @@ -19,14 +19,6 @@ diff --git a/releasenote.md b/releasenote.md index 0cdfa20..3c700b5 100644 --- a/releasenote.md +++ b/releasenote.md -@@ -156,6 +156,7 @@ - |:---------------|:---------|:------------|:---------|:---------|:--------- - | CFL-H/S | P0 | 06-9e-0c/22 | 000000f6 | 000000f8 | Core Gen9 - -+ - ## [microcode-20241112](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20241112) - - ### Purpose @@ -164,6 +165,7 @@ - Security updates for [INTEL-SA-01079](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01079.html) - Updated security updates for [INTEL-SA-01097](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01097.html) diff --git a/0017-releasenote.md-add-information-about-removal-of-CLX-.patch b/0017-releasenote.md-add-information-about-removal-of-CLX-.patch index b49f1fa..b425178 100644 --- a/0017-releasenote.md-add-information-about-removal-of-CLX-.patch +++ b/0017-releasenote.md-add-information-about-removal-of-CLX-.patch @@ -31,7 +31,7 @@ index 3c700b5..d42e9ad 100644 +| CLX-SP | B0 | 06-55-06/bf | 04003605 | | Xeon Scalable Gen2 +| EMR-SP | A0 | 06-cf-01/87 | 21000291 | | Xeon Scalable Gen5 + - + # Release Notes ## [microcode-20250211](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20250211) -- diff --git a/0101-releasenote.md-drop-Removed-Platforms-from-microcode.patch b/0101-releasenote.md-drop-Removed-Platforms-from-microcode.patch index 5dce5ad..6ffac1b 100644 --- a/0101-releasenote.md-drop-Removed-Platforms-from-microcode.patch +++ b/0101-releasenote.md-drop-Removed-Platforms-from-microcode.patch @@ -17,7 +17,7 @@ diff --git a/releasenote.md b/releasenote.md index d42e9ad..e46f6f0 100644 --- a/releasenote.md +++ b/releasenote.md -@@ -85,13 +85,6 @@ +@@ -188,13 +188,6 @@ | TWL | N0 | 06-be-00/19 | 0000001c | 0000001d | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E | WHL-U | V0 | 06-8e-0c/94 | 000000fc | 00000100 | Core Gen8 Mobile @@ -28,10 +28,10 @@ index d42e9ad..e46f6f0 100644 -| CLX-SP | B0 | 06-55-06/bf | 04003605 | | Xeon Scalable Gen2 -| EMR-SP | A0 | 06-cf-01/87 | 21000291 | | Xeon Scalable Gen5 - - + # Release Notes ## [microcode-20250211](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20250211) -@@ -149,14 +142,6 @@ +@@ -252,14 +245,6 @@ | SPR-SP | E5/S3 | 06-8f-08/87 | 2b000603 | 2b000620 | Xeon Scalable Gen4 | TWL | N0 | 06-be-00/19 | 0000001a | 0000001c | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E diff --git a/06-8f-08_config b/06-8f-08_config index c069767..9e9477d 100644 --- a/06-8f-08_config +++ b/06-8f-08_config @@ -1,5 +1,5 @@ model GenuineIntel 06-8f-08 -path intel-ucode/06-87-08 +path intel-ucode/06-8f-08 ## A possible way to disable 0x2b000603 and newer microcode on SPR-EE by default ## Based on https://cdrdv2.intel.com/v1/dl/getcontent/772415 ## and https://cdrdv2.intel.com/v1/dl/getcontent/784461 diff --git a/microcode_ctl.spec b/microcode_ctl.spec index 5e21935..0f2a350 100644 --- a/microcode_ctl.spec +++ b/microcode_ctl.spec @@ -1,4 +1,4 @@ -%define intel_ucode_version 20250812 +%define intel_ucode_version 20251111 %global debug_package %{nil} %define caveat_dir %{_datarootdir}/microcode_ctl/ucode_with_caveats @@ -636,6 +636,38 @@ rm -rf %{buildroot} %changelog +* Mon Nov 24 2025 Denys Vlasenko - 4:20251111-1 +- Fix typo in /usr/share/microcode_ctl/ucode_with_caveats/intel-06-8f-08/config +- Update Intel CPU microcode to microcode-20251111 release (RHEL-128250) +- New microcode files (in hex): + 06-ae-01: Granite Rapids-D: revision 1000273 +- Microcode files (/platform_mask shown) with revision updates (in hex): + 06-8f-07/87: Sapphire Rapids: 2b000643 to 2b000650 + 06-8f-08/10: Sapphire Rapids with HBM: 2c000401 to 2c000410 + 06-8f-08/87: Sapphire Rapids: 2b000643 to 2b000650 + 06-97-02/07: Alder Lake: 003a to 003d + 06-97-05/07: Alder Lake: 003a to 003d + 06-9a-03/80: Alder Lake-L: 0437 to 043a + 06-9a-04/80: Alder Lake-L: 0437 to 043a + 06-9a-04/40: Arizona Beach (Atom C11xx): 000a to 000b + 06-ad-01/95: Granite Rapids-X: 10003d0 to 10003f0 + 06-ad-01/20: Granite Rapids-X: a000100 to a000124 + 06-af-03/01: Crestmont (Sierra Forest): 3000362 to 3000382 + 06-b7-01/32: Raptor Lake: 012f to 0132 + 06-ba-02/e0: Raptor Lake-P: 4129 to 6133 + 06-ba-03/e0: Raptor Lake-P: 4129 to 6133 + 06-bd-01/80: Lunar Lake: 0123 to 0125 + 06-be-00/19: Gracemont (Alder Lake-N): 001d to 001e + 06-bf-02/07: Raptor Lake-S: 003a to 003d + 06-bf-05/07: Raptor Lake-S: 003a to 003d + 06-c5-02/82: Arrow Lake-H: 0119 to 011a + 06-c6-02/82: Arrow Lake: 0119 to 011a + 06-cf-02/87: Emerald Rapids: 210002b3 to 210002c0 +- Fixes errata RPL070/ADL083/LNL047/ARL054/SPR154/EMR147: + "REP SCASB, REP CMPSB may return incorrect results when racing + memory access with another core or thread" on Raptor Lake, + Alder Lake, Lunar Lake, Arrow Lake, Sapphire Rapids, Emerald Rapids. + * Wed Aug 20 2025 Denys Vlasenko - 4:20250812-1 - Update Intel CPU microcode to microcode-20250812 release - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000404 diff --git a/sources b/sources index b557975..d10c7bc 100644 --- a/sources +++ b/sources @@ -1,6 +1,6 @@ SHA512 (microcode-20190918.tar.gz) = 82e5212238d3e35470d139240d9157877ac252725598ec31bfe1763755681539a4ecdf24e04c4e4270215578a9ca3c063c8fc353accf99999c3d4ac2780a6e0c SHA512 (microcode-20191115.tar.gz) = 11014c16bde83ac290bc75e458242f5e64b8dffd49de2e938f61f4a09979cd5e80dd1a85d2ccbac067e4398dc3d93ef3583e4aa9b2e545ba46d26e65ec1e2881 -SHA512 (microcode-20250812.tar.gz) = 5c21676d1c1783c937c78ca00b9f8d9a870bc7dfdde564bdf2ba277931223fa8d6a2f21d6a0e6249b4ba8ccc2e47d5b3cbf41cc5edc08360c909b3f1c7f2dec1 +SHA512 (microcode-20251111.tar.gz) = a11ded3158d761ae68258ca61a15014258d68ea28e9e9c94c125a49490a1df0f4b5c6cc37e97b42d84594760e455a1444feb2106e920ea6dd09934e545d92188 SHA512 (06-2d-07) = 631ec8ad8ad3c9b32d9569689f673010d26c13c7cc377d66b8fc5150de52485076d1514ba867dfa4f468889a31d6701cd8a0789d465ad069d98c8ea0f5bd3204 SHA512 (06-4e-03) = 248066b521bf512b5d8e4a8c7e921464ce52169c954d6e4ca580d8c172cd789519e22b4cf56c212e452b4191741f0202019f7061d322c9433b5af9ce5413b567 SHA512 (06-55-04) = db2783cd62680510a7105e7c3fd9d5fffac6a33159ba811f4669f8afb9a5badde4c009bf1868e6a53eb3ac2286812404127bcd45fcbc65fe004788e25ae3e222