From 735fed49e18c13ba22e6f66f56c60f9334080e39 Mon Sep 17 00:00:00 2001 From: Eugene Syromiatnikov Date: Wed, 20 Nov 2024 14:07:42 +0100 Subject: [PATCH] Update Intel CPU microcode to microcode-20241112 release - Update Intel CPU microcode to microcode-20241112 release, addresses CVE-2024-21820, CVE-2024-21853, CVE-2024-23918, CVE-2024-23984: - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision 0x2b0005c0 up to 0x2b000603; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision 0x36 up to 0x37; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-97-02) from revision 0x36 up to 0x37; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x36 up to 0x37; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x36 up to 0x37; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x36 up to 0x37; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x36 up to 0x37; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x36 up to 0x37; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x36 up to 0x37; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision 0x434 up to 0x435; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in intel-ucode/06-9a-03) from revision 0x434 up to 0x435; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in intel-ucode/06-9a-04) from revision 0x434 up to 0x435; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x434 up to 0x435; - Update of 06-aa-04/0xe6 (MTL-H/U C0) microcode from revision 0x1f up to 0x20; - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x129 up to 0x12b; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision 0x4122 up to 0x4123; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-02) from revision 0x4122 up to 0x4123; - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) from revision 0x4122 up to 0x4123; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-03) from revision 0x4122 up to 0x4123; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4122 up to 0x4123; - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) from revision 0x4122 up to 0x4123; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-08) from revision 0x4122 up to 0x4123; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-08) from revision 0x4122 up to 0x4123; - Update of 06-ba-08/0xe0 microcode from revision 0x4122 up to 0x4123; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-02) from revision 0x36 up to 0x37; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-02) from revision 0x36 up to 0x37; - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x36 up to 0x37; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) from revision 0x36 up to 0x37; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x36 up to 0x37; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-05) from revision 0x36 up to 0x37; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) from revision 0x36 up to 0x37; - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x36 up to 0x37; - Update of 06-cf-01/0x87 (EMR-SP A0) microcode from revision 0x21000230 up to 0x21000283; - Update of 06-cf-02/0x87 (EMR-SP A1) microcode (in intel-ucode/06-cf-01) from revision 0x21000230 up to 0x21000283; - Update of 06-cf-01/0x87 (EMR-SP A0) microcode (in intel-ucode/06-cf-02) from revision 0x21000230 up to 0x21000283; - Update of 06-cf-02/0x87 (EMR-SP A1) microcode from revision 0x21000230 up to 0x21000283. * .gitignore: Replace /microcode-20240910.tar.gz entry with /microcode-20241112.tar.gz. * microcode_ctl.spec (intel_ucode_version): Bump to 20241112. (Release): Reset to 1. (%changelog): Add a record, fix a typo in the previous one. * sources: Replace microcode-20240910.tar.gz record with microcode-20241112.tar.gz. Resolves: RHEL-67335 Signed-off-by: Eugene Syromiatnikov --- .gitignore | 1 + microcode_ctl.spec | 119 +++++++++++++++++++++++++++++++++++++++++++-- sources | 2 +- 3 files changed, 118 insertions(+), 4 deletions(-) diff --git a/.gitignore b/.gitignore index 16ae4f1..aa64001 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,3 @@ /microcode-20240531.tar.gz /microcode-20240910.tar.gz +/microcode-20241112.tar.gz diff --git a/microcode_ctl.spec b/microcode_ctl.spec index ee71cfa..cf4722b 100644 --- a/microcode_ctl.spec +++ b/microcode_ctl.spec @@ -1,4 +1,4 @@ -%define intel_ucode_version 20240910 +%define intel_ucode_version 20241112 %define caveat_dir %{_datarootdir}/microcode_ctl/ucode_with_caveats %define microcode_ctl_libexec %{_libexecdir}/microcode_ctl @@ -12,7 +12,7 @@ Summary: CPU microcode updates for Intel x86 processors Name: microcode_ctl Version: %{intel_ucode_version} -Release: 2%{?dist} +Release: 1%{?dist} Epoch: 4 License: CC0 and Redistributable, no modification permitted URL: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files @@ -397,13 +397,126 @@ rm -rf %{buildroot} %changelog +* Tue Nov 19 2024 Eugene Syromiatnikov - 4:20241112-1 +- Update Intel CPU microcode to microcode-20241112 release, addresses + CVE-2024-21820, CVE-2024-21853, CVE-2024-23918, CVE-2024-23984 (RHEL-67335): + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in + intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b0005c0 + up to 0x2b000603; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in + intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in + intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in + intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in + intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in + intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b0005c0 + up to 0x2b000603; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in + intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in + intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in + intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in + intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in + intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision + 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in + intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in + intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in + intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in + intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in + intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603; + - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision + 0x2b0005c0 up to 0x2b000603; + - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision + 0x36 up to 0x37; + - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in + intel-ucode/06-97-02) from revision 0x36 up to 0x37; + - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) + from revision 0x36 up to 0x37; + - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) + from revision 0x36 up to 0x37; + - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in + intel-ucode/06-97-05) from revision 0x36 up to 0x37; + - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x36 + up to 0x37; + - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) + from revision 0x36 up to 0x37; + - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) + from revision 0x36 up to 0x37; + - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision + 0x434 up to 0x435; + - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in + intel-ucode/06-9a-03) from revision 0x434 up to 0x435; + - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in + intel-ucode/06-9a-04) from revision 0x434 up to 0x435; + - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x434 + up to 0x435; + - Update of 06-aa-04/0xe6 (MTL-H/U C0) microcode from revision 0x1f + up to 0x20; + - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x129 up + to 0x12b; + - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision + 0x4122 up to 0x4123; + - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in + intel-ucode/06-ba-02) from revision 0x4122 up to 0x4123; + - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) from + revision 0x4122 up to 0x4123; + - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in + intel-ucode/06-ba-03) from revision 0x4122 up to 0x4123; + - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4122 + up to 0x4123; + - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) from + revision 0x4122 up to 0x4123; + - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in + intel-ucode/06-ba-08) from revision 0x4122 up to 0x4123; + - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in + intel-ucode/06-ba-08) from revision 0x4122 up to 0x4123; + - Update of 06-ba-08/0xe0 microcode from revision 0x4122 up to 0x4123; + - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in + intel-ucode/06-bf-02) from revision 0x36 up to 0x37; + - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in + intel-ucode/06-bf-02) from revision 0x36 up to 0x37; + - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x36 up + to 0x37; + - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) + from revision 0x36 up to 0x37; + - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in + intel-ucode/06-bf-05) from revision 0x36 up to 0x37; + - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in + intel-ucode/06-bf-05) from revision 0x36 up to 0x37; + - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) + from revision 0x36 up to 0x37; + - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x36 up + to 0x37; + - Update of 06-cf-01/0x87 (EMR-SP A0) microcode from revision 0x21000230 + up to 0x21000283; + - Update of 06-cf-02/0x87 (EMR-SP A1) microcode (in + intel-ucode/06-cf-01) from revision 0x21000230 up to 0x21000283; + - Update of 06-cf-01/0x87 (EMR-SP A0) microcode (in + intel-ucode/06-cf-02) from revision 0x21000230 up to 0x21000283; + - Update of 06-cf-02/0x87 (EMR-SP A1) microcode from revision 0x21000230 + up to 0x21000283. + * Tue Oct 29 2024 Troy Dawson - 4:20240910-2 - Bump release for October 2024 mass rebuild: Resolves: RHEL-64018 * Mon Sep 23 2024 Eugene Syromiatnikov - 4:20240910-1 - Update Intel CPU microcode to microcode-20240910 release, addresses -- Addresses CVE-2024-23984, CVE-2024-24853, CVE-2024-24968, CVE-2024-24980, + CVE-2024-23984, CVE-2024-24853, CVE-2024-24968, CVE-2024-24980, CVE-2024-25939 (RHEL-58058): - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision 0x5003605 up to 0x5003707; diff --git a/sources b/sources index 818bd12..56ce129 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (microcode-20240910.tar.gz) = d996de4f045df33f4eb1a1dabfb2f55bd8941e8dc16241d7a6c361216f4b87b88c34ba57c88ee4d4b7b3cf2b3fac937c43806191681df031fa3d5cdd677a86fe +SHA512 (microcode-20241112.tar.gz) = de4ddb0a77e17a4a5b6789537cf71db9ab884c795ef5c77b17d3392fda0fbb4d860cc27bcdbd7512d9412d6f934e6771e889be262b20e77433e0f72d3b6cf1f0