diff --git a/microcode_ctl.spec b/microcode_ctl.spec index 0f2a350..07be61f 100644 --- a/microcode_ctl.spec +++ b/microcode_ctl.spec @@ -1,4 +1,4 @@ -%define intel_ucode_version 20251111 +%define intel_ucode_version 20260210 %global debug_package %{nil} %define caveat_dir %{_datarootdir}/microcode_ctl/ucode_with_caveats @@ -636,6 +636,41 @@ rm -rf %{buildroot} %changelog +* Wed Feb 25 2026 Denys Vlasenko - 4:20260210-1 +- Update Intel CPU microcode to microcode-20260210 release (RHEL-151645) +- Microcode files (/platform_mask shown) with revision updates (in hex): + 06-6a-06/87: Ice Lake-X: d000410 to d000421 + 06-6c-01/10: Ice Lake-D: 10002e0 to 10002f1 + 06-7e-05/80: Ice Lake-L: 00ca to 00cc + 06-8c-01/80: Tiger Lake: 00bc to 00be + 06-8c-02/c2: Tiger Lake: 003c to 003e + 06-8d-01/c2: Tiger Lake-H: 0056 to 0058 + 06-8f-07/87: Sapphire Rapids: 2b000650 to 2b000661 + 06-8f-08/10: Sapphire Rapids with HBM: 2c000410 to 2c000421 + 06-8f-08/87: Sapphire Rapids: 2b000650 to 2b000661 + 06-97-02/07: Alder Lake: 003d to 003e + 06-97-05/07: Alder Lake: 003d to 003e + 06-9a-03/80: Alder Lake-L: 043a to 043b + 06-9a-04/80: Alder Lake-L: 043a to 043b + 06-9a-04/40: Arizona Beach (Atom C11xx): 000b to 000c + 06-9a-04/80: Alder Lake-L: 043a to 043b + 06-a7-01/02: Rocket Lake: 0064 to 0065 + 06-aa-04/e6: Meteor Lake-L: 0025 to 0028 + 06-ad-01/20: Granite Rapids-X: a000124 to a000133 + 06-ad-01/95: Granite Rapids-X: 10003f0 to 1000405 + 06-ae-01/97: Granite Rapids-D: 1000273 to 10002f3 + 06-b5-00/80: Arrow Lake-U: 000a to 000d + 06-b7-01/32: Raptor Lake: 0132 to 0133 + 06-ba-02/e0: Raptor Lake-P: 6133 to 6134 + 06-ba-03/e0: Raptor Lake-P: 6133 to 6134 + 06-be-00/19: Gracemont (Alder Lake-N): 001e to 0021 + 06-bf-02/07: Raptor Lake-S: 003d to 003e + 06-bf-05/07: Raptor Lake-S: 003d to 003e + 06-c5-02/82: Arrow Lake-H: 011a to 011b + 06-c6-02/82: Arrow Lake: 011a to 011b + 06-cf-02/87: Emerald Rapids: 210002c0 to 210002d3 +Resolves: RHEL-151757 + * Mon Nov 24 2025 Denys Vlasenko - 4:20251111-1 - Fix typo in /usr/share/microcode_ctl/ucode_with_caveats/intel-06-8f-08/config - Update Intel CPU microcode to microcode-20251111 release (RHEL-128250) diff --git a/sources b/sources index d10c7bc..95cf882 100644 --- a/sources +++ b/sources @@ -1,6 +1,6 @@ SHA512 (microcode-20190918.tar.gz) = 82e5212238d3e35470d139240d9157877ac252725598ec31bfe1763755681539a4ecdf24e04c4e4270215578a9ca3c063c8fc353accf99999c3d4ac2780a6e0c SHA512 (microcode-20191115.tar.gz) = 11014c16bde83ac290bc75e458242f5e64b8dffd49de2e938f61f4a09979cd5e80dd1a85d2ccbac067e4398dc3d93ef3583e4aa9b2e545ba46d26e65ec1e2881 -SHA512 (microcode-20251111.tar.gz) = a11ded3158d761ae68258ca61a15014258d68ea28e9e9c94c125a49490a1df0f4b5c6cc37e97b42d84594760e455a1444feb2106e920ea6dd09934e545d92188 +SHA512 (microcode-20260210.tar.gz) = ec4ed32600ce1ce2c9c52796458f92205c89c38ba2834d84ab86d800790c709d22cb66e4fca5edda42752363956324f8066d08e3b1d81c50ac879d2749068655 SHA512 (06-2d-07) = 631ec8ad8ad3c9b32d9569689f673010d26c13c7cc377d66b8fc5150de52485076d1514ba867dfa4f468889a31d6701cd8a0789d465ad069d98c8ea0f5bd3204 SHA512 (06-4e-03) = 248066b521bf512b5d8e4a8c7e921464ce52169c954d6e4ca580d8c172cd789519e22b4cf56c212e452b4191741f0202019f7061d322c9433b5af9ce5413b567 SHA512 (06-55-04) = db2783cd62680510a7105e7c3fd9d5fffac6a33159ba811f4669f8afb9a5badde4c009bf1868e6a53eb3ac2286812404127bcd45fcbc65fe004788e25ae3e222