From 622ec2258563274ff8975c25e51935729ea1d836 Mon Sep 17 00:00:00 2001 From: Eugene Syromiatnikov Date: Wed, 25 Sep 2024 15:49:23 +0200 Subject: [PATCH] Update Intel CPU microcode to microcode-20240910 release - Update Intel CPU microcode to microcode-20240910 release, addresses - Addresses CVE-2024-23984, CVE-2024-24853, CVE-2024-24968, CVE-2024-24980, CVE-2024-25939: - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision 0x5003605 up to 0x5003707; - Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002802 up to 0x7002904; - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd0003d1 up to 0xd0003e7; - Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x1000290 up to 0x10002b0; - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xc4 up to 0xc6; - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode from revision 0xb6 up to 0xb8; - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x36 up to 0x38; - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x50 up to 0x52; - Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode from revision 0xf4 up to 0xf6; - Update of 06-8e-09/0xc0 (KBL-U/U 2+3e/Y H0/J1) microcode from revision 0xf4 up to 0xf6; - Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode from revision 0xf4 up to 0xf6; - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xf4 up to 0xf6; - Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0) microcode from revision 0xfa up to 0xfc; - Update of 06-96-01/0x01 (EHL B1) microcode from revision 0x19 up to 0x1a; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision 0x35 up to 0x36; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-97-02) from revision 0x35 up to 0x36; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x35 up to 0x36; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x35 up to 0x36; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x35 up to 0x36; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x35 up to 0x36; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x35 up to 0x36; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x35 up to 0x36; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision 0x433 up to 0x434; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in intel-ucode/06-9a-03) from revision 0x433 up to 0x434; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in intel-ucode/06-9a-04) from revision 0x433 up to 0x434; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x433 up to 0x434; - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode from revision 0xf6 up to 0xf8; - Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode from revision 0xf4 up to 0xf6; - Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode from revision 0xf6 up to 0xf8; - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode from revision 0xfc up to 0x100; - Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xfa up to 0xfc; - Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xfa up to 0xfc; - Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xfa up to 0xfc; - Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xfa up to 0xfe; - Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision 0xfa up to 0xfc; - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x5e up to 0x62; - Update of 06-aa-04/0xe6 (MTL-H/U C0) microcode from revision 0x1c up to 0x1f; - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x123 up to 0x129; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision 0x4121 up to 0x4122; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-02) from revision 0x4121 up to 0x4122; - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) from revision 0x4121 up to 0x4122; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-03) from revision 0x4121 up to 0x4122; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4121 up to 0x4122; - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) from revision 0x4121 up to 0x4122; - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-08) from revision 0x4121 up to 0x4122; - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-08) from revision 0x4121 up to 0x4122; - Update of 06-ba-08/0xe0 microcode from revision 0x4121 up to 0x4122; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-02) from revision 0x35 up to 0x36; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-02) from revision 0x35 up to 0x36; - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x35 up to 0x36; - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) from revision 0x35 up to 0x36; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x35 up to 0x36; - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-05) from revision 0x35 up to 0x36; - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) from revision 0x35 up to 0x36; - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x35 up to 0x36; - Update of 06-be-00/0x19 (ADL-N A0) microcode from revision 0x17 up to 0x1a (old pf 0x11). * .gitignore: Add /microcode-20240910.tar.gz entry. * microcode_ctl.spec (intel_ucode_version): Bump to 20240910. (%changelog): Add a record. * sources: Replace microcode-20240531.tar.gz record with microcode-20240910.tar.gz. Resolves: RHEL-58058 Signed-off-by: Eugene Syromiatnikov --- .gitignore | 1 + microcode_ctl.spec | 118 ++++++++++++++++++++++++++++++++++++++++++++- sources | 2 +- 3 files changed, 119 insertions(+), 2 deletions(-) diff --git a/.gitignore b/.gitignore index 6f24c19..16ae4f1 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1,2 @@ /microcode-20240531.tar.gz +/microcode-20240910.tar.gz diff --git a/microcode_ctl.spec b/microcode_ctl.spec index ae67913..f786888 100644 --- a/microcode_ctl.spec +++ b/microcode_ctl.spec @@ -1,4 +1,4 @@ -%define intel_ucode_version 20240531 +%define intel_ucode_version 20240910 %define caveat_dir %{_datarootdir}/microcode_ctl/ucode_with_caveats %define microcode_ctl_libexec %{_libexecdir}/microcode_ctl @@ -397,6 +397,122 @@ rm -rf %{buildroot} %changelog +* Mon Sep 23 2024 Eugene Syromiatnikov - 4:20240910-1 +- Update Intel CPU microcode to microcode-20240910 release, addresses +- Addresses CVE-2024-23984, CVE-2024-24853, CVE-2024-24968, CVE-2024-24980, + CVE-2024-25939 (RHEL-58058): + - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision + 0x5003605 up to 0x5003707; + - Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002802 + up to 0x7002904; + - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd0003d1 + up to 0xd0003e7; + - Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x1000290 + up to 0x10002b0; + - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xc4 + up to 0xc6; + - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode from revision + 0xb6 up to 0xb8; + - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x36 up + to 0x38; + - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x50 up + to 0x52; + - Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode from revision 0xf4 + up to 0xf6; + - Update of 06-8e-09/0xc0 (KBL-U/U 2+3e/Y H0/J1) microcode from revision + 0xf4 up to 0xf6; + - Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode from + revision 0xf4 up to 0xf6; + - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xf4 up + to 0xf6; + - Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0) + microcode from revision 0xfa up to 0xfc; + - Update of 06-96-01/0x01 (EHL B1) microcode from revision 0x19 up + to 0x1a; + - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision + 0x35 up to 0x36; + - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in + intel-ucode/06-97-02) from revision 0x35 up to 0x36; + - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) + from revision 0x35 up to 0x36; + - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) + from revision 0x35 up to 0x36; + - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in + intel-ucode/06-97-05) from revision 0x35 up to 0x36; + - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x35 + up to 0x36; + - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) + from revision 0x35 up to 0x36; + - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) + from revision 0x35 up to 0x36; + - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision + 0x433 up to 0x434; + - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in + intel-ucode/06-9a-03) from revision 0x433 up to 0x434; + - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in + intel-ucode/06-9a-04) from revision 0x433 up to 0x434; + - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x433 + up to 0x434; + - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode from revision + 0xf6 up to 0xf8; + - Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode from revision 0xf4 + up to 0xf6; + - Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode from revision + 0xf6 up to 0xf8; + - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode from revision + 0xfc up to 0x100; + - Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xfa up + to 0xfc; + - Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xfa + up to 0xfc; + - Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xfa + up to 0xfc; + - Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xfa + up to 0xfe; + - Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision + 0xfa up to 0xfc; + - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x5e up + to 0x62; + - Update of 06-aa-04/0xe6 (MTL-H/U C0) microcode from revision 0x1c + up to 0x1f; + - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x123 up + to 0x129; + - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision + 0x4121 up to 0x4122; + - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in + intel-ucode/06-ba-02) from revision 0x4121 up to 0x4122; + - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) from + revision 0x4121 up to 0x4122; + - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in + intel-ucode/06-ba-03) from revision 0x4121 up to 0x4122; + - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4121 + up to 0x4122; + - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) from + revision 0x4121 up to 0x4122; + - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in + intel-ucode/06-ba-08) from revision 0x4121 up to 0x4122; + - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in + intel-ucode/06-ba-08) from revision 0x4121 up to 0x4122; + - Update of 06-ba-08/0xe0 microcode from revision 0x4121 up to 0x4122; + - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in + intel-ucode/06-bf-02) from revision 0x35 up to 0x36; + - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in + intel-ucode/06-bf-02) from revision 0x35 up to 0x36; + - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x35 up + to 0x36; + - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) + from revision 0x35 up to 0x36; + - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in + intel-ucode/06-bf-05) from revision 0x35 up to 0x36; + - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in + intel-ucode/06-bf-05) from revision 0x35 up to 0x36; + - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) + from revision 0x35 up to 0x36; + - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x35 up + to 0x36; + - Update of 06-be-00/0x19 (ADL-N A0) microcode from revision 0x17 up + to 0x1a (old pf 0x11). + * Fri Jul 26 2024 Eugene Syromiatnikov - 4:20240531-1 - Bring in RHEL-specific packaging bits. diff --git a/sources b/sources index c76fa69..818bd12 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -SHA512 (microcode-20240531.tar.gz) = fb9d772491f279ebb691248e4a665da45c986ca7b4668ecf311c5fcb91a42400f7a5b35e8bfc31ceb1c9d598e753c817359900e3fa316d825f8ecec21ec63cfe +SHA512 (microcode-20240910.tar.gz) = d996de4f045df33f4eb1a1dabfb2f55bd8941e8dc16241d7a6c361216f4b87b88c34ba57c88ee4d4b7b3cf2b3fac937c43806191681df031fa3d5cdd677a86fe