diff --git a/microcode_ctl.spec b/microcode_ctl.spec
index d1b8ffe..5e21935 100644
--- a/microcode_ctl.spec
+++ b/microcode_ctl.spec
@@ -1,4 +1,4 @@
-%define intel_ucode_version 20250512
+%define intel_ucode_version 20250812
 %global debug_package %{nil}
 
 %define caveat_dir %{_datarootdir}/microcode_ctl/ucode_with_caveats
@@ -636,6 +636,83 @@ rm -rf %{buildroot}
 
 
 %changelog
+* Wed Aug 20 2025 Denys Vlasenko <dvlasenk@redhat.com> - 4:20250812-1
+- Update Intel CPU microcode to microcode-20250812 release
+  - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000404
+    up to 0xd000410;
+  - Update of 06-6c-01/0x10 (ICL-D B0) microcode from revision 0x10002d0
+    up to 0x10002e0;
+  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-07) from revision 0x2b000639 up to 0x2b000643;
+  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-07) from revision 0x2b000639 up to 0x2b000643;
+  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-07) from revision 0x2b000639 up to 0x2b000643;
+  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision
+    0x2b000639 up to 0x2b000643;
+  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-07) from revision 0x2b000639 up to 0x2b000643;
+  - Update of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) from
+    revision 0x2c0003f7 up to 0x2c000401;
+  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2b000639 up to 0x2b000643;
+  - Update of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2c0003f7 up to 0x2c000401;
+  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2b000639 up to 0x2b000643;
+  - Update of 06-8f-06/0x10 microcode (in intel-ucode/06-8f-08) from
+    revision 0x2c0003f7 up to 0x2c000401;
+  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2b000639 up to 0x2b000643;
+  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2b000639 up to 0x2b000643;
+  - Update of 06-8f-08/0x10 (SPR-HBM B3) microcode from revision
+    0x2c0003f7 up to 0x2c000401;
+  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision
+    0x2b000639 up to 0x2b000643;
+  - Update of 06-aa-04/0xe6 (MTL-H/U C0) microcode from revision 0x24
+    up to 0x25;
+  - Update of 06-ad-01/0x20 (GNR-AP/SP H0) microcode from revision
+    0xa0000d1 up to 0xa000100;
+  - Update of 06-ad-01/0x95 (GNR-AP/SP B0) microcode from revision
+    0x10003a2 up to 0x10003d0;
+  - Update of 06-af-03/0x01 (SRF-SP C0) microcode from revision 0x3000341
+    up to 0x3000362;
+  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision
+    0x4128 up to 0x4129;
+  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
+    intel-ucode/06-ba-02) from revision 0x4128 up to 0x4129;
+  - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) from
+    revision 0x4128 up to 0x4129;
+  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
+    intel-ucode/06-ba-03) from revision 0x4128 up to 0x4129;
+  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4128
+    up to 0x4129;
+  - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) from
+    revision 0x4128 up to 0x4129;
+  - Update of 06-bd-01/0x80 (LNL B0) microcode from revision 0x11f up
+    to 0x123;
+  - Update of 06-c5-02/0x82 (ARL-H A1) microcode from revision 0x118 up
+    to 0x119;
+  - Update of 06-c6-02/0x82 (ARL-HX 8P/S B0) microcode (in
+    intel-ucode/06-c5-02) from revision 0x118 up to 0x119;
+  - Update of 06-c6-04/0x82 microcode (in intel-ucode/06-c5-02) from
+    revision 0x118 up to 0x119;
+  - Update of 06-ca-02/0x82 microcode (in intel-ucode/06-c5-02) from
+    revision 0x118 up to 0x119;
+  - Update of 06-c5-02/0x82 (ARL-H A1) microcode (in intel-ucode/06-c6-02)
+    from revision 0x118 up to 0x119;
+  - Update of 06-c6-02/0x82 (ARL-HX 8P/S B0) microcode from revision
+    0x118 up to 0x119;
+  - Update of 06-c6-04/0x82 microcode (in intel-ucode/06-c6-02) from
+    revision 0x118 up to 0x119;
+  - Update of 06-ca-02/0x82 microcode (in intel-ucode/06-c6-02) from
+    revision 0x118 up to 0x119;
+  - Update of 06-cf-01/0x87 (EMR-SP A0) microcode (in
+    intel-ucode/06-cf-02) from revision 0x210002a9 up to 0x210002b3;
+  - Update of 06-cf-02/0x87 (EMR-SP A1) microcode from revision 0x210002a9
+    up to 0x210002b3.
+
 * Tue Jun 10 2025 Denys Vlasenko <dvlasenk@redhat.com> - 4:20250512-1
 - Add a caveat to provide ability to persistently disable SPR-EE updates
   beyond 0x2b0005c0 on systems where absence of latency spikes
diff --git a/sources b/sources
index 4a64829..b557975 100644
--- a/sources
+++ b/sources
@@ -1,6 +1,6 @@
 SHA512 (microcode-20190918.tar.gz) = 82e5212238d3e35470d139240d9157877ac252725598ec31bfe1763755681539a4ecdf24e04c4e4270215578a9ca3c063c8fc353accf99999c3d4ac2780a6e0c
 SHA512 (microcode-20191115.tar.gz) = 11014c16bde83ac290bc75e458242f5e64b8dffd49de2e938f61f4a09979cd5e80dd1a85d2ccbac067e4398dc3d93ef3583e4aa9b2e545ba46d26e65ec1e2881
-SHA512 (microcode-20250512.tar.gz) = 7c22448eaec64a09562fc05da59e8b77bd828ff7a8c2973a012eb5e2cf92a6cfff6e770e379f5db4a8d633de610be6f02ddd033351505a2b8180e3982d63a49e
+SHA512 (microcode-20250812.tar.gz) = 5c21676d1c1783c937c78ca00b9f8d9a870bc7dfdde564bdf2ba277931223fa8d6a2f21d6a0e6249b4ba8ccc2e47d5b3cbf41cc5edc08360c909b3f1c7f2dec1
 SHA512 (06-2d-07) = 631ec8ad8ad3c9b32d9569689f673010d26c13c7cc377d66b8fc5150de52485076d1514ba867dfa4f468889a31d6701cd8a0789d465ad069d98c8ea0f5bd3204
 SHA512 (06-4e-03) = 248066b521bf512b5d8e4a8c7e921464ce52169c954d6e4ca580d8c172cd789519e22b4cf56c212e452b4191741f0202019f7061d322c9433b5af9ce5413b567
 SHA512 (06-55-04) = db2783cd62680510a7105e7c3fd9d5fffac6a33159ba811f4669f8afb9a5badde4c009bf1868e6a53eb3ac2286812404127bcd45fcbc65fe004788e25ae3e222