Update to upstream 2.1-40. 20230516

- Update to upstream 2.1-40. 20230516 - Addition of 06-6c-01/0x10 (ICL-D B0) microcode at revision 0x1000230; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode at revision 0x2b000461; - Addition of 06-8f-04/0x10 microcode at revision 0x2c0001d1; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-04) at revision 0x2b000461; - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-04) at revision 0x2c0001d1; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-04) at revision 0x2b000461; - Addition of 06-8f-06/0x10 (SPR-HBM B2) microcode (in intel-ucode/06-8f-04) at revision 0x2c0001d1; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-04) at revision 0x2b000461; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-04) at revision 0x2b000461; - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-04) at revision 0x2c0001d1; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-05) at revision 0x2b000461; - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) at revision 0x2c0001d1; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode at revision 0x2b000461; - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode at revision 0x2c0001d1; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-05) at revision 0x2b000461; - Addition of 06-8f-06/0x10 (SPR-HBM B2) microcode (in intel-ucode/06-8f-05) at revision 0x2c0001d1; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-05) at revision 0x2b000461; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-05) at revision 0x2b000461; - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-05) at revision 0x2c0001d1; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-06) at revision 0x2b000461; - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) at revision 0x2c0001d1; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-06) at revision 0x2b000461; - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-06) at revision 0x2c0001d1; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode at revision 0x2b000461; - Addition of 06-8f-06/0x10 (SPR-HBM B2) microcode at revision 0x2c0001d1; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-06) at revision 0x2b000461; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-06) at revision 0x2b000461; - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in intel-ucode/06-8f-06) at revision 0x2c0001d1; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-07) at revision 0x2b000461; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-07) at revision 0x2b000461; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-07) at revision 0x2b000461; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode at revision 0x2b000461; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in intel-ucode/06-8f-07) at revision 0x2b000461; - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in intel-ucode/06-8f-08) at revision 0x2b000461; - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) at revision 0x2c0001d1; - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in intel-ucode/06-8f-08) at revision 0x2b000461; - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in intel-ucode/06-8f-08) at revision 0x2c0001d1; - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in intel-ucode/06-8f-08) at revision 0x2b000461; - Addition of 06-8f-06/0x10 (SPR-HBM B2) microcode (in intel-ucode/06-8f-08) at revision 0x2c0001d1; - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in intel-ucode/06-8f-08) at revision 0x2b000461; - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode at revision 0x2b000461; - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode at revision 0x2c0001d1; - Addition of 06-b7-01/0x32 (RPL-S S0) microcode at revision 0x113; - Addition of 06-ba-02/0xc0 (RPL-H 6+8/P 6+8 J0) microcode at revision 0x4112; - Addition of 06-ba-03/0xc0 (RPL-U 2+8 Q0) microcode (in intel-ucode/06-ba-02) at revision 0x4112; - Addition of 06-ba-02/0xc0 (RPL-H 6+8/P 6+8 J0) microcode (in intel-ucode/06-ba-03) at revision 0x4112; - Addition of 06-ba-03/0xc0 (RPL-U 2+8 Q0) microcode at revision 0x4112; - Addition of 06-be-00/0x01 (ADL-N A0) microcode at revision 0x10; - Addition of 06-9a-04/0x40 (AZB A0/R0) microcode at revision 0x4; - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x100015e up to 0x1000171; - Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode from revision 0x2006e05 up to 0x2006f05; - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003302 up to 0x4003501; - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision 0x5003302 up to 0x5003501; - Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002501 up to 0x7002601; - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000375 up to 0xd000390; - Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x3c up to 0x3e; - Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x20 up to 0x22; - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xb2 up to 0xba; - Update of 06-8a-01/0x10 (LKF B2/B3) microcode from revision 0x31 up to 0x33; - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode from revision 0xa4 up to 0xaa; - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x28 up to 0x2a; - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x40 up to 0x44; - Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode from revision 0xf0 up to 0xf2; - Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode from revision 0xf0 up to 0xf2; - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xf0 up to 0xf2; - Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0) microcode from revision 0xf0 up to 0xf6; - Update of 06-96-01/0x01 (EHL B1) microcode from revision 0x16 up to 0x17; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision 0x421 up to 0x42a; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in intel-ucode/06-9a-03) from revision 0x421 up to 0x42a; - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in intel-ucode/06-9a-04) from revision 0x421 up to 0x42a; - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x421 up to 0x42a; - Update of 06-9c-00/0x01 (JSL A0/A1) microcode from revision 0x24000023 up to 0x24000024; - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision 0xf0 up to 0xf2; - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode from revision 0xf0 up to 0xf2; - Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode from revision 0xf0 up to 0xf2; - Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode from revision 0xf0 up to 0xf2; - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode from revision 0xf0 up to 0xf8; - Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf0 up to 0xf6; - Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf0 up to 0xf6; - Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf0 up to 0xf6; - Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf0 up to 0xf6; - Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision 0xf0 up to 0xf6; - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x54 up to 0x58; - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-97-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-97-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3); - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x22 up to 0x2c (old pf 0x3). - Addresses CVE-2022-21216, CVE-2022-33196, CVE-2022-33972, CVE-2022-38090 Signed-off-by: Eugene Syromiatnikov <esyr@redhat.com>
2023-05-25 19:42:24 +02:00 · 2023-05-25 19:42:24 +02:00 · 123508e80a
commit 123508e80a
parent e5c966e15b
3 changed files with 200 additions and 3 deletions
--- a/.gitignore
+++ b/.gitignore
@ -57,3 +57,4 @@ microcode-20100826.dat
 /microcode_ctl-2.1-35.tar.xz
 /microcode_ctl-2.1-36.tar.xz
 /microcode_ctl-2.1-37.tar.xz
+/microcode_ctl-2.1-40.tar.xz
--- a/microcode_ctl.spec
+++ b/microcode_ctl.spec
@ -1,10 +1,10 @@
-%define upstream_version 2.1-37
+%define upstream_version 2.1-40
 %global debug_package %{nil}

 Summary:        Tool to transform and deploy CPU microcode update for x86
 Name:           microcode_ctl
 Version:        2.1
-Release:        54%{?dist}
+Release:        55%{?dist}
 Epoch:          2
 License:        GPLv2+ and Redistributable, no modification permitted
 URL:            https://pagure.io/microcode_ctl
@ -35,6 +35,202 @@ make DESTDIR=%{buildroot} PREFIX=%{_prefix} INSDIR=/usr/sbin install clean


 %changelog
+* Thu May 25 2023 Eugene Syromiatnikov <esyr@redhat.com> 2:2.1-55
+- Update to upstream 2.1-40. 20230516
+  - Addition of 06-6c-01/0x10 (ICL-D B0) microcode at revision 0x1000230;
+  - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode at revision
+    0x2b000461;
+  - Addition of 06-8f-04/0x10 microcode at revision 0x2c0001d1;
+  - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2b000461;
+  - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2c0001d1;
+  - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2b000461;
+  - Addition of 06-8f-06/0x10 (SPR-HBM B2) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2c0001d1;
+  - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2b000461;
+  - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2b000461;
+  - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
+    intel-ucode/06-8f-04) at revision 0x2c0001d1;
+  - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-05) at revision 0x2b000461;
+  - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-05) at
+    revision 0x2c0001d1;
+  - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode at revision
+    0x2b000461;
+  - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode at revision
+    0x2c0001d1;
+  - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-05) at revision 0x2b000461;
+  - Addition of 06-8f-06/0x10 (SPR-HBM B2) microcode (in
+    intel-ucode/06-8f-05) at revision 0x2c0001d1;
+  - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-05) at revision 0x2b000461;
+  - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-05) at revision 0x2b000461;
+  - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
+    intel-ucode/06-8f-05) at revision 0x2c0001d1;
+  - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-06) at revision 0x2b000461;
+  - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-06) at
+    revision 0x2c0001d1;
+  - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-06) at revision 0x2b000461;
+  - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
+    intel-ucode/06-8f-06) at revision 0x2c0001d1;
+  - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode at revision
+    0x2b000461;
+  - Addition of 06-8f-06/0x10 (SPR-HBM B2) microcode at revision
+    0x2c0001d1;
+  - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-06) at revision 0x2b000461;
+  - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-06) at revision 0x2b000461;
+  - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode (in
+    intel-ucode/06-8f-06) at revision 0x2c0001d1;
+  - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-07) at revision 0x2b000461;
+  - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-07) at revision 0x2b000461;
+  - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-07) at revision 0x2b000461;
+  - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode at revision
+    0x2b000461;
+  - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-07) at revision 0x2b000461;
+  - Addition of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-08) at revision 0x2b000461;
+  - Addition of 06-8f-04/0x10 microcode (in intel-ucode/06-8f-08) at
+    revision 0x2c0001d1;
+  - Addition of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-08) at revision 0x2b000461;
+  - Addition of 06-8f-05/0x10 (SPR-HBM B1) microcode (in
+    intel-ucode/06-8f-08) at revision 0x2c0001d1;
+  - Addition of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-08) at revision 0x2b000461;
+  - Addition of 06-8f-06/0x10 (SPR-HBM B2) microcode (in
+    intel-ucode/06-8f-08) at revision 0x2c0001d1;
+  - Addition of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-08) at revision 0x2b000461;
+  - Addition of 06-8f-08/0x87 (SPR-SP E5/S3) microcode at revision
+    0x2b000461;
+  - Addition of 06-8f-08/0x10 (SPR-HBM B3) microcode at revision
+    0x2c0001d1;
+  - Addition of 06-b7-01/0x32 (RPL-S S0) microcode at revision 0x113;
+  - Addition of 06-ba-02/0xc0 (RPL-H 6+8/P 6+8 J0) microcode at revision
+    0x4112;
+  - Addition of 06-ba-03/0xc0 (RPL-U 2+8 Q0) microcode (in
+    intel-ucode/06-ba-02) at revision 0x4112;
+  - Addition of 06-ba-02/0xc0 (RPL-H 6+8/P 6+8 J0) microcode (in
+    intel-ucode/06-ba-03) at revision 0x4112;
+  - Addition of 06-ba-03/0xc0 (RPL-U 2+8 Q0) microcode at revision 0x4112;
+  - Addition of 06-be-00/0x01 (ADL-N A0) microcode at revision 0x10;
+  - Addition of 06-9a-04/0x40 (AZB A0/R0) microcode at revision 0x4;
+  - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x100015e
+    up to 0x1000171;
+  - Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode from
+    revision 0x2006e05 up to 0x2006f05;
+  - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003302
+    up to 0x4003501;
+  - Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision
+    0x5003302 up to 0x5003501;
+  - Update of 06-55-0b/0xbf (CPX-SP A1) microcode from revision 0x7002501
+    up to 0x7002601;
+  - Update of 06-6a-06/0x87 (ICX-SP D0) microcode from revision 0xd000375
+    up to 0xd000390;
+  - Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x3c up
+    to 0x3e;
+  - Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x20 up
+    to 0x22;
+  - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0xb2
+    up to 0xba;
+  - Update of 06-8a-01/0x10 (LKF B2/B3) microcode from revision 0x31 up
+    to 0x33;
+  - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode from revision
+    0xa4 up to 0xaa;
+  - Update of 06-8c-02/0xc2 (TGL-R C0) microcode from revision 0x28 up
+    to 0x2a;
+  - Update of 06-8d-01/0xc2 (TGL-H R0) microcode from revision 0x40 up
+    to 0x44;
+  - Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode from revision 0xf0
+    up to 0xf2;
+  - Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode from
+    revision 0xf0 up to 0xf2;
+  - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xf0 up
+    to 0xf2;
+  - Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0)
+    microcode from revision 0xf0 up to 0xf6;
+  - Update of 06-96-01/0x01 (EHL B1) microcode from revision 0x16 up
+    to 0x17;
+  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision
+    0x421 up to 0x42a;
+  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in
+    intel-ucode/06-9a-03) from revision 0x421 up to 0x42a;
+  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in
+    intel-ucode/06-9a-04) from revision 0x421 up to 0x42a;
+  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x421
+    up to 0x42a;
+  - Update of 06-9c-00/0x01 (JSL A0/A1) microcode from revision 0x24000023
+    up to 0x24000024;
+  - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from
+    revision 0xf0 up to 0xf2;
+  - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode from revision
+    0xf0 up to 0xf2;
+  - Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode from revision 0xf0
+    up to 0xf2;
+  - Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode from revision
+    0xf0 up to 0xf2;
+  - Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode from revision
+    0xf0 up to 0xf8;
+  - Update of 06-a5-02/0x20 (CML-H R1) microcode from revision 0xf0 up
+    to 0xf6;
+  - Update of 06-a5-03/0x22 (CML-S 6+2 G1) microcode from revision 0xf0
+    up to 0xf6;
+  - Update of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode from revision 0xf0
+    up to 0xf6;
+  - Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xf0
+    up to 0xf6;
+  - Update of 06-a6-01/0x80 (CML-U 6+2 v2 K1) microcode from revision
+    0xf0 up to 0xf6;
+  - Update of 06-a7-01/0x02 (RKL-S B0) microcode from revision 0x54 up
+    to 0x58;
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision
+    0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
+    intel-ucode/06-97-02) from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
+    from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
+    from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
+    intel-ucode/06-97-05) from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x22
+    up to 0x2c (old pf 0x3);
+  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
+    from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
+    from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
+    intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
+    intel-ucode/06-bf-02) from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x22 up to
+    0x2c (old pf 0x3);
+  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02)
+    from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
+    intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
+    intel-ucode/06-bf-05) from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05)
+    from revision 0x22 up to 0x2c (old pf 0x3);
+  - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x22 up to
+    0x2c (old pf 0x3).
+- Addresses CVE-2022-21216, CVE-2022-33196, CVE-2022-33972, CVE-2022-38090
+
 * Thu Jan 19 2023 Fedora Release Engineering <releng@fedoraproject.org> - 2:2.1-54
 - Rebuilt for https://fedoraproject.org/wiki/Fedora_38_Mass_Rebuild

--- a/2
+++ b/2
@ -1 +1 @@
-SHA512 (microcode_ctl-2.1-37.tar.xz) = 03e26c9b03bce7d52095374139f2b003e1c232a27dd998afa892ec4c98edef37a7c669c76e125df4f507450d9083035f65930fd5ba5dc5651110a787435460a8
+SHA512 (microcode_ctl-2.1-40.tar.xz) = cc072e269cdc6a8a6b2641f849d3ad2ffda630f53366016a91d498d3ae1804eefef2a79960494c41960c8de792a193cd299b4bf523f0035d5d57077aeba00cea