import microcode_ctl-20210216-1.el8
This commit is contained in:
CentOS Sources
Stepan Oksanichenko
parent
fea0b7d605
commit
0c422277ec
3
.gitignore
vendored
3
.gitignore
vendored
@ -2,6 +2,7 @@ SOURCES/06-2d-07
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SOURCES/06-4e-03
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SOURCES/06-55-04
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SOURCES/06-5e-03
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SOURCES/06-8c-01
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SOURCES/microcode-20190918.tar.gz
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SOURCES/microcode-20191115.tar.gz
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SOURCES/microcode-20200609.tar.gz
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SOURCES/microcode-20210216.tar.gz
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@ -2,6 +2,7 @@ bcf2173cd3dd499c37defbc2533703cfa6ec2430 SOURCES/06-2d-07
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06432a25053c823b0e2a6b8e84e2e2023ee3d43e SOURCES/06-4e-03
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2e405644a145de0f55517b6a9de118eec8ec1e5a SOURCES/06-55-04
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86c60ee7d5d0d7115a4962c1c61ceecb0fd3a95a SOURCES/06-5e-03
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2204a6dee1688980cd228268fdf4b6ed5904fe04 SOURCES/06-8c-01
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bc20d6789e6614b9d9f88ee321ab82bed220f26f SOURCES/microcode-20190918.tar.gz
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774636f4d440623b0ee6a2dad65260e81208074d SOURCES/microcode-20191115.tar.gz
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c2a433c1f68c2dc5b752bd7dddf204ea89ad5761 SOURCES/microcode-20200609.tar.gz
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26608161d98c3d0c965fc41856520434b14c000d SOURCES/microcode-20210216.tar.gz
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@ -8,10 +8,11 @@ for the OS-driven microcode update.
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[1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/31
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For the reference, SHA1 checksums of 06-55-04 microcode files containing
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For the reference, SHA1 checksums of 06-4e-03 microcode files containing
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microcode revisions in question are listed below:
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* 06-4e-03, revision 0xd6: 06432a25053c823b0e2a6b8e84e2e2023ee3d43e
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* 06-4e-03, revision 0xdc: cd1733458d187486999337ff8b51eeaa0cfbca6c
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* 06-4e-03, revision 0xe2: 41f4513cf563605bc85db38056ac430dec948366
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Please contact your system vendor for a BIOS/firmware update that contains
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the latest microcode version. For the information regarding microcode versions
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@ -35,6 +36,10 @@ to the following knowledge base articles:
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CVE-2020-0548 (Vector Register Data Sampling),
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CVE-2020-0549 (L1D Cache Eviction Sampling):
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https://access.redhat.com/solutions/5142751
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* CVE-2020-8695 (Information disclosure issue in Intel SGX via RAPL interface),
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CVE-2020-8696 (Vector Register Leakage-Active),
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CVE-2020-8698 (Fast Forward Store Predictor):
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https://access.redhat.com/articles/5569051
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The information regarding enforcing microcode update is provided below.
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@ -17,6 +17,8 @@ microcode revisions in question are listed below:
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* 06-55-04, revision 0x2000064: 2e405644a145de0f55517b6a9de118eec8ec1e5a
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* 06-55-04, revision 0x2000065: f27f12b9d53f492c297afd856cdbc596786fad23
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* 06-55-04, revision 0x2006906: 5f18f985f6d5ad369b5f6549b7f3ee55acaef967
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* 06-55-04, revision 0x2006a08: 4059fb1f60370297454177f63cd7cc20b3fa1212
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* 06-55-04, revision 0x2006a0a: 7ec27025329c82de9553c14a78733ad1013e5462
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Please contact your system vendor for a BIOS/firmware update that contains
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the latest microcode version. For the information regarding microcode versions
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@ -40,6 +42,10 @@ to the following knowledge base articles:
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CVE-2020-0548 (Vector Register Data Sampling),
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CVE-2020-0549 (L1D Cache Eviction Sampling):
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https://access.redhat.com/solutions/5142751
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* CVE-2020-8695 (Information disclosure issue in Intel SGX via RAPL interface),
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CVE-2020-8696 (Vector Register Leakage-Active),
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CVE-2020-8698 (Fast Forward Store Predictor):
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https://access.redhat.com/articles/5569051
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The information regarding disabling microcode update is provided below.
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@ -8,10 +8,11 @@ by default on these systems, and the previously published microcode revision
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[1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/31#issuecomment-644885826
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For the reference, SHA1 checksums of 06-55-04 microcode files containing
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For the reference, SHA1 checksums of 06-5e-03 microcode files containing
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microcode revisions in question are listed below:
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* 06-5e-03, revision 0xd6: 86c60ee7d5d0d7115a4962c1c61ceecb0fd3a95a
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* 06-5e-03, revision 0xdc: 5e1020a10678cfc60980131c3d3a2cfd462b4dd7
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* 06-5e-03, revision 0xe2: 031e6e148b590d1c9cfdb6677539eeb4899e831c
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Please contact your system vendor for a BIOS/firmware update that contains
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the latest microcode version. For the information regarding microcode versions
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@ -35,6 +36,10 @@ to the following knowledge base articles:
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CVE-2020-0548 (Vector Register Data Sampling),
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CVE-2020-0549 (L1D Cache Eviction Sampling):
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https://access.redhat.com/solutions/5142751
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* CVE-2020-8695 (Information disclosure issue in Intel SGX via RAPL interface),
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CVE-2020-8696 (Vector Register Leakage-Active),
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CVE-2020-8698 (Fast Forward Store Predictor):
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https://access.redhat.com/articles/5569051
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The information regarding enforcing microcode update is provided below.
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3
SOURCES/06-8c-01_config
Normal file
3
SOURCES/06-8c-01_config
Normal file
@ -0,0 +1,3 @@
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model GenuineIntel 06-8c-01
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path intel-ucode/06-8c-01
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disable early late
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4
SOURCES/06-8c-01_disclaimer
Normal file
4
SOURCES/06-8c-01_disclaimer
Normal file
@ -0,0 +1,4 @@
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Microcode updates for Intel Tiger Lake-UP3/UP4 (family 6, model 140, stepping 1;
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CPUID 0x806c1) are disabled as they may cause system instability.
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Please refer to /usr/share/doc/microcode_ctl/caveats/06-8c-01_readme
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and /usr/share/doc/microcode_ctl/README.caveats for details.
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40
SOURCES/06-8c-01_readme
Normal file
40
SOURCES/06-8c-01_readme
Normal file
@ -0,0 +1,40 @@
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Some Intel Tiger Lake-UP3/UP4 CPU models (TGL, family 6, model 140, stepping 1)
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have reports of system hangs when a microcode update, that is included
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since microcode-20201110 update, is applied[1]. In order to address this,
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microcode update has been disabled by default on these systems.
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[1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/44
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Please contact your system vendor for a BIOS/firmware update that contains
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the latest microcode version.
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The information regarding enforcing microcode update is provided below.
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To enforce usage of the latest 06-8c-01 microcode revision for a specific kernel
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version, please create a file "force-intel-06-8c-01" inside
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/lib/firmware/<kernel_version> directory, run
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"/usr/libexec/microcode_ctl/update_ucode" to add it to firmware directory
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where microcode will be available for late microcode update, and run
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"dracut -f --kver <kernel_version>", so initramfs for this kernel version
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is regenerated and the microcode can be loaded early, for example:
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touch /lib/firmware/3.10.0-862.9.1/force-intel-06-8c-01
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/usr/libexec/microcode_ctl/update_ucode
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dracut -f --kver 3.10.0-862.9.1
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After that, it is possible to perform a late microcode update by executing
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"/usr/libexec/microcode_ctl/reload_microcode" or by writing value "1" to
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"/sys/devices/system/cpu/microcode/reload" directly.
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To enforce addition of this microcode for all kernels, please create file
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"/etc/microcode_ctl/ucode_with_caveats/force-intel-06-8c-01", run
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"/usr/libexec/microcode_ctl/update_ucode" for enabling late microcode updates,
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and "dracut -f --regenerate-all" for enabling early microcode updates:
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mkdir -p /etc/microcode_ctl/ucode_with_caveats
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touch /etc/microcode_ctl/ucode_with_caveats/force-intel-06-8c-01
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/usr/libexec/microcode_ctl/update_ucode
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dracut -f --regenerate-all
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Please refer to /usr/share/doc/microcode_ctl/README.caveats for additional
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information.
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@ -72,6 +72,16 @@ in question:
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* 06-9e-0c, revision 0xd6: 4b9059e519bcab6085b6c103f5d99e509fe0b2bb
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* 06-9e-0d, revision 0xd6: 3a3b7edfd8126bb34b761b46a32102a622047899
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* 06-8e-09, revision 0xde: 84d7514101eb8904834a3dacdee684b3c574245f
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* 06-8e-0a, revision 0xe0: 080b9e3ebbcf6bb1eca0fb5f640e6bfbfe3a1e6e
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* 06-8e-0b, revision 0xde: 80fed976231bbff4c7103e373498e07eef0bff31
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* 06-8e-0c, revision 0xde: 84f160587fea4acb81451c8ff53dc51afba06343
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* 06-9e-09, revision 0xde: 422026ffb2cca446693c586be98d0d9e7dfeb116
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* 06-9e-0a, revision 0xde: b6c44b9fe26e1d6bafa27f37ffe010284294bf1c
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* 06-9e-0b, revision 0xde: 6452937a0d359066b95f9e679a41a15490770312
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* 06-9e-0c, revision 0xde: a95021a4e497e0bf3691ecf3d020728f25a3f542
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* 06-9e-0d, revision 0xde: 03b20fdc2fa3f9586f93a7e40d3b61be5b7b788c
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Please contact your system vendor for a BIOS/firmware update that contains
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the latest microcode version. For the information regarding microcode versions
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required for mitigating specific side-channel cache attacks, please refer
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@ -94,6 +104,10 @@ to the following knowledge base articles:
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CVE-2020-0548 (Vector Register Data Sampling),
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CVE-2020-0549 (L1D Cache Eviction Sampling):
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https://access.redhat.com/solutions/5142751
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* CVE-2020-8695 (Information disclosure issue in Intel SGX via RAPL interface),
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CVE-2020-8696 (Vector Register Leakage-Active),
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CVE-2020-8698 (Fast Forward Store Predictor):
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https://access.redhat.com/articles/5569051
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The information regarding disabling microcode update is provided below.
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@ -72,6 +72,16 @@ in question:
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* 06-9e-0c, revision 0xd6: 4b9059e519bcab6085b6c103f5d99e509fe0b2bb
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* 06-9e-0d, revision 0xd6: 3a3b7edfd8126bb34b761b46a32102a622047899
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* 06-8e-09, revision 0xde: 84d7514101eb8904834a3dacdee684b3c574245f
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* 06-8e-0a, revision 0xe0: 080b9e3ebbcf6bb1eca0fb5f640e6bfbfe3a1e6e
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* 06-8e-0b, revision 0xde: 80fed976231bbff4c7103e373498e07eef0bff31
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* 06-8e-0c, revision 0xde: 84f160587fea4acb81451c8ff53dc51afba06343
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* 06-9e-09, revision 0xde: 422026ffb2cca446693c586be98d0d9e7dfeb116
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* 06-9e-0a, revision 0xde: b6c44b9fe26e1d6bafa27f37ffe010284294bf1c
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* 06-9e-0b, revision 0xde: 6452937a0d359066b95f9e679a41a15490770312
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* 06-9e-0c, revision 0xde: a95021a4e497e0bf3691ecf3d020728f25a3f542
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* 06-9e-0d, revision 0xde: 03b20fdc2fa3f9586f93a7e40d3b61be5b7b788c
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Please contact your system vendor for a BIOS/firmware update that contains
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the latest microcode version. For the information regarding microcode versions
|
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required for mitigating specific side-channel cache attacks, please refer
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@ -94,6 +104,10 @@ to the following knowledge base articles:
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CVE-2020-0548 (Vector Register Data Sampling),
|
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CVE-2020-0549 (L1D Cache Eviction Sampling):
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https://access.redhat.com/solutions/5142751
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* CVE-2020-8695 (Information disclosure issue in Intel SGX via RAPL interface),
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CVE-2020-8696 (Vector Register Leakage-Active),
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CVE-2020-8698 (Fast Forward Store Predictor):
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https://access.redhat.com/articles/5569051
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The information regarding disabling microcode update is provided below.
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27
SOURCES/README
Normal file
27
SOURCES/README
Normal file
@ -0,0 +1,27 @@
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The microcode_ctl package contains microcode files (vendor-provided binary data
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and/or code in proprietary format that affects behaviour of a device) for Intel
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CPUs that may be loaded into the CPU during boot.
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This directory contains information regarding various aspects of the provided
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microcode files and their usage.
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* LICENSE.intel-ucode
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"license" file from the Intel x86 CPU microcode archive.
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* README
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This file.
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* README.caveats
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Caveats (mechanism for enabling/disabling usage of sets of microcode files
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based on caveat configuration and user preferences) documentation.
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Also contains general information about microcode update behaviour and links
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with additional information about the relevant microarchitectural
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vulnerabilities.
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* README.intel-ucode
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"README.md" file from the Intel x86 CPU microcode archive.
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* RELEASE_NOTES.intel-ucode
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"releasenote.md" file from the Intel x86 CPU microcode archive.
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* SECURITY.intel-ucode
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"security.md" file from the Intel x86 CPU microcode archive.
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* SUMMARY.intel-ucode
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Information about supplied microcode files extracted from their headers.
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* caveats
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Directory that contains readme files for specific caveats.
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@ -630,6 +630,26 @@ Mitigation: previously published microcode revision 0xac/0xb4/0xb8 is used
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as a convenience for the cases where it was working well before.
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Intel Tiger Lake-UP3/UP4 caveat
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-------------------------------
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Some systems with Intel Tiger Lake-UP3/UP4 CPUs (TGL, family 6, model 140,
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stepping 1) have reports of system hangs when a microcode update,
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that is included since microcode-20201110 release, is applied[1].
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In order to address this, microcode update to a newer revision has been disabled
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by default on these systems; the newer microcode file, however, is still shipped
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as a part of microcode_ctl package and can be used for performing a microcode
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update if it is enforced via the aforementioned overrides. (See the sections
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"check_caveats script" and "reload_microcode script" for details.)
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[1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/44
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Caveat names: intel-06-8c-01
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Affected microcode: intel-ucode/06-8c-01.
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Mitigation: microcode loading is disabled for the affected CPU model.
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Additional information
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======================
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@ -658,3 +678,7 @@ Intel CPU vulnerabilities is available in the following knowledge base articles:
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CVE-2020-0548 (Vector Register Data Sampling),
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CVE-2020-0549 (L1D Cache Eviction Sampling):
|
||||
https://access.redhat.com/solutions/5142751
|
||||
* CVE-2020-8695 (Information disclosure issue in Intel SGX via RAPL interface),
|
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CVE-2020-8696 (Vector Register Leakage-Active),
|
||||
CVE-2020-8698 (Fast Forward Store Predictor):
|
||||
https://access.redhat.com/articles/5569051
|
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@ -628,10 +628,9 @@ for cfg in $(echo "${configs}"); do
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cfg_mc_present=0
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for p in $(printf "%s" "$cfg_path"); do
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{ /usr/bin/find "$MC_CAVEATS_DATA_DIR/$cfg" \
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-path "$MC_CAVEATS_DATA_DIR/$cfg/$p" -print0;
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/bin/true; } \
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| /bin/grep -zFxq "$cpu_mc_path" \
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/usr/bin/find "$MC_CAVEATS_DATA_DIR/$cfg" \
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-path "$MC_CAVEATS_DATA_DIR/$cfg/$p" -print0 \
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| /bin/grep -zFxc "$cpu_mc_path" > /dev/null \
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|| continue
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cfg_mc_present=1
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313
SOURCES/codenames.list
Normal file
313
SOURCES/codenames.list
Normal file
@ -0,0 +1,313 @@
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# format=extended
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# SPDX-License-Identifier: CC0-1.0
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# Segment; Unused; Codename; Stepping; PF; CPUID; Abbreviation; Variant(s); Families; Models
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||||
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Server;;Pentium Pro;B0;00;611;;;Pentium Pro;
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Server;;Pentium Pro;C0;00;612;;;Pentium Pro;
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Server;;Pentium Pro;sA0;00;616;;;Pentium Pro;
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Server;;Pentium Pro;sA1;00;617;;;Pentium Pro;
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Server;;Pentium Pro;sB1;00;619;;;Pentium Pro;
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Desktop;;Klamath (PII);C0;ff;633;;;Pentium II;
|
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Desktop;;Klamath (PII);C1;ff;634;;;Pentium II;
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Desktop;;Deschutes SEPP (PII);A0;01;650;;;Celeron;
|
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Mobile;;Deschutes Mini-Cart (PII);A0;02;650;;;Pentium II Mobile;
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Server;;Deschutes SECC (PII);A0;04;650;;;Pentium II Xeon;
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Mobile;;Deschutes MMC1/MMC2 (PII);A0;08;650;;;Pentium II Mobile;
|
||||
Mobile;;Deschutes Micro-PGA1 (PII);A0;20;650;;;Pentium II Mobile;
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||||
Mobile;;Deschutes (PII);A0;80;650;;;Pentium II Mobile;
|
||||
Desktop;;Deschutes SECC/SECC2 (PII);A1;01;651;;;Celeron;
|
||||
Desktop;;Deschutes SEPP (PII);A1;01;651;;;Celeron;
|
||||
Mobile;;Deschutes Mini-Cart (PII);A1;02;651;;;Pentium II Mobile;
|
||||
Mobile;;Deschutes MMC1/MMC2 (PII);A1;08;651;;;Pentium II Mobile;
|
||||
Desktop;;Deschutes SECC/SECC2 (PII);B0;01;652;;;Pentium II;
|
||||
Mobile;;Deschutes Mini-Cart (PII);B0;02;652;;;Pentium II Mobile;
|
||||
Server;;Deschutes SECC (PII);B0;04;652;;;Pentium II Xeon;
|
||||
Mobile;;Deschutes MMC1/MMC2 (PII);B0;08;652;;;Pentium II Mobile;
|
||||
Desktop;;Deschutes SECC/SECC2 (PII);B1;01;653;;;Pentium II;
|
||||
Mobile;;Deschutes Mini-Cart (PII);B1;02;653;;;Pentium II Mobile;
|
||||
Server;;Deschutes SECC (PII);B1;04;653;;;Pentium II Xeon;
|
||||
Mobile;;Deschutes MMC1/MMC2 (PII);B1;08;653;;;Pentium II Mobile;
|
||||
Desktop;;Mendocino SEPP (PII);A0;01;660;;;Celeron;
|
||||
Desktop;;Mendocino PPGA (PII);B0;10;665;;;Celeron;
|
||||
Mobile;;Dixon Mini-Cart (PII);A1;02;66a;;;Pentium II Mobile;
|
||||
Mobile;;Dixon MMC1/MMC2 (PII);A1;08;66a;;;Pentium II Mobile, Celeron Mobile;
|
||||
Mobile;;Dixon Micro-PGA1 (PII);A1;20;66a;;;Pentium II Mobile, Celeron Mobile;
|
||||
Mobile;;Dixon Mini-Cart (PII);A1;02;66d;;;Pentium II Mobile;
|
||||
Mobile;;Dixon MMC1/MMC2 (PII);A1;08;66d;;;Pentium II Mobile;
|
||||
Mobile;;Dixon Micro-PGA1 (PII);A1;20;66d;;;Pentium II Mobile;
|
||||
Desktop;;Katmai SECC/SECC2 (PIII);B0;01;671;;;Pentium III;
|
||||
Server;;Tanner SECC (PIII);B0;04;671;;;Pentium III Xeon;
|
||||
Desktop;;Katmai SECC/SECC2 (PIII);B0;01;672;;;Pentium III;
|
||||
Server;;Tanner SECC (PIII);B0;04;672;;;Pentium III Xeon;
|
||||
Desktop;;Katmai SECC/SECC2 (PIII);C0;01;673;;;Pentium III;
|
||||
Server;;Tanner SECC (PIII);C0;04;673;;;Pentium III Xeon;
|
||||
Desktop;;Coppermine SECC/SECC2 (PIII);A2;01;681;;;Pentium III;
|
||||
Server;;Cascades SECC (PIII);A2;04;681;;;Pentium III Xeon;
|
||||
Mobile;;Coppermine MMC2 (PIII);A2;08;681;;;Pentium III Mobile;
|
||||
Desktop;;Coppermine FC-PGA (PIII);A2;10;681;;;Pentium III;
|
||||
Mobile;;Coppermine Micro-PGA2 (PIII);A2;20;681;;;Pentium III Mobile;
|
||||
Desktop;;Coppermine SECC/SECC2 (PIII);B0;01;683;;;Pentium III;
|
||||
Server;;Cascades SECC (PIII);B0;04;683;;;Pentium III Xeon;
|
||||
Mobile;;Coppermine MMC2 (PIII);B0;08;683;;;Pentium III Mobile;
|
||||
Desktop;;Coppermine FC-PGA (PIII);B0;10;683;;;Pentium III;
|
||||
Mobile;;Coppermine Micro-PGA2 (PIII);B0;20;683;;;Pentium III Mobile;
|
||||
Desktop;;Coppermine SECC/SECC2 (PIII);C0;01;686;;;Pentium III;
|
||||
Mobile;;Coppermine (PIII);C0;02;686;;;Pentium III Mobile;
|
||||
Server;;Cascades SECC (PIII);C0;04;686;;;Pentium III Xeon;
|
||||
Mobile;;Coppermine MMC2 (PIII);C0;08;686;;;Pentium III Mobile;
|
||||
Desktop;;Coppermine FC-PGA (PIII);C0;10;686;;;Pentium III;
|
||||
Mobile;;Coppermine Micro-PGA2 (PIII);C0;20;686;;;Pentium III Mobile;
|
||||
Desktop;;Coppermine FC-PGA2 (PIII);C0;20;686;;;Pentium III;
|
||||
Desktop;;Coppermine (PIII);C0;80;686;;;Pentium III;
|
||||
Desktop;;Coppermine (PIII);D0;ff;68a;;;Pentium III;
|
||||
Mobile;;Banias (P-M);B1;b0;695;;;Pentium M, Celeron M;
|
||||
Server;;Cascades (PIII);A0;04;6a0;;;Pentium III Xeon;
|
||||
Server;;Cascades (PIII);A1;04;6a1;;;Pentium III Xeon;
|
||||
Server;;Cascades (PIII);B0;04;6a4;;;Pentium III Xeon;
|
||||
Desktop;;Tualatin FC-PGA2 (PIII);A0;10;6b0;;;Pentium III;
|
||||
Desktop;;Tualatin FC-PGA2 (PIII);A1;10;6b1;;;Pentium III;
|
||||
Mobile;;Tualatin Micro-PGA2 (PIII);A1;20;6b1;;;Pentium III Mobile;
|
||||
Desktop;;Tualatin FC-PGA2 (PIII);B1;10;6b4;;;Pentium III;
|
||||
Mobile;;Tualatin Micro-PGA2 (PIII);B1;20;6b4;;;Pentium III Mobile;
|
||||
Mobile;;Dothan (P-M);B0;20;6d6;;;Pentium M;
|
||||
Mobile;;Dothan (P-M);C0;20;6d8;;;Pentium M;
|
||||
Mobile;;Yonah;B0;20;6e4;;;Core Duo, Core Solo;
|
||||
Mobile;;Yonah;C0;20;6e8;;;Core Duo, Core Solo;
|
||||
Server;;Sossaman (Yonah);C0;00;6e8;;;Xeon LV;
|
||||
Mobile;;Yonah;E0;a0;6ec;;;Core Duo, Core Solo;
|
||||
Server;;Sossaman (Yonah);D0;00;6ec;;;Xeon LV, Xeon ULV;
|
||||
Mobile;;Yonah;M0;20;6ed;;;Core Duo Mobile;
|
||||
Desktop;;Conroe (Merom);L2;01;6f2;;;Core2 Duo E4xxx, E6xxx;
|
||||
Mobile;;Merom;L2;20;6f2;;;Core2 Duo Mobile;
|
||||
Server;;Conroe Xeon (Merom);L2;01;6f2;;;;Xeon 3040, 3050
|
||||
Desktop;;Conroe (Merom);B0;01;6f4;;;Core2 Duo E4xxx, E6xxx;
|
||||
Server;;Woodcrest (Merom);B0;04;6f4;;;Xeon 51xx;
|
||||
Desktop;;Conroe (Merom);B2;01;6f6;;;Core2 Duo E4xxx, E6xxx;
|
||||
Mobile;;Merom;B2;20;6f6;;;Core2 Duo Mobile;
|
||||
Server;;Conroe Xeon (Merom);B2;01;6f6;;;;Xeon 3040, 3050, 3060, 3070
|
||||
Server;;Woodcrest (Merom);B2;04;6f6;;;;Xeon 5110, 5120, 5130, 5140, 5150, 5160, Xeon LV 5128, 5133, 5138, 5148
|
||||
Desktop;;Kentsfield (Merom);B3;10;6f7;;;;
|
||||
Server;;Kentsfield Xeon (Merom);B3;10;6f7;;;;Xeon X3210, X3220
|
||||
Server;;Clovertown (Merom);B3;40;6f7;;;;Xeon E5310, E5320, E5335, E5345, X5355, X5365, L5310, L5320
|
||||
Desktop;;Tigerton (Merom);E0;01;6f9;;;;
|
||||
Mobile;;Merom;E1;80;6fa;;;Core 2 Duo Mobile, Celeron Processor 500;
|
||||
Desktop;;Conroe (Merom);G0;01;6fb;;;;
|
||||
Desktop;;Kentsfield (Merom);G0;10;6fb;;;;
|
||||
Mobile;;Merom;G0;a0;6fb;;;;
|
||||
Server;;Conroe Xeon (Merom);G0;01;6fb;;;;Xeon 3065, 3075, 3085
|
||||
Server;;Woodcrest (Merom);G0;04;6fb;;;;Xeon 5110, 5120, 5130, 5140, 5150, 5160, Xeon LV 5113, 5128, 5133, 5138, 5148
|
||||
Server;;Tigerton (Merom);G0;08;6fb;;;;Xeon E7210, E7220, E7310, E7320, E7330, E7340, X7350, L7345
|
||||
Server;;Kentsfield Xeon (Merom);G0;10;6fb;;;;Xeon X3210, X3220, X3230
|
||||
Server;;Clovertown (Merom);G0;40;6fb;;;;Xeon E5310, E5320, E5335, E5345, X5355, X5365, L5310, L5318, L5320, L5335
|
||||
Desktop;;Conroe (Merom);M0;01;6fd;;;;
|
||||
Mobile;;Merom;M0;a0;6fd;;;;
|
||||
Desktop;;Willamette (NetBurst);B2;01;f07;;;Pentium 4 (Socket 423);
|
||||
Server;;Foster DP (NetBurst);B2;02;f07;;;Pentium 4 Xeon (Socket 603);
|
||||
Desktop;;Willamette (NetBurst);B2;04;f07;;;Pentium 4 (Willamette, Socket 478);
|
||||
Desktop;;Willamette (NetBurst);C1;01;f0a;;;Pentium 4 (Socket 423);
|
||||
Server;;Foster DP (NetBurst);C1;02;f0a;;;Pentium 4 Xeon (Socket 603);
|
||||
Desktop;;Willamette (NetBurst);C1;04;f0a;;;Pentium 4 (Willamette, Socket 478);
|
||||
Server;;Foster MP (NetBurst);C0;02;f11;;;Pentium 4 Xeon MP (Socket 603);
|
||||
Desktop;;Willamette (NetBurst);D0;01;f12;;;Pentium 4 (Socket 423);
|
||||
Server;;Foster DP (NetBurst);D0;02;f12;;;Pentium 4 Xeon (Socket 603);
|
||||
Desktop;;Willamette (NetBurst);D0;04;f12;;;Pentium 4 (Willamette, Socket 478);
|
||||
Desktop;;Willamette (NetBurst);E0;04;f13;;;Pentium 4 (Willamette, Socket 478), Celeron (Willamette, Socket 478);
|
||||
Server;;Prestonia (NetBurst);A0;02;f22;;;Pentium 4 Xeon MP (Socket 603);
|
||||
Desktop;;Northwood (NetBurst);B0;04;f24;;;Pentium 4 (Northwood);
|
||||
Mobile;;Northwood (NetBurst);B0;08;f24;;;Pentium 4-M;
|
||||
Mobile;;Northwood (NetBurst);B0;10;f24;;;Pentium 4 Mobile;
|
||||
Server;;Prestonia (NetBurst);B0;02;f24;;;Pentium 4 Xeon (Socket 603/604);
|
||||
Desktop;;Northwood (NetBurst);B1,M0;14;f25;;;Pentium 4 (Northwood);
|
||||
Server;;Prestonia (NetBurst);B1,M0;01;f25;;;Pentium 4 Xeon (Socket 603/604);
|
||||
Server;;Gallatin (NetBurst);B1;02;f25;;;Pentium 4 Xeon (Socket 603/604);
|
||||
Server;;Gallatin (NetBurst);B1;02;f26;;;Pentium 4 Xeon (Socket 603/604);
|
||||
Desktop;;Northwood (NetBurst);C1;04;f27;;;Pentium 4 (Northwood), Celeron (Northwood);
|
||||
Mobile;;Northwood (NetBurst);C1;08;f27;;;Pentium 4-M, Celeron Mobile;
|
||||
Server;;Prestonia (NetBurst);C1;02;f27;;;Pentium 4 Xeon (Socket 603/604);
|
||||
Desktop;;Northwood (NetBurst);D1;04;f29;;;Pentium 4 (Northwood), Celeron (Northwood);
|
||||
Mobile;;Northwood (NetBurst);D1;08;f29;;;Pentium 4-M, Celeron Mobile;
|
||||
Server;;Prestonia (NetBurst);D1;02;f29;;;Pentium 4 Xeon (Socket 603/604);
|
||||
Desktop;;Prescott (NetBurst);B1;0d;f32;;;Pentium 4 (Prescott);
|
||||
Desktop;;Prescott (NetBurst);C0;0d;f33;;;Pentium 4 (Prescott), Celeron D;
|
||||
Desktop;;Prescott (NetBurst);D0;1d;f34;;;Pentium 4 (Prescott), Celeron D;
|
||||
Server;;Nocona (NetBurst);D0;1d;f34;;;Pentium 4 (Prescott);
|
||||
Desktop;;Prescott (NetBurst);E0;bd;f41;;;Pentium 4 (Prescott), Celeron D;
|
||||
Server;;Protomac (NetBurst);C0;02;f41;;;Pentium 4 Xeon MP (Socket 604);
|
||||
Server;;Cranford (NetBurst);A0;bd;f41;;;Pentium 4 Xeon MP (Socket 604);
|
||||
Server;;Nocona (NetBurst);E0;bd;f41;;;Pentium 4 Xeon (Socket 604);
|
||||
Desktop;;Prescott (NetBurst);N0;9d;f43;;;Pentium 4 (Prescott);
|
||||
Server;;Irwindale (NetBurst);N0;9d;f43;;;Pentium 4 Xeon (Socket 604);
|
||||
Desktop;;Smithfield (NetBurst);A0;9d;f44;;;Pentium D 8x0 (Smithfield);
|
||||
Desktop;;Smithfield (NetBurst);B0;9d;f47;;;Pentium D 8x0 (Smithfield);
|
||||
Server;;Paxwille (NetBurst);A0;01;f48;;;Pentium 4 Dual-Core Xeon 70xx;
|
||||
Server;;Paxwille (NetBurst);A0;02;f48;;;Pentium 4 Dual-Core Xeon MP 70xx;
|
||||
Desktop;;Prescott (NetBurst);G1;bd;f49;;;Pentium 4 (Prescott), Celeron D;
|
||||
Server;;Cranford (NetBurst);B0;bd;f49;;;Pentium 4 Xeon MP (Socket 604);
|
||||
Server;;Nocona (NetBurst);G1;bd;f49;;;Pentium 4 Xeon (Socket 604);
|
||||
Desktop;;Prescott (NetBurst);R0;5c;f4a;;;Pentium 4 (Prescott);
|
||||
Server;;Irwindale (NetBurst);R0;5d;f4a;;;Pentium 4 Xeon (Socket 604);
|
||||
Desktop;;Cedar Mill (NetBurst);B1;04;f62;;;;Pentium 4 HT 631, 641, 651, 661
|
||||
Desktop;;Presler (NetBurst);B1;04;f62;;;;Pentium D 920, 930, 940, 950, Pentium Extreme Edition 955
|
||||
Desktop;;Cedar Mill (NetBurst);C1;34;f64;;;;Pentium 4 HT 631, 641, 651, 661, Celeron D 347, 352, 356
|
||||
Desktop;;Presler (NetBurst);C1;34;f64;;;;Pentium D 915, 920, 925, 930, 940, 945, 950, 960, Pentium Extreme Edition 965
|
||||
Server;;Dempsey (NetBurst);C1;01;f64;;;Xeon 50xx;
|
||||
Desktop;;Cedar Mill (NetBurst);D0;04;f65;;;;Pentium 4 HT 631, 641, 651, 661, Celeron D 347, 352, 356, 360, 365
|
||||
Desktop;;Presler (NetBurst);D0;04;f65;;;;Pentium D 915, 925, 935, 945, 950, 960
|
||||
Server;;Dempsey (NetBurst);D0;01;f65;;;Xeon 50xx;
|
||||
Server;;Tulsa (NetBurst);B0;22;f68;;;;Xeon 7110N, 7110M, 7120N, 7120M, 7130N, 7130M, 7140N, 7140M, 7150N
|
||||
Server;;Deschutes (PII);B0;00;01632;;;Pentium II Xeon;
|
||||
SOC;;Tolapai (P-M);B0;ff;10650;;;;EP80579
|
||||
Desktop;;Conroe-L (Merom);A1;01;10661;;;;Celeron 220, 420, 430, 440, 450
|
||||
Mobile;;Merom-L;A1;82;10661;;;;
|
||||
Desktop;;Wolfdale (Penryn);M0;91;10676;;;;Core2 Duo E7200, E7300, E8190, E8200, E8300, E8400, E8500, Core2 Quad Q9450, Q9550, Core2 Extreme QX9650, QX9770, QX9775
|
||||
Desktop;;Yorkfield (Penryn);C0;91;10676;;;;Core2 Quad Q9450, Q9550, Core2 Extreme QX9650, QX9770, QX9775
|
||||
Mobile;;Penryn;C0;91;10676;;;;Core2 Duo E8135, E8235, E8335, E8435, T8100, T8300, T9300, T9400, T9500, T9600, P7350, P7450, P8400, P8600, P9500, SP9300, SP9400, SL9300, SL9380, SL9400, SU9300, SU9400, Core2 Extreme X9000, X9100
|
||||
Server;;Wolfdale Xeon (Penryn);C0;91;10676;;;;Xeon E3110
|
||||
Server;;Yorkfield Xeon (Penryn);C0;91;10676;;;;Xeon X3350, X3360
|
||||
Server;;Wolfdale-DP (Penryn);M0;04;10676;;;;Xeon E5205, E5220, E5240, X5260, X5272
|
||||
Server;;Harpertown (Penryn);C0;40;10676;;;;Xeon L5408, L5410, L5420, E5405,E5410,E5420,E5430, E5440, E5450, E5462, E5472, X5450, X5460, X5470, X5472, X5482
|
||||
Desktop;;Yorkfield (Penryn);C1,M1;10;10677;;;Core2 Extreme, Core2 Quad;Core2 Extreme QX9650, QX9770, QX9775, Core2 Quad Q8200, Q8200S, Q8400, Q8400S, Q9300, Q9400, Q9400S, Q9450, Q9500, Q9505, Q9505S, Q9550, Q9550S, Q9650
|
||||
Server;;Yorkfield Xeon (Penryn);C1,M1;10;10677;;;Xeon L33xx, X33xx;Xeon L3360, X3320, X3330, X3350, X3360, X3370, X3380
|
||||
Desktop;;Wolfdale (Penryn);E0,R0;b1;1067a;;;Core2 Extreme, Core2 Quad, Core2 Duo;Core2 Extreme QX9650, QX9770, QX9775, Core2 Quad Q8200, Q8200S, Q8300, Q8400, Q8400S, Q9300, Q9400, Q9400S, Q9450, Q9500, Q9505, Q9505S, Q9550, Q9550S, Q9650, Core2 Duo E7200, E7300, E7400, E7500, E7600, E8190, E8200, E8300, E8400, E8500, E8600, Pentium E5200, E5300, E5400, E5500, E5700, E5800, E6300, E6500, E6500K, E6600, E6700, E6800, Celeron E3200, E3300, E3400, E3500
|
||||
Mobile;;Wolfdale (Penryn);E0,R0;b1;1067a;;;Core2 Extreme, Core2 Quad, Core2 Duo, Core2 Solo, Pentium T4x00;Core2 Extreme QX9300, X9000, X9100, Core2 Quad Q9000, Q9100, Core2 Duo T6400, T6500, T6670, T8100, T8300, T9300, T9400, T9500, T9550, T9600, T9800, T9900, SU9300, SU9400, SU9600, SP9300, SP9400, SP9600, SL9380, SL9400, SL9600, SL9300, P7350, P7370, P7450, P7550, P7570, P8400, P8600, P8700, P8800, P9500, P9600, P9700, Core2 Solo SU3500, ULV SU3500, ULV SU3300, Pentium T4200, T4300, T4400, T4500, Celeron 900, 925, SU2300, T3100, T3300, T3500, ULV 763, Celeron M Processor ULV 722, ULV 723, ULV 743
|
||||
Server;;Harpertown (Penryn);E0;44;1067a;;;;Xeon L5408, L5410, L5420, L5430, E5405, E5410, E5420, E5430, E5440, E5450, E5462, E5472, X5450, X5460, X5470, X5492
|
||||
Server;;Wolfdale-DP (Penryn);E0;44;1067a;;;;Xeon E3110, E3120, E5205, E5220, L3110, L5215, L5240, X5260, X5270, X5272
|
||||
Dekstop;;Bloomfield (Nehalem);C0;03;106a4;NHM;;Core i7-9xx;
|
||||
Dekstop;;Bloomfield (Nehalem);D0;03;106a5;NHM;;Core i7-9xx;
|
||||
Server;;Bloomfield Xeon (Nehalem);D0;03;106a5;NHM;EP,WS;Xeon E/L/X/W55xx;
|
||||
Mobile;;Silverthorne (Bonnell);C0;01;106c2;;;Intel Atom Z5x0;
|
||||
Desktop;;Diamondville (Bonnell);C0;04;106c2;;;;Intel Atom 230
|
||||
Desktop;;Diamondville (Bonnell);C0;08;106c2;;;;Intel Atom 330
|
||||
Mobile;;Diamondville (Bonnell);C0;04;106c2;;;;Intel Atom N270, N280
|
||||
Desktop;;Pineview (Bonnell);A0;05;106ca;;;;Intel Atom D410, D425
|
||||
Desktop;;Pineview (Bonnell);B0;18;106ca;;;;Intel Atom D510, D525
|
||||
Mobile;;Pineview (Bonnell);A0;05;106ca;;;;Intel Atom N435, N450, N455, N470, N475
|
||||
Mobile;;Pineview (Bonnell);B0;18;106ca;;;;Intel Atom N550, N570
|
||||
Server;;Dunnington (Penryn);A1;08;106d1;;;Intel Xeon MP;Intel Xeon E7420, E7430, E7440, E7450, E7458, L7445, X7460
|
||||
Server;;Jasper Forest (Nehalem);B0;09;106e4;NHM;;;Xeon EC3528, EC3529, EC5509, EC5539, EC5549, LC3518, LC3528, LC5518, LC5528, Celeron P1053
|
||||
Dekstop;;Lynnfield (Nehalem);B1;13;106e5;NHM;;Core i7-8xx, i5-7xx;
|
||||
Mobile;;Clarksfield (Nehalem);B1;13;106e5;NHM;;Core i7-9xxXM, i7-8xxQM, i7-7xxQM;
|
||||
Server;;Lynnfield Xeon (Nehalem);B1;13;106e5;NHM;;Xeon L3426, X24xx;
|
||||
Desktop;;Westmere;K0,C2;12;20652;WSM;;Core i7-6xx, i5-6xx/5xx/4xx, i3-5xx/3xx, Pentium G69xx/P6xxx/U5xxx, Celeon P45xx/U3xxx;
|
||||
Mobile;;Westmere;K0,C2;12;20652;WSM;;Core i7-6xxM, i5-6xxM/4xxM, i3-5xxM/3xxM;
|
||||
Server;;Westmere;K0,C2;12;20652;WSM;;Xeon L3406;
|
||||
Desktop;;Clarkdale (Westmere);K0;92;20655;WSM;;Core i7-6xxE/LE/UE, i5-5xxE, i3-3xxE;
|
||||
Mobile;;Arrandale (Westmere);K0;92;20655;WSM;;Core i7-6xxM/LM/UM, i5-5xxM/UM, i3-3xxM/UM, Pentium Mobile P6xxx/U5xxx, Celeron Mobile P4xxx/U3xxx;
|
||||
SOC;;Lincroft (Bonnell);C0;01;20661;;;;Intel Atom Z600, Z605, Z610, Z612, Z615, Z620, Z625, Z650, Z670
|
||||
SOC;;Tunnell Creek (Bonnell);B0,B1;02;20661;;;;Intel Atom E620, E620T, E640, E640T, E660, E660T, E680, E680T
|
||||
Desktop;;Sandy Bridge;D2,J1,Q0;12;206a7;SNB;;Core Gen2;
|
||||
Mobile;;Sandy Bridge;D2,J1,Q0;12;206a7;SNB;;Core Gen2 Mobile;
|
||||
Server;;Sandy Bridge;D2,Q0;12;206a7;SNB;Xeon E3;Xeon E3;
|
||||
Desktop;;Gulftown (Westmere);B1;03;206c2;WSM;;;Core i7-970/980/980X/990X
|
||||
Server;;Westmere-EP;B1;03;206c2;WSM;EP;Xeon E/L/X56xx;
|
||||
Server;;Westmere-WS;B1;03;206c2;WSM;WS;Xeon W36xx;
|
||||
Desktop;;Sandy Bridge;C1,M0;6d;206d6;SNB;E;Core i7-39xx, i7-38xx;
|
||||
Server;;Sandy Bridge;C1,M0;6d;206d6;SNB;EN,EP;Xeon E5;
|
||||
Desktop;;Sandy Bridge;C2,M1;6d;206d7;SNB;E;Core i7-39xx, i7-38xx;
|
||||
Server;;Sandy Bridge;C2,M1;6d;206d7;SNB;EN,EP;Xeon E5;
|
||||
Server;;Nehalem;D0;04;206e6;NHM;EX;Xeon E/L/X65xx/75xx;
|
||||
Server;;Westmere-EX;A2;05;206f2;WSM;EX;Xeon E7;
|
||||
SOC;;Valleyview;C0;02;30678;VLV;;Atom Z36xx, Z37xx, Z38xx, Z39xx;
|
||||
SOC;;Valleyview;C0;0C;30678;VLV;;Celeron N2xxx, Pentium N35xx;
|
||||
SOC;;Valleyview;D0;0F;30679;VLV;;Atom E38xx;
|
||||
Desktop;;Ivy Bridge;E1,E2,L1;12;306a9;IVB;;Core Gen3;
|
||||
Mobile;;Ivy Bridge;E1,E2,L1;12;306a9;IVB;;Core Gen3 Mobile;
|
||||
Server;;Ivy Bridge;E1,E2,L1;12;306a9;IVB;;Xeon E3 v2;
|
||||
Desktop;;Haswell;Cx,Dx;32;306c3;HSW;S;Core Gen4;
|
||||
Mobile;;Haswell;Cx,Dx;32;306c3;HSW;H;Core Gen4 Mobile;
|
||||
Server;;Haswell;Cx,Dx;32;306c3;HSW;Xeon E3;Xeon E3 v3;
|
||||
Mobile;;Broadwell;E0,F0;c0;306d4;BDW;U,Y;Core Gen5 Mobile;
|
||||
Desktop;;Ivy Bridge;S1;ed;306e4;IVB;E;Core-i7 49xx/48xx;Core i7-4960X/4930K/4820K
|
||||
Server;;Ivy Bridge;C0,C1,M1,S1;ed;306e4;IVB;EP;Xeon E5 v2;
|
||||
Server;;Ivy Bridge;;ed;306e6;IVB;EX;Xeon E7 v2 ES;
|
||||
Server;;Ivy Bridge;D1;ed;306e7;IVB;EX;Xeon E7 v2;
|
||||
Desktop;;Haswell;C0,C1,M1,R2;6f;306f2;HSX;E;Core i7-59xx/58xx;
|
||||
Server;;Haswell;C0,C1,M1,R2;6f;306f2;HSX;EN,EP,EP 4S;Xeon E5 v3;
|
||||
Server;;Haswell;E0;80;306f4;HSX;EX;Xeon E7 v3;
|
||||
Mobile;;Haswell;Cx,Dx;72;40651;HSW;U;Core Gen4 Mobile;
|
||||
Desktop;;Broadwell;E0,G0;22;40671;BDW;S;Core Gen5;
|
||||
Mobile;;Broadwell;E0,G0;22;40671;BDW;H;Core Gen5 Mobile;
|
||||
Server;;Broadwell;E0,G0;22;40671;BDW;Xeon E3;Xeon E3 v4;
|
||||
Desktop;;Haswell;Cx,Dx;32;40661;HSW;R;Core Gen4;
|
||||
Mobile;;Haswell;Cx,Dx;32;40661;HSW;H;Core Gen4 Mobile;
|
||||
SOC;;Cherry View;C0;01;406c3;CHV;;Atom x5-Zxxxx;
|
||||
SOC;;Cherry View;D0;01;406c4;CHV;;Celeron Jxxxx, N3xxx, Pentium J3xxx, N3xxx, Atom x5-E8000;
|
||||
SOC;;Avoton;B0,C0;01;406d8;AVN;;Atom C2xxx;
|
||||
Mobile;;Skylake;D0;c0;406e3;SKL;U,Y;Core Gen6 Mobile;
|
||||
Mobile;;Skylake;K1;c0;406e3;SKL;U 2+3e;Core Gen6 Mobile;
|
||||
Desktop;;Broadwell;B0,M0,R0;ef;406f1;BDX;E;Core i7-69xx/68xx;
|
||||
Server;;Broadwell;B0,M0,R0;ef;406f1;BDX;EP,EX;Xeon E5/E7 v4;
|
||||
Server;;Broadwell;B0,M0,R0;ef;406f1;BDX;ML;Xeon E5/E7 v4;
|
||||
Server;;Skylake;B1;97;50653;SKX;SP;Xeon Scalable;
|
||||
Desktop;;Skylake;H0,M0,U0;b7;50654;SKX;X;Core i9-7xxxX, i9-9xxxX;
|
||||
Server;;Skylake;H0,M0,U0;b7;50654;SKX;SP,W;Xeon Scalable;
|
||||
Server;;Skylake;M1;b7;50654;SKX;D;Xeon D-21xx;
|
||||
Server;;Cascade Lake;B0;bf;50656;CLX;SP;Xeon Scalable Gen2;
|
||||
Desktop;;Cascade Lake;B1,L1;bf;50657;CLX;X;;
|
||||
Server;;Cascade Lake;B1,L1;bf;50657;CLX;SP;Xeon Scalable Gen2;
|
||||
Server;;Cascade Lake;B1,L1;bf;50657;CLX;W;;Xeon W-3275M, W-3275, W-3265M, W-3265, W-3245M, W-3245, W-3235, W-3225, W-3223, W-2295, W-2275, W-2265, W-2255, W-2245, W-2235, W-2225, W-2223
|
||||
Server;;Cooper Lake;A1;bf;5065b;CPX;SP;Xeon Scalable Gen3;
|
||||
Server;;Broadwell;V1;10;50662;BDX;DE;;Xeon D-1520/40
|
||||
Server;;Broadwell;V2,V3;10;50663;BDX;DE;;Xeon D-1518/19/21/27/28/31/33/37/41/48, Pentium D1507/08/09/17/19
|
||||
Server;;Broadwell;Y0;10;50664;BDX;DE;;Xeon D-1557/59/67/71/77/81/87
|
||||
Server;;Broadwell;A0,A1;10;50665;BDX;NS;;Xeon D-1513N/23/33/43/53
|
||||
Server;;Hewitt Lake (Broadwell);A1;10;50665;HWL;;;Xeon D-1602/22/23N/27/33N/37/49N/53N
|
||||
Server;;Knights Landing;B0;78;50671;KNL;;Xeon Phi x200;Xeon Phi 7210, 7210F, 7230, 7230F, 7250, 7250F, 7290, 7290F
|
||||
SOC;;Broxton;C0;01;506c2;BXT;;Atom T5500/5700
|
||||
SOC;;Apollo Lake;D0;03;506c9;APL;;Pentium N/J4xxx, Celeron N/J3xxx, Atom x5/7-E39xx;
|
||||
SOC;;Apollo Lake;B1,F1;03;506ca;APL;;Atom 3900 Series;Atom x5-E3930, x5-E3940, x7-E3950
|
||||
Desktop;;Skylake;N0,R0,S0;36;506e3;SKL;S;Core Gen6;
|
||||
Mobile;;Skylake;N0,R0,S0;36;506e3;SKL;H;Core Gen6 Mobile;
|
||||
Server;;Skylake;N0,R0,S0;36;506e3;SKL;Xeon E3;Xeon E3 v5;
|
||||
SOC;;Denverton;B0;01;506f1;DNV;;Atom C3xxx;
|
||||
SOC;;XMM 7272 (SoFIA);;01;60650;;;XMM 7272
|
||||
Mobile;;Cannon Lake;D0;80;60663;CNL;U;Core Gen8 Mobile;
|
||||
SOC;;Gemini Lake;B0;01;706a1;GLK;;;Pentium J5005/N5000, Celeron J4005/J4105/N4000/N4100
|
||||
SOC;;Gemini Lake;R0;01;706a8;GLK;R;;Pentium J5040/N5030, Celeron J4125/J4025/N4020/N4120
|
||||
Mobile;;Ice Lake;D1;80;706e5;ICL;U,Y;Core Gen10 Mobile;
|
||||
Server;;Knights Mill;A0;08;80650;KNM;;Xeon hi 72x5;Xeon Phi 7235, 7285, 7295
|
||||
Mobile;;Tiger Lake;B1;80;806c1;TGL;UP3,UP4;Core Gen11 Mobile;
|
||||
Mobile;;Amber Lake;H0;10;806e9;AML;Y 2+2;Core Gen8 Mobile;
|
||||
Mobile;;Kaby Lake;H0;c0;806e9;KBL;U,Y;Core Gen7 Mobile;
|
||||
Mobile;;Kaby Lake;J1;c0;806e9;KBL;U 2+3e;Core Gen7 Mobile;
|
||||
Mobile;;Coffee Lake;D0;c0;806ea;CFL;U 4+3e;Core Gen8 Mobile;
|
||||
Mobile;;Kaby Lake;Y0;c0;806ea;KBL;R;Core Gen8 Mobile;
|
||||
Mobile;;Amber Lake;V0;94;806ec;AML;Y 4+2;Core Gen10 Mobile;
|
||||
Mobile;;Comet Lake;V0;94;806ec;CML;U 4+2;Core Gen10 Mobile;
|
||||
Mobile;;Whiskey Lake;W0;d0;806eb;WHL;U;Core Gen8 Mobile;
|
||||
Mobile;;Whiskey Lake;V0;94;806ec;WHL;U;Core Gen8 Mobile;
|
||||
Mobile;;Whiskey Lake;V0;94;806ed;WHL;U;Core Gen8 Mobile;
|
||||
Desktop;;Kaby Lake;B0;2a;906e9;KBL;S,X;Core Gen7;
|
||||
Mobile;;Kaby Lake;B0;2a;906e9;KBL;G,H;Core Gen7 Mobile;
|
||||
Server;;Kaby Lake;B0;2a;906e9;KBL;Xeon E3;Xeon E3 v6;
|
||||
Desktop;;Coffee Lake;U0;22;906ea;CFL;S;Core Gen8 Desktop;
|
||||
Mobile;;Coffee Lake;U0;22;906ea;CFL;H;Core Gen8 Mobile;
|
||||
Server;;Coffee Lake;U0;22;906ea;CFL;Xeon E;Xeon E;
|
||||
Desktop;;Coffee Lake;B0;02;906eb;CFL;S;Core Gen8 Desktop;
|
||||
Mobile;;Coffee Lake;B0;02;906eb;CFL;H;Core Gen8 Mobile;
|
||||
Server;;Coffee Lake;B0;02;906eb;CFL;E;Xeon E;
|
||||
Desktop;;Coffee Lake;P0;22;906ec;CFL;S;Core Gen9 Desktop;
|
||||
Mobile;;Coffee Lake;P0;22;906ec;CFL;H;Core Gen9 Mobile;
|
||||
Server;;Coffee Lake;P0;22;906ec;CFL;Xeon E;Xeon E;
|
||||
Desktop;;Coffee Lake;R0;22;906ed;CFL;S;Core Gen9 Desktop;
|
||||
Mobile;;Coffee Lake;R0;22;906ed;CFL;H;Core Gen9 Mobile;
|
||||
Server;;Coffee Lake;R0;22;906ed;CFL;Xeon E;Xeon E;
|
||||
Mobile;;Comet Lake;R1;20;a0652;CML;H;Core Gen10 Mobile;
|
||||
Desktop;;Comet Lake;G1;22;a0653;CML;S 6+2;Core Gen10 Desktop;
|
||||
Desktop;;Comet Lake;Q0;22;a0655;CML;S 10+2;Core Gen10 Desktop;
|
||||
Mobile;;Comet Lake;A0;80;a0660;CML;U 6+2;Core Gen10 Mobile;
|
||||
Mobile;;Comet Lake;K0;80;a0661;CML;U 6+2 v2;Core Gen10 Mobile;
|
||||
SOC;;Lakefield;B2,B3;10;806a1;LKF;;Core w/Hybrid Technology;
|
||||
|
||||
# sources:
|
||||
# https://en.wikichip.org/wiki/intel/cpuid
|
||||
# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/x86/include/asm/intel-family.h
|
||||
# releasenote from microcode releases
|
||||
# https://software.intel.com/security-software-guidance/processors-affected-transient-execution-attack-mitigation-product-cpu-model
|
||||
# https://en.wikipedia.org/wiki/Cascade_Lake_(microarchitecture)
|
||||
# https://en.wikipedia.org/wiki/List_of_Intel_Broadwell-based_Xeon_microprocessors
|
||||
# https://github.com/InstLatx64/InstLatx64
|
||||
# https://fossies.org/linux/cpuid/cpuid.c
|
||||
# https://software.intel.com/content/www/us/en/develop/articles/intel-architecture-and-processor-identification-with-cpuid-model-and-family-numbers.html
|
||||
# http://ixbtlabs.com/articles/cpuerrata/index.html
|
||||
# http://bios.rom.by/ROMutils/BIOS_Patcher/ALLCODES.TXT
|
||||
@ -127,23 +127,41 @@ for f in $(grep -E '/intel-ucode.*/[0-9a-f][0-9a-f]-[0-9a-f][0-9a-f]-[0-9a-f][0-
|
||||
|
||||
# Generate tags with codename information, in case
|
||||
# it is available
|
||||
cpuid_up="$(echo "$cpuid" | tr 'a-z' 'A-Z')"
|
||||
if [ -e "$CODENAMES" ]; then
|
||||
grep ' '"$cpuid_up"' ' "$CODENAMES" \
|
||||
| while IFS=$'\t' read segm int_fname codename stepping candidate_pf rest; do
|
||||
cpuid_up="$(echo "$cpuid" | tr 'a-z' 'A-Z')"
|
||||
cpuid_short="$(printf "%x" "0x$cpuid")"
|
||||
(grep ' '"$cpuid_up"' ' "$CODENAMES" || :; grep ';'"$cpuid_short"';' "$CODENAMES" || :) \
|
||||
| while IFS=$';\t' read segm int_fname codename stepping candidate_pf cpuid_cn cname variants rest; do
|
||||
[ "x${segm###}" = "x$segm" ] || continue
|
||||
[ -n "${segm}" ] || continue
|
||||
codename=$(echo "$codename" | tr ' (),' '_[];')
|
||||
candidate_pf=$(printf "%u" "0x${candidate_pf}")
|
||||
[ \( 0 -ne "$pf_mask" \) -a \
|
||||
\( "$candidate_pf" -ne "$((candidate_pf & pf_mask))" \) ] || { \
|
||||
printf "iucode_rev(fname:%s;cpuid:%s;pf_mask:0x%x;segment:\"%s\";codename:\"%s\";stepping:\"%s\";pf_model:0x%x) = %s\n" \
|
||||
"$ucode_fname" "$cpuid" "$pf_mask" \
|
||||
"$segm" "$codename" "$stepping" "$candidate_pf" \
|
||||
"$rev";
|
||||
printf "iucode_date(fname:%s;cpuid:%s;pf_mask:0x%x;segment:\"%s\";codename:\"%s\";stepping:\"%s\";pf_model:0x%x) = %s.%s.%s\n" \
|
||||
"$ucode_fname" "$cpuid" "$pf_mask" \
|
||||
"$segm" "$codename" "$stepping" "$candidate_pf" \
|
||||
"$date_y" "$date_m" "$date_d";
|
||||
}
|
||||
(IFS=','; for s in $stepping; do
|
||||
[ \( 0 -ne "$pf_mask" \) -a \
|
||||
\( 0 -eq "$((candidate_pf & pf_mask))" \) ] || { \
|
||||
printf "iucode_rev(fname:%s;cpuid:%s;pf_mask:0x%x;segment:\"%s\";codename:\"%s\";stepping:\"%s\";pf_model:0x%x) = %s\n" \
|
||||
"$ucode_fname" "$cpuid" "$pf_mask" \
|
||||
"$segm" "$codename" "$s" "$candidate_pf" \
|
||||
"$rev";
|
||||
printf "iucode_date(fname:%s;cpuid:%s;pf_mask:0x%x;segment:\"%s\";codename:\"%s\";stepping:\"%s\";pf_model:0x%x) = %s.%s.%s\n" \
|
||||
"$ucode_fname" "$cpuid" "$pf_mask" \
|
||||
"$segm" "$codename" "$s" "$candidate_pf" \
|
||||
"$date_y" "$date_m" "$date_d";
|
||||
if [ "$cpuid_short" = "$cpuid_cn" -a -n "$variants" ]; then
|
||||
(IFS=','; for v in $variants; do
|
||||
v=$(echo "$v" | tr ' (),' '_[];')
|
||||
printf "iucode_rev(fname:%s;cpuid:%s;pf_mask:0x%x;segment:\"%s\";codename:\"%s_%s\";stepping:\"%s\";pf_model:0x%x) = %s\n" \
|
||||
"$ucode_fname" "$cpuid" "$pf_mask" \
|
||||
"$segm" "$codename" "$v" "$s" "$candidate_pf" \
|
||||
"$rev";
|
||||
printf "iucode_date(fname:%s;cpuid:%s;pf_mask:0x%x;segment:\"%s\";codename:\"%s_%s\";stepping:\"%s\";pf_model:0x%x) = %s.%s.%s\n" \
|
||||
"$ucode_fname" "$cpuid" "$pf_mask" \
|
||||
"$segm" "$codename" "$v" "$s" "$candidate_pf" \
|
||||
"$date_y" "$date_m" "$date_d";
|
||||
done)
|
||||
fi
|
||||
}
|
||||
done)
|
||||
done
|
||||
fi
|
||||
|
||||
|
||||
855
SOURCES/gen_updates2.py
Executable file
855
SOURCES/gen_updates2.py
Executable file
@ -0,0 +1,855 @@
|
||||
#! /usr/bin/python
|
||||
# SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
import argparse
|
||||
import errno
|
||||
import io
|
||||
import itertools
|
||||
import os
|
||||
import re
|
||||
import shutil
|
||||
import struct
|
||||
import sys
|
||||
import tempfile
|
||||
from subprocess import PIPE, Popen, STDOUT
|
||||
|
||||
# Python 3 shims
|
||||
try:
|
||||
from functools import reduce
|
||||
except:
|
||||
pass
|
||||
try:
|
||||
from itertools import zip_longest as izip_longest
|
||||
except:
|
||||
from itertools import izip_longest
|
||||
|
||||
# revs:
|
||||
# [ { "path", "cpuid", "pf", "rev", "date" } ]
|
||||
|
||||
# artifacts:
|
||||
# * content summary (per-file)
|
||||
# * overlay summary (per-fms/pf)
|
||||
# * changelog (per-file?)
|
||||
# * discrepancies (per-fms/pf)
|
||||
|
||||
log_level = 0
|
||||
print_date = False
|
||||
|
||||
|
||||
def log_status(msg, level=0):
|
||||
global log_level
|
||||
|
||||
if log_level >= level:
|
||||
sys.stderr.write(msg + "\n")
|
||||
|
||||
|
||||
def log_info(msg, level=2):
|
||||
global log_level
|
||||
|
||||
if log_level >= level:
|
||||
sys.stderr.write("INFO: " + msg + "\n")
|
||||
|
||||
|
||||
def log_warn(msg, level=1):
|
||||
global log_level
|
||||
|
||||
if log_level >= level:
|
||||
sys.stderr.write("WARNING: " + msg + "\n")
|
||||
|
||||
|
||||
def log_error(msg, level=-1):
|
||||
global log_level
|
||||
|
||||
if log_level >= level:
|
||||
sys.stderr.write("ERROR: " + msg + "\n")
|
||||
|
||||
|
||||
def remove_prefix(text, prefix):
|
||||
if isinstance(prefix, str):
|
||||
prefix = [prefix, ]
|
||||
|
||||
for p in prefix:
|
||||
pfx = p if p.endswith(os.sep) else p + os.sep
|
||||
if text.startswith(pfx):
|
||||
return text[len(pfx):]
|
||||
|
||||
return text
|
||||
|
||||
|
||||
def file_walk(args, yield_dirs=False):
|
||||
for content in args:
|
||||
if os.path.isdir(content):
|
||||
if yield_dirs:
|
||||
yield ("", content)
|
||||
for root, dirs, files in os.walk(content):
|
||||
if yield_dirs:
|
||||
for f in dirs:
|
||||
p = os.path.join(root, f)
|
||||
yield (remove_prefix(p, content), p)
|
||||
for f in files:
|
||||
p = os.path.join(root, f)
|
||||
yield (remove_prefix(p, content), p)
|
||||
elif os.path.exists(content):
|
||||
yield ("", content)
|
||||
else:
|
||||
raise IOError(errno.ENOENT, os.strerror(errno.ENOENT), content)
|
||||
|
||||
|
||||
def cpuid_fname(c):
|
||||
return "%02x-%02x-%02x" % (
|
||||
((c >> 16) & 0xff0) + ((c >> 8) & 0xf),
|
||||
((c >> 12) & 0xf0) + ((c >> 4) & 0xf),
|
||||
c & 0xf)
|
||||
|
||||
|
||||
def read_revs_dir(path, src=None, ret=None):
|
||||
if ret is None:
|
||||
ret = []
|
||||
|
||||
ucode_re = re.compile('[0-9a-f]{2}-[0-9a-f]{2}-0[0-9a-f]$')
|
||||
ucode_dat_re = re.compile('microcode.*\.dat$')
|
||||
|
||||
for rp, ap in file_walk([path, ]):
|
||||
rp_fname = os.path.basename(rp)
|
||||
if not ucode_re.match(rp_fname) and not ucode_dat_re.match(rp_fname):
|
||||
continue
|
||||
|
||||
# Text-based format
|
||||
data = None
|
||||
if ucode_dat_re.match(rp_fname):
|
||||
data = io.BytesIO()
|
||||
with open(ap, "r") as f:
|
||||
for line in f:
|
||||
if line.startswith("/"):
|
||||
continue
|
||||
vals = line.split(",")
|
||||
for val in vals:
|
||||
val = val.strip()
|
||||
if not val:
|
||||
continue
|
||||
data.write(struct.pack("<I", int(val, 16)))
|
||||
sz = data.seek(0, os.SEEK_CUR)
|
||||
data.seek(0, os.SEEK_SET)
|
||||
else:
|
||||
sz = os.stat(ap).st_size
|
||||
|
||||
try:
|
||||
with data or open(ap, "rb") as f:
|
||||
log_info("Processing %s" % ap)
|
||||
offs = 0
|
||||
while offs < sz:
|
||||
f.seek(offs, os.SEEK_SET)
|
||||
hdr = struct.unpack("IiIIIIIIIIII", f.read(48))
|
||||
ret.append({"path": rp, "src": src or path,
|
||||
"cpuid": hdr[3], "pf": hdr[6], "rev": hdr[1],
|
||||
"date": hdr[2], "offs": offs, "cksum": hdr[4],
|
||||
"data_size": hdr[7], "total_size": hdr[8]})
|
||||
|
||||
if hdr[8] and hdr[8] - hdr[7] > 48:
|
||||
f.seek(hdr[7], os.SEEK_CUR)
|
||||
ext_tbl = struct.unpack("IIIII", f.read(20))
|
||||
log_status("Found %u extended signatures for %s:%#x" %
|
||||
(ext_tbl[0], rp, offs), level=1)
|
||||
|
||||
cur_offs = offs + hdr[7] + 48 + 20
|
||||
ext_sig_cnt = 0
|
||||
while cur_offs < offs + hdr[8] \
|
||||
and ext_sig_cnt <= ext_tbl[0]:
|
||||
ext_sig = struct.unpack("III", f.read(12))
|
||||
ret.append({"path": rp, "src": src or path,
|
||||
"cpuid": ext_sig[0], "pf": ext_sig[1],
|
||||
"rev": hdr[1], "date": hdr[2],
|
||||
"offs": offs, "ext_offs": cur_offs,
|
||||
"cksum": hdr[4],
|
||||
"ext_cksum": ext_sig[2],
|
||||
"data_size": hdr[7],
|
||||
"total_size": hdr[8]})
|
||||
log_status(("Got ext sig %#x/%#x for " +
|
||||
"%s:%#x:%#x/%#x") %
|
||||
(ext_sig[0], ext_sig[1], rp, offs,
|
||||
hdr[3], hdr[6]), level=2)
|
||||
|
||||
cur_offs += 12
|
||||
ext_sig_cnt += 1
|
||||
|
||||
offs += hdr[8] or 2048
|
||||
except Exception as e:
|
||||
log_error("a problem occurred while processing %s: %s" % (ap, e),
|
||||
level=1)
|
||||
|
||||
return ret
|
||||
|
||||
|
||||
def read_revs_rpm(path, ret=None):
|
||||
if ret is None:
|
||||
ret = []
|
||||
|
||||
dir_tmp = tempfile.mkdtemp()
|
||||
|
||||
log_status("Trying to extract files from RPM \"%s\"..." % path,
|
||||
level=1)
|
||||
|
||||
rpm2cpio = Popen(args=["rpm2cpio", path], stdout=PIPE, stderr=PIPE,
|
||||
close_fds=True)
|
||||
cpio = Popen(args=["cpio", "-idmv", "*??-??-??", "*microcode*.dat"],
|
||||
cwd=dir_tmp, stdin=rpm2cpio.stdout,
|
||||
stdout=PIPE, stderr=STDOUT)
|
||||
out, cpio_stderr = cpio.communicate()
|
||||
rpm2cpio_out, rpm2cpio_err = rpm2cpio.communicate()
|
||||
|
||||
rpm2cpio_ret = rpm2cpio.returncode
|
||||
cpio_ret = cpio.returncode
|
||||
|
||||
log_info("rpm2cpio exit code: %d, cpio exit code: %d" %
|
||||
(rpm2cpio_ret, cpio_ret))
|
||||
if rpm2cpio_err:
|
||||
log_info("rpm2cpio stderr:\n%s" % rpm2cpio_err, level=3)
|
||||
if out:
|
||||
log_info("cpio output:\n%s" % out, level=3)
|
||||
if cpio_stderr:
|
||||
log_info("cpio stderr:\n%s" % cpio_stderr, level=3)
|
||||
|
||||
if rpm2cpio_ret == 0 and cpio_ret == 0:
|
||||
ret = read_revs_dir(dir_tmp, path)
|
||||
|
||||
shutil.rmtree(dir_tmp)
|
||||
|
||||
return ret
|
||||
|
||||
|
||||
def read_revs(path, ret=None):
|
||||
if ret is None:
|
||||
ret = []
|
||||
if os.path.isdir(path):
|
||||
return read_revs_dir(path, ret)
|
||||
else:
|
||||
return read_revs_rpm(path, ret)
|
||||
|
||||
|
||||
def gen_mc_map(mc_data, merge=False, merge_path=False):
|
||||
"""
|
||||
Converts an array of microcode file information to a map with path/sig/pf
|
||||
as a key.
|
||||
|
||||
merge: whether to leave only the newest mc variant in the map or leave all
|
||||
possible variants.
|
||||
"""
|
||||
res = dict()
|
||||
|
||||
for mc in mc_data:
|
||||
key = (None if merge_path else mc["path"], mc["cpuid"], mc["pf"])
|
||||
|
||||
if key not in res:
|
||||
res[key] = dict()
|
||||
|
||||
cpuid = mc["cpuid"]
|
||||
cur_pf = mc["pf"]
|
||||
pid = 1
|
||||
while cur_pf > 0:
|
||||
if cur_pf & 1 and not (merge and pid in res[key]
|
||||
and res[key][pid]["rev"][0] >= mc["rev"]):
|
||||
if pid not in res[cpuid] or merge:
|
||||
res[cpuid][pid] = []
|
||||
res[cpuid][pid].append(mc)
|
||||
|
||||
cur_pf = cur_pf / 2
|
||||
pid = pid * 2
|
||||
|
||||
return res
|
||||
|
||||
|
||||
def gen_fn_map(mc_data, merge=False, merge_path=False):
|
||||
res = dict()
|
||||
|
||||
for mc in mc_data:
|
||||
key = (None if merge_path else mc["path"], mc["cpuid"], mc["pf"])
|
||||
if key in res:
|
||||
log_warn("Duplicate path/cpuid/pf: %s/%#x/%#x" % key)
|
||||
else:
|
||||
res[key] = []
|
||||
if merge and len(res[key]):
|
||||
if mc["rev"] > res[key][0]["rev"]:
|
||||
res[key][0] = mc
|
||||
else:
|
||||
res[key].append(mc)
|
||||
|
||||
return res
|
||||
|
||||
|
||||
def revcmp(a, b):
|
||||
return b["rev"] - a["rev"]
|
||||
|
||||
|
||||
class ChangeLogEntry:
|
||||
ADDED = 0
|
||||
REMOVED = 1
|
||||
UPDATED = 2
|
||||
DOWNGRADED = 3
|
||||
OTHER = 4
|
||||
|
||||
|
||||
def mc_stripped_path(mc):
|
||||
paths = ("usr/share/microcode_ctl/ucode_with_caveats/intel",
|
||||
"usr/share/microcode_ctl/ucode_with_caveats",
|
||||
"usr/share/microcode_ctl",
|
||||
"lib/firmware",
|
||||
"etc/firmware",
|
||||
)
|
||||
|
||||
return remove_prefix(mc["path"], paths)
|
||||
|
||||
|
||||
class mcnm:
|
||||
MCNM_ABBREV = 0
|
||||
MCNM_FAMILIES = 1
|
||||
MCNM_MODELS = 2
|
||||
MCNM_FAMILIES_MODELS = 3
|
||||
MCNM_CODENAME = 4
|
||||
|
||||
|
||||
def get_mc_cnames(mc, cmap, mode=mcnm.MCNM_ABBREV):
|
||||
if not isinstance(mc, dict):
|
||||
mc = mc_from_mc_key(mc)
|
||||
sig = mc["cpuid"]
|
||||
pf = mc["pf"]
|
||||
res = []
|
||||
|
||||
if not cmap:
|
||||
return None
|
||||
if sig not in cmap:
|
||||
log_info("No codename information for sig %#x" % sig)
|
||||
return None
|
||||
|
||||
cnames = cmap[sig]
|
||||
|
||||
if mode in (mcnm.MCNM_FAMILIES, mcnm.MCNM_MODELS,
|
||||
mcnm.MCNM_FAMILIES_MODELS):
|
||||
for c in cnames:
|
||||
if not (pf & c["pf_mask"]):
|
||||
continue
|
||||
for m, f in ((mcnm.MCNM_FAMILIES, "families"),
|
||||
(mcnm.MCNM_MODELS, "models")):
|
||||
if m & mode == 0:
|
||||
continue
|
||||
if f not in c or not c[f]:
|
||||
log_info("No %s for sig %#x in %r" % (f, sig, c))
|
||||
continue
|
||||
|
||||
res.append(c[f])
|
||||
|
||||
return ", ".join(res) or None
|
||||
|
||||
steppings = dict()
|
||||
suffices = dict()
|
||||
for c in cnames:
|
||||
if pf and not (pf & c["pf_mask"]):
|
||||
continue
|
||||
|
||||
if mode == mcnm.MCNM_ABBREV and "abbrev" in c and c["abbrev"]:
|
||||
cname = c["abbrev"]
|
||||
else:
|
||||
cname = c["codename"]
|
||||
|
||||
if cname not in suffices:
|
||||
suffices[cname] = set()
|
||||
if "variant" in c and c["variant"]:
|
||||
suffices[cname] |= set(c["variant"])
|
||||
|
||||
if cname not in steppings:
|
||||
steppings[cname] = set()
|
||||
if c["stepping"]:
|
||||
steppings[cname] |= set(c["stepping"])
|
||||
|
||||
for cname in sorted(steppings.keys()):
|
||||
cname_str = cname
|
||||
if len(suffices[cname]):
|
||||
cname_str += "-" + "/".join(sorted(suffices[cname]))
|
||||
if len(steppings[cname]):
|
||||
cname_str += " " + "/".join(sorted(steppings[cname]))
|
||||
res.append(cname_str)
|
||||
|
||||
return ", ".join(res) or None
|
||||
|
||||
|
||||
def mc_from_mc_key(k):
|
||||
return dict(zip(("path", "cpuid", "pf"), k))
|
||||
|
||||
|
||||
def mc_path(mc, pf_sfx=True, midword=None, cmap=None):
|
||||
if not isinstance(mc, dict):
|
||||
mc = mc_from_mc_key(mc)
|
||||
path = mc_stripped_path(mc) if mc["path"] is not None else None
|
||||
cpuid_fn = cpuid_fname(mc["cpuid"])
|
||||
fname = os.path.basename(mc["path"] or cpuid_fn)
|
||||
midword = "" if midword is None else " " + midword
|
||||
cname = get_mc_cnames(mc, cmap)
|
||||
cname_str = " (" + cname + ")" if cname else ""
|
||||
|
||||
if pf_sfx:
|
||||
sfx = "/0x%02x" % mc["pf"]
|
||||
else:
|
||||
sfx = ""
|
||||
|
||||
if not path or path == os.path.join("intel-ucode", cpuid_fn):
|
||||
return "%s%s%s%s" % (fname, sfx, cname_str, midword)
|
||||
else:
|
||||
return "%s%s%s%s (in %s)" % (cpuid_fn, sfx, cname_str, midword, path)
|
||||
|
||||
|
||||
def gen_changelog_file(old, new):
|
||||
pass
|
||||
|
||||
|
||||
def mc_cmp(old_mc, new_mc):
|
||||
res = []
|
||||
|
||||
old_mc_revs = [x["rev"] for x in old_mc]
|
||||
new_mc_revs = [x["rev"] for x in new_mc]
|
||||
common = set(old_mc_revs) & set(new_mc_revs)
|
||||
old_rev_list = [x for x in sorted(old_mc_revs) if x not in common]
|
||||
new_rev_list = [x for x in sorted(new_mc_revs) if x not in common]
|
||||
|
||||
if len(old_rev_list) != 1 or len(new_rev_list) != 1:
|
||||
for i in new_mc:
|
||||
if i["rev"] in new_rev_list:
|
||||
res.append((ChangeLogEntry.ADDED, None, i))
|
||||
for i in old_mc:
|
||||
if i["rev"] in old_rev_list:
|
||||
res.append((ChangeLogEntry.REMOVED, i, None))
|
||||
else:
|
||||
for old in old_mc:
|
||||
if old["rev"] == old_rev_list[0]:
|
||||
break
|
||||
for new in new_mc:
|
||||
if new["rev"] == new_rev_list[0]:
|
||||
break
|
||||
if new["rev"] > old["rev"]:
|
||||
res.append((ChangeLogEntry.UPDATED, old, new))
|
||||
elif new["rev"] < old["rev"]:
|
||||
res.append((ChangeLogEntry.DOWNGRADED, old, new))
|
||||
|
||||
return res
|
||||
|
||||
|
||||
def gen_changelog(old, new):
|
||||
res = []
|
||||
|
||||
old_map = gen_fn_map(old)
|
||||
new_map = gen_fn_map(new)
|
||||
|
||||
old_files = set(old_map.keys())
|
||||
new_files = set(new_map.keys())
|
||||
|
||||
both = old_files & new_files
|
||||
added = new_files - old_files
|
||||
removed = old_files - new_files
|
||||
|
||||
for f in sorted(added):
|
||||
p = mc_path(new_map[f][0])
|
||||
for old_f in sorted(removed):
|
||||
old_p = mc_path(old_map[old_f][0])
|
||||
if p == old_p and f[1] == old_f[1] and f[2] == old_f[2]:
|
||||
log_info("Matched %s (%s and %s)" %
|
||||
(p, old_map[old_f][0]["path"], new_map[f][0]["path"]))
|
||||
added.remove(f)
|
||||
removed.remove(old_f)
|
||||
|
||||
res += mc_cmp(old_map[old_f], new_map[f])
|
||||
|
||||
for f in sorted(added):
|
||||
for i in new_map[f]:
|
||||
res.append((ChangeLogEntry.ADDED, None, i))
|
||||
for f in sorted(removed):
|
||||
for i in old_map[f]:
|
||||
res.append((ChangeLogEntry.REMOVED, i, None))
|
||||
for f in sorted(both):
|
||||
res += mc_cmp(old_map[f], new_map[f])
|
||||
|
||||
return res
|
||||
|
||||
|
||||
def mc_date(mc):
|
||||
if isinstance(mc, dict):
|
||||
mc = mc["date"]
|
||||
return "%04x-%02x-%02x" % (mc & 0xffff, mc >> 24, (mc >> 16) & 0xff)
|
||||
|
||||
|
||||
def mc_rev(mc, date=None):
|
||||
'''
|
||||
While revision is signed for comparison purposes, historically
|
||||
it is printed as unsigned, Oh well.
|
||||
'''
|
||||
global print_date
|
||||
|
||||
if mc["rev"] < 0:
|
||||
rev = 2**32 + mc["rev"]
|
||||
else:
|
||||
rev = mc["rev"]
|
||||
|
||||
if date if date is not None else print_date:
|
||||
return "%#x (%s)" % (rev, mc_date(mc))
|
||||
else:
|
||||
return "%#x" % rev
|
||||
|
||||
|
||||
def print_changelog(clog, cmap, args):
|
||||
for e, old, new in sorted(clog):
|
||||
if e == ChangeLogEntry.ADDED:
|
||||
print("Addition of %s at revision %s" %
|
||||
(mc_path(new, midword="microcode", cmap=cmap), mc_rev(new)))
|
||||
elif e == ChangeLogEntry.REMOVED:
|
||||
print("Removal of %s at revision %s" %
|
||||
(mc_path(old, midword="microcode", cmap=cmap), mc_rev(old)))
|
||||
elif e == ChangeLogEntry.UPDATED:
|
||||
print("Update of %s from revision %s up to %s" %
|
||||
(mc_path(old, midword="microcode", cmap=cmap),
|
||||
mc_rev(old), mc_rev(new)))
|
||||
elif e == ChangeLogEntry.DOWNGRADED:
|
||||
print("Downgrade of %s from revision %s down to %s" %
|
||||
(mc_path(old, midword="microcode", cmap=cmap),
|
||||
mc_rev(old), mc_rev(new)))
|
||||
elif e == ChangeLogEntry.OTHER:
|
||||
print("Other change in %s:" % old["path"])
|
||||
print(" old: %#x/%#x: rev %s (offs %#x)" %
|
||||
(old["cpuid"], old["pf"], mc_rev(old), old["offs"]))
|
||||
print(" new: %#x/%#x: rev %s (offs %#x)" %
|
||||
(new["cpuid"], new["pf"], mc_rev(new), new["offs"]))
|
||||
|
||||
|
||||
class TableStyles:
|
||||
TS_CSV = 0
|
||||
TS_FANCY = 1
|
||||
|
||||
|
||||
def print_line(line, column_sz):
|
||||
print(" | ".join([str(x).ljust(column_sz[i])
|
||||
for i, x in zip(itertools.count(),
|
||||
itertools.chain(line,
|
||||
[""] * (len(column_sz) -
|
||||
len(line))))]).rstrip())
|
||||
|
||||
|
||||
def print_table(items, header=[], style=TableStyles.TS_CSV):
|
||||
if style == TableStyles.TS_CSV:
|
||||
for i in items:
|
||||
print(";".join(i))
|
||||
elif style == TableStyles.TS_FANCY:
|
||||
column_sz = list(reduce(lambda x, y:
|
||||
map(max, izip_longest(x, y, fillvalue=0)),
|
||||
[[len(x) for x in i]
|
||||
for i in itertools.chain(header, items)]))
|
||||
for i in header:
|
||||
print_line(i, column_sz)
|
||||
if header:
|
||||
print("-+-".join(["-" * x for x in column_sz]))
|
||||
for i in items:
|
||||
print_line(i, column_sz)
|
||||
|
||||
|
||||
def print_summary(revs, cmap, args):
|
||||
m = gen_fn_map(revs)
|
||||
cnames_mode = mcnm.MCNM_ABBREV if args.abbrev else mcnm.MCNM_CODENAME
|
||||
|
||||
header = []
|
||||
if args.header:
|
||||
header.append(["Path", "Offset", "Ext. Offset", "CPUID",
|
||||
"Platform ID Mask", "Revision", "Date", "Checksum",
|
||||
"Codenames"] +
|
||||
(["Models"] if args.models else []))
|
||||
tbl = []
|
||||
for k in sorted(m.keys()):
|
||||
for mc in m[k]:
|
||||
tbl.append([mc_stripped_path(mc),
|
||||
"0x%x" % mc["offs"],
|
||||
"0x%x" % mc["ext_offs"] if "ext_offs" in mc else "-",
|
||||
"0x%05x" % mc["cpuid"],
|
||||
"0x%02x" % mc["pf"],
|
||||
mc_rev(mc, date=False),
|
||||
mc_date(mc),
|
||||
"0x%08x" % mc["cksum"],
|
||||
get_mc_cnames(mc, cmap, cnames_mode) or ""] +
|
||||
([get_mc_cnames(mc, cmap,
|
||||
mcnm.MCNM_FAMILIES_MODELS)]
|
||||
if args.models else []))
|
||||
|
||||
print_table(tbl, header, style=TableStyles.TS_FANCY)
|
||||
|
||||
|
||||
def read_codenames_file(path):
|
||||
'''
|
||||
Supports two formats: new and old
|
||||
* old: tab-separated. Field order:
|
||||
Segment, (unused), Codename, (dash-separated) Stepping,
|
||||
Platform ID mask, CPUID, (unused) Update link, (unused) Specs link
|
||||
* new: semicolon-separated; support comments. Distinguished
|
||||
by the first line that starts with octothorp. Field order:
|
||||
Segment, Unused, Codename, Stepping, Platform ID mask, CPUID,
|
||||
Abbreviation, Variant(s), Families, Models
|
||||
'''
|
||||
old_fields = ["segment", "_", "codename", "stepping", "pf_mask", "sig",
|
||||
"_update", "_specs"]
|
||||
new_fields = ["segment", "_", "codename", "stepping", "pf_mask", "sig",
|
||||
"abbrev", "variant", "families", "models"]
|
||||
new_fmt = False
|
||||
field_names = old_fields
|
||||
|
||||
res = dict()
|
||||
|
||||
try:
|
||||
with open(path, "r") as f:
|
||||
for line in f:
|
||||
line = line.strip()
|
||||
if len(line) == 0:
|
||||
continue
|
||||
if line[0] == '#':
|
||||
new_fmt = True
|
||||
field_names = new_fields
|
||||
continue
|
||||
|
||||
fields = line.split(";" if new_fmt else "\t",
|
||||
1 + len(field_names))
|
||||
fields = dict(zip(field_names, fields))
|
||||
if "sig" not in fields:
|
||||
log_warn("Skipping %r (from \"%s\")" % (fields, line))
|
||||
continue
|
||||
|
||||
sig = fields["sig"] = int(fields["sig"], 16)
|
||||
fields["pf_mask"] = int(fields["pf_mask"], 16)
|
||||
fields["stepping"] = fields["stepping"].split(",")
|
||||
if "variant" in fields:
|
||||
if fields["variant"]:
|
||||
fields["variant"] = fields["variant"].split(",")
|
||||
else:
|
||||
fields["variant"] = []
|
||||
|
||||
if sig not in res:
|
||||
res[sig] = list()
|
||||
res[sig].append(fields)
|
||||
except Exception as e:
|
||||
log_error("a problem occurred while reading code names: %s" % e)
|
||||
|
||||
return res
|
||||
|
||||
|
||||
def print_discrepancies(rev_map, deps, cmap, args):
|
||||
"""
|
||||
rev_map: dict "name": revs
|
||||
deps: list of tuples (name, parent/None)
|
||||
"""
|
||||
sigs = set()
|
||||
|
||||
for p, r in rev_map.items():
|
||||
sigs |= set(r.keys())
|
||||
|
||||
if args.header:
|
||||
header1 = ["sig"]
|
||||
if args.print_vs:
|
||||
header2 = [""]
|
||||
for p, n, d in deps:
|
||||
header1.append(n)
|
||||
if args.print_vs:
|
||||
add = ""
|
||||
if d:
|
||||
for pd, nd, dd in deps:
|
||||
if pd == d:
|
||||
add = "(vs. %s)" % nd
|
||||
break
|
||||
header2.append(add)
|
||||
if args.models:
|
||||
header1.append("Model names")
|
||||
if args.print_vs:
|
||||
header2.append("")
|
||||
header = [header1] + ([header2] if args.print_vs else [])
|
||||
|
||||
tbl = []
|
||||
for s in sorted(sigs):
|
||||
out = [mc_path(s)]
|
||||
print_out = not args.print_filter
|
||||
print_date = args.min_date is None
|
||||
|
||||
for p, n, d in deps:
|
||||
cur = dict([(x["rev"], x) for x in rev_map[p][s]]) \
|
||||
if s in rev_map[p] else []
|
||||
v = "/".join([mc_rev(y) for x, y in sorted(cur.items())]) \
|
||||
if cur else "-"
|
||||
if d is not None:
|
||||
prev = [x["rev"] for x in rev_map[d][s]] if s in rev_map[d] \
|
||||
else []
|
||||
if [x for x in cur if x not in prev]:
|
||||
v += " (*)"
|
||||
print_out = True
|
||||
if args.min_date is not None and s in rev_map[p]:
|
||||
for x in rev_map[p][s]:
|
||||
print_date |= mc_date(x) > args.min_date
|
||||
out.append(v)
|
||||
|
||||
if print_out and print_date:
|
||||
if args.models:
|
||||
out.append(get_mc_cnames(s, cmap) or "")
|
||||
tbl.append(out)
|
||||
|
||||
print_table(tbl, header, style=TableStyles.TS_FANCY)
|
||||
|
||||
|
||||
def cmd_summary(args):
|
||||
revs = []
|
||||
for p in args.filelist:
|
||||
revs = read_revs(p, ret=revs)
|
||||
|
||||
codenames_map = read_codenames_file(args.codenames)
|
||||
|
||||
print_summary(revs, codenames_map, args)
|
||||
|
||||
return 0
|
||||
|
||||
|
||||
def cmd_changelog(args):
|
||||
codenames_map = read_codenames_file(args.codenames)
|
||||
base_path = args.filelist[0]
|
||||
upd_path = args.filelist[1]
|
||||
|
||||
base = read_revs(base_path)
|
||||
upd = read_revs(upd_path)
|
||||
|
||||
print_changelog(gen_changelog(base, upd), codenames_map, args)
|
||||
|
||||
return 0
|
||||
|
||||
|
||||
def cmd_discrepancies(args):
|
||||
"""
|
||||
filenames:
|
||||
* "<" prefix (possibly multiple times) to refer to a previous entry
|
||||
to compare against
|
||||
* "[name]" prefix is a name reference
|
||||
"""
|
||||
codenames_map = read_codenames_file(args.codenames)
|
||||
rev_map = dict()
|
||||
deps = list()
|
||||
cur = -1
|
||||
|
||||
for path in args.filelist:
|
||||
orig_path = path
|
||||
name = None
|
||||
cur += 1
|
||||
dep = None
|
||||
while True:
|
||||
if path[0] == '<':
|
||||
path = path[1:]
|
||||
dep = cur - 1 if dep is None else dep - 1
|
||||
elif path[0] == '[' and path.find(']') > 0:
|
||||
pos = path.find(']')
|
||||
name = path[1:pos]
|
||||
path = path[pos + 1:]
|
||||
else:
|
||||
break
|
||||
if name is None:
|
||||
name = path
|
||||
if dep is not None and dep < 0:
|
||||
log_error("Incorrect dep reference for '%s' (points to index %d)" %
|
||||
(orig_path, dep))
|
||||
return 1
|
||||
deps.append((path, name, deps[dep][0] if dep is not None else None))
|
||||
rev_map[path] = gen_fn_map(read_revs(path), merge=args.merge,
|
||||
merge_path=True)
|
||||
|
||||
print_discrepancies(rev_map, deps, codenames_map, args)
|
||||
|
||||
return 0
|
||||
|
||||
|
||||
def parse_cli():
|
||||
root_parser = argparse.ArgumentParser(prog="gen_updates",
|
||||
description="Intel CPU Microcode " +
|
||||
"parser")
|
||||
root_parser.add_argument("-C", "--codenames", default='codenames',
|
||||
help="Code names file")
|
||||
root_parser.add_argument("-v", "--verbose", action="count", default=0,
|
||||
help="Increase output verbosity")
|
||||
|
||||
cmdparsers = root_parser.add_subparsers(title="Commands",
|
||||
help="main gen_updates commands")
|
||||
|
||||
parser_s = cmdparsers.add_parser("summary",
|
||||
help="Generate microcode summary")
|
||||
parser_s.add_argument("-a", "--abbreviate", action="store_const",
|
||||
dest="abbrev", const=True, default=True,
|
||||
help="Abbreviate code names")
|
||||
parser_s.add_argument("-A", "--no-abbreviate", action="store_const",
|
||||
dest="abbrev", const=False,
|
||||
help="Do not abbreviate code names")
|
||||
parser_s.add_argument("-m", "--print-models", action="store_const",
|
||||
dest="models", const=True, default=False,
|
||||
help="Print models")
|
||||
parser_s.add_argument("-M", "--no-print-models",
|
||||
action="store_const", dest="models",
|
||||
const=False, help="Do not print models")
|
||||
parser_s.add_argument("-H", "--no-print-header",
|
||||
action="store_const", dest="header",
|
||||
const=False, default=True,
|
||||
help="Do not print hader")
|
||||
parser_s.add_argument("filelist", nargs="*", default=[],
|
||||
help="List or RPMs/directories to process")
|
||||
parser_s.set_defaults(func=cmd_summary)
|
||||
|
||||
parser_c = cmdparsers.add_parser("changelog",
|
||||
help="Generate changelog")
|
||||
parser_c.add_argument("filelist", nargs=2,
|
||||
help="RPMs/directories to compare")
|
||||
parser_c.set_defaults(func=cmd_changelog)
|
||||
|
||||
parser_d = cmdparsers.add_parser("discrepancies",
|
||||
help="Generate discrepancies")
|
||||
parser_d.add_argument("-s", "--merge-revs", action="store_const",
|
||||
dest="merge", const=True, default=False,
|
||||
help="Merge revisions that come" +
|
||||
" from different files")
|
||||
parser_d.add_argument("-S", "--no-merge-revs", action="store_const",
|
||||
dest="merge", const=False,
|
||||
help="Do not Merge revisions that come" +
|
||||
" from different files")
|
||||
parser_d.add_argument("-v", "--print-vs", action="store_const",
|
||||
dest="print_vs", const=True, default=False,
|
||||
help="Print base version ")
|
||||
parser_d.add_argument("-V", "--no-print-vs", action="store_const",
|
||||
dest="print_vs", const=False,
|
||||
help="Do not Merge revisions that come" +
|
||||
" from different files")
|
||||
parser_d.add_argument("-m", "--print-models", action="store_const",
|
||||
dest="models", const=True, default=True,
|
||||
help="Print model names")
|
||||
parser_d.add_argument("-M", "--no-print-models", action="store_const",
|
||||
dest="models", const=False,
|
||||
help="Do not print model names")
|
||||
parser_d.add_argument("-H", "--no-print-header", action="store_const",
|
||||
dest="header", const=False, default=True,
|
||||
help="Do not print hader")
|
||||
parser_d.add_argument("-a", "--print-all-files", action="store_const",
|
||||
dest="print_filter", const=False, default=True,
|
||||
help="Print all files")
|
||||
parser_d.add_argument("-c", "--print-changed-files", action="store_const",
|
||||
dest="print_filter", const=True,
|
||||
help="Print only changed files")
|
||||
parser_d.add_argument("-d", "--min-date", action="store",
|
||||
help="Minimum date filter")
|
||||
parser_d.add_argument("filelist", nargs='*',
|
||||
help="RPMs/directories to compare")
|
||||
parser_d.set_defaults(func=cmd_discrepancies)
|
||||
|
||||
args = root_parser.parse_args()
|
||||
if not hasattr(args, "func"):
|
||||
root_parser.print_help()
|
||||
return None
|
||||
return args
|
||||
|
||||
|
||||
def main():
|
||||
args = parse_cli()
|
||||
if args is None:
|
||||
return 1
|
||||
|
||||
return args.func(args)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
sys.exit(main())
|
||||
@ -1,4 +1,4 @@
|
||||
%define intel_ucode_version 20200609
|
||||
%define intel_ucode_version 20210216
|
||||
%global debug_package %{nil}
|
||||
|
||||
%define caveat_dir %{_datarootdir}/microcode_ctl/ucode_with_caveats
|
||||
@ -13,7 +13,7 @@
|
||||
Summary: CPU microcode updates for Intel x86 processors
|
||||
Name: microcode_ctl
|
||||
Version: %{intel_ucode_version}
|
||||
Release: 2%{?dist}
|
||||
Release: 1%{?dist}
|
||||
Epoch: 4
|
||||
License: CC0 and Redistributable, no modification permitted
|
||||
URL: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files
|
||||
@ -33,6 +33,11 @@ Source5: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Fi
|
||||
Source6: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/archive/microcode-20190918.tar.gz
|
||||
# microcode-20191115 release,containing revision 0xca of 06-[89]e-0X microcode
|
||||
Source7: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/archive/microcode-20191115.tar.gz
|
||||
# microcode-20201118 has removed 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode update
|
||||
# at revision 0x68; it is, however, may still be useful for some[1], so it is
|
||||
# to be preserved in a caveat.
|
||||
# [1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/39
|
||||
Source8: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/raw/microcode-20201112/intel-ucode/06-8c-01
|
||||
|
||||
|
||||
# systemd unit
|
||||
@ -50,6 +55,7 @@ Source32: reload_microcode
|
||||
|
||||
# docs
|
||||
Source41: README.caveats
|
||||
Source42: README
|
||||
|
||||
## Caveats
|
||||
# BDW EP/EX
|
||||
@ -110,9 +116,15 @@ Source170: 06-8e-9e-0x-dell_readme
|
||||
Source171: 06-8e-9e-0x-dell_config
|
||||
Source172: 06-8e-9e-0x-dell_disclaimer
|
||||
|
||||
# TGL-UP3/UP4 (CPUID 06-8c-01) hangs
|
||||
Source180: 06-8c-01_readme
|
||||
Source181: 06-8c-01_config
|
||||
Source182: 06-8c-01_disclaimer
|
||||
|
||||
# "Provides:" RPM tags generator
|
||||
Source200: gen_provides.sh
|
||||
Source1000: gen_provides.sh
|
||||
Source1001: codenames.list
|
||||
Source1002: gen_updates2.py
|
||||
|
||||
ExclusiveArch: %{ix86} x86_64
|
||||
BuildRequires: systemd-units
|
||||
@ -125,7 +137,7 @@ Requires(postun): systemd coreutils
|
||||
Requires(posttrans): dracut coreutils
|
||||
|
||||
%global _use_internal_dependency_generator 0
|
||||
%define __find_provides "%{SOURCE200}"
|
||||
%define __find_provides "%{SOURCE1000}" "%{SOURCE1001}"
|
||||
|
||||
%description
|
||||
This package provides microcode update files for Intel x86 and x86_64 CPUs.
|
||||
@ -169,6 +181,9 @@ tar xvvf "%{SOURCE7}" --wildcards --strip-components=2 \
|
||||
'*/intel-ucode/06-[89]e-0*'
|
||||
popd
|
||||
|
||||
# Moving 06-8c-01 microcode to intel-ucode-with-caveats
|
||||
cp "%{SOURCE8}" intel-ucode-with-caveats/
|
||||
|
||||
:
|
||||
|
||||
%install
|
||||
@ -200,20 +215,25 @@ install "%{SOURCE30}" "%{SOURCE31}" "%{SOURCE32}" \
|
||||
install -m 755 -d "%{buildroot}/%{_pkgdocdir}/caveats"
|
||||
|
||||
# caveats readme
|
||||
install "%{SOURCE41}" \
|
||||
install "%{SOURCE41}" "%{SOURCE42}" \
|
||||
-m 644 -t "%{buildroot}/%{_pkgdocdir}/"
|
||||
|
||||
# Provide Intel microcode license, as it requires so
|
||||
install -m 644 license \
|
||||
"%{buildroot}/%{_pkgdocdir}/LICENSE.intel-ucode"
|
||||
|
||||
# Provide release notes for Intel microcode
|
||||
install -m 644 releasenote \
|
||||
# Provide release notes, README and security for Intel microcode
|
||||
install -m 644 README.md \
|
||||
"%{buildroot}/%{_pkgdocdir}/README.intel-ucode"
|
||||
install -m 644 security.md \
|
||||
"%{buildroot}/%{_pkgdocdir}/SECURITY.intel-ucode"
|
||||
install -m 644 releasenote.md \
|
||||
"%{buildroot}/%{_pkgdocdir}/RELEASE_NOTES.intel-ucode"
|
||||
|
||||
# caveats
|
||||
install -m 644 "%{SOURCE100}" "%{SOURCE110}" "%{SOURCE120}" "%{SOURCE130}" \
|
||||
"%{SOURCE140}" "%{SOURCE150}" "%{SOURCE160}" "%{SOURCE170}" \
|
||||
"%{SOURCE180}" \
|
||||
-t "%{buildroot}/%{_pkgdocdir}/caveats/"
|
||||
|
||||
|
||||
@ -283,6 +303,21 @@ install -m 644 "%{SOURCE170}" "%{dell_latest_inst_dir}/readme"
|
||||
install -m 644 "%{SOURCE171}" "%{dell_latest_inst_dir}/config"
|
||||
install -m 644 "%{SOURCE172}" "%{dell_latest_inst_dir}/disclaimer"
|
||||
|
||||
# TGL caveat
|
||||
%define tgl_inst_dir %{buildroot}/%{caveat_dir}/intel-06-8c-01/
|
||||
install -m 755 -d "%{tgl_inst_dir}/intel-ucode"
|
||||
install -m 644 intel-ucode-with-caveats/06-8c-01 -t "%{tgl_inst_dir}/intel-ucode/"
|
||||
install -m 644 "%{SOURCE180}" "%{tgl_inst_dir}/readme"
|
||||
install -m 644 "%{SOURCE181}" "%{tgl_inst_dir}/config"
|
||||
install -m 644 "%{SOURCE182}" "%{tgl_inst_dir}/disclaimer"
|
||||
|
||||
# SUMMARY.intel-ucode generation
|
||||
# It is to be done only after file population, so, it is here,
|
||||
# at the end of the install stage
|
||||
/usr/libexec/platform-python "%{SOURCE1002}" -C "%{SOURCE1001}" \
|
||||
summary -A "%{buildroot}" \
|
||||
> "%{buildroot}/%{_pkgdocdir}/SUMMARY.intel-ucode"
|
||||
|
||||
|
||||
%post
|
||||
%systemd_post microcode.service
|
||||
@ -513,6 +548,108 @@ rm -rf %{buildroot}
|
||||
|
||||
|
||||
%changelog
|
||||
* Wed Feb 17 2021 Eugene Syromiatnikov <esyr@redhat.com> - 4:20210216-1
|
||||
- Update Intel CPU microcode to microcode-20210216 release (#1902884):
|
||||
- Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode (in
|
||||
intel-06-55-04/intel-ucode/06-55-04) from revision 0x2006a08 up
|
||||
to 0x2006a0a;
|
||||
- Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4003003
|
||||
up to 0x4003006;
|
||||
- Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision
|
||||
0x5003003 up to 0x5003006.
|
||||
|
||||
* Wed Feb 17 2021 Eugene Syromiatnikov <esyr@redhat.com> - 4:20201112-3
|
||||
- Remove 06-55-04/06-55-06/06-55-07 (SKX-SP/CLX-SP) microcode-20201110 caveats.
|
||||
|
||||
* Tue Dec 01 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20201112-2
|
||||
- Do not use "grep -q" in a pipe in check_caveats (#1902021).
|
||||
- Add 06-55-04/06-55-06/06-55-07 (SKX-SP/CLX-SP) microcode-20201110 caveats
|
||||
(#1902884).
|
||||
|
||||
* Fri Nov 13 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20201112-1
|
||||
- Update Intel CPU microcode to microcode-20201112 release (#1896912):
|
||||
- Addition of 06-8a-01/0x10 (LKF B2/B3) microcode at revision 0x28;
|
||||
- Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x32 up
|
||||
to 0x34;
|
||||
- Updated releasenote file.
|
||||
|
||||
* Fri Nov 13 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20201027-2
|
||||
- Disable 06-8c-01 (TGL-UP3/UP4 B1) microcode update by default (#1897534).
|
||||
|
||||
* Thu Oct 29 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20201027-1
|
||||
- Update Intel CPU microcode to microcode-20201027 release, addresses
|
||||
CVE-2020-8694, CVE-2020-8695, CVE-2020-8696, CVE-2020-8698
|
||||
(#1893266, #1893254, #1893234):
|
||||
- Addition of 06-55-0b/0xbf (CPX-SP A1) microcode at revision 0x700001e;
|
||||
- Addition of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode at revision 0x68;
|
||||
- Addition of 06-a5-02/0x20 (CML-H R1) microcode at revision 0xe0;
|
||||
- Addition of 06-a5-03/0x22 (CML-S 6+2 G1) microcode at revision 0xe0;
|
||||
- Addition of 06-a5-05/0x22 (CML-S 10+2 Q0) microcode at revision 0xe0;
|
||||
- Addition of 06-a6-01/0x80 (CML-U 6+2 v2 K0) microcode at revision
|
||||
0xe0;
|
||||
- Update of 06-4e-03/0xc0 (SKL-U/U 2+3e/Y D0/K1) microcode (in
|
||||
intel-06-4e-03/intel-ucode/06-4e-03) from revision 0xdc up to 0xe2;
|
||||
- Update of 06-55-04/0xb7 (SKX-D/SP/W/X H0/M0/M1/U0) microcode (in
|
||||
intel-06-55-04/intel-ucode/06-55-04) from revision 0x2006906 up
|
||||
to 0x2006a08;
|
||||
- Update of 06-5e-03/0x36 (SKL-H/S/Xeon E3 N0/R0/S0) microcode (in
|
||||
intel-06-5e-03/intel-ucode/06-5e-03) from revision 0xdc up to 0xe2;
|
||||
- Update of 06-8e-09/0x10 (AML-Y 2+2 H0) microcode (in
|
||||
intel-06-8e-9e-0x-dell/intel-ucode/06-8e-09) from revision 0xd6 up
|
||||
to 0xde;
|
||||
- Update of 06-8e-09/0xc0 (KBL-U/U 2+3e/Y H0/J1) microcode (in
|
||||
intel-06-8e-9e-0x-dell/intel-ucode/06-8e-09) from revision 0xd6 up
|
||||
to 0xde;
|
||||
- Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0, KBL-R Y0) microcode (in
|
||||
intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0a) from revision 0xd6 up
|
||||
to 0xe0;
|
||||
- Update of 06-8e-0b/0xd0 (WHL-U W0) microcode (in
|
||||
intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0b) from revision 0xd6 up
|
||||
to 0xde;
|
||||
- Update of 06-8e-0c/0x94 (AML-Y 4+2 V0, CML-U 4+2 V0, WHL-U V0)
|
||||
microcode (in intel-06-8e-9e-0x-dell/intel-ucode/06-8e-0c) from
|
||||
revision 0xd6 up to 0xde;
|
||||
- Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode (in
|
||||
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-09) from revision 0xd6 up
|
||||
to 0xde;
|
||||
- Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) microcode (in
|
||||
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0a) from revision 0xd6 up
|
||||
to 0xde;
|
||||
- Update of 06-9e-0b/0x02 (CFL-E/H/S B0) microcode (in
|
||||
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0b) from revision 0xd6 up
|
||||
to 0xde;
|
||||
- Update of 06-9e-0c/0x22 (CFL-H/S/Xeon E P0) microcode (in
|
||||
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0c) from revision 0xd6 up
|
||||
to 0xde;
|
||||
- Update of 06-9e-0d/0x22 (CFL-H/S/Xeon E R0) microcode (in
|
||||
intel-06-8e-9e-0x-dell/intel-ucode/06-9e-0d) from revision 0xd6 up
|
||||
to 0xde;
|
||||
- Update of 06-3f-02/0x6f (HSX-E/EN/EP/EP 4S C0/C1/M1/R2) microcode
|
||||
from revision 0x43 up to 0x44;
|
||||
- Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000157
|
||||
up to 0x1000159;
|
||||
- Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x4002f01
|
||||
up to 0x4003003;
|
||||
- Update of 06-55-07/0xbf (CLX-SP/W/X B1/L1) microcode from revision
|
||||
0x5002f01 up to 0x5003003;
|
||||
- Update of 06-5c-09/0x03 (APL D0) microcode from revision 0x38 up
|
||||
to 0x40;
|
||||
- Update of 06-5c-0a/0x03 (APL B1/F1) microcode from revision 0x16 up
|
||||
to 0x1e;
|
||||
- Update of 06-7a-08/0x01 (GLK-R R0) microcode from revision 0x16 up
|
||||
to 0x18;
|
||||
- Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x78
|
||||
up to 0xa0;
|
||||
- Update of 06-a6-00/0x80 (CML-U 6+2 A0) microcode from revision 0xca
|
||||
up to 0xe0.
|
||||
|
||||
* Fri Aug 21 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20200609-3
|
||||
- Add README file to the documentation directory.
|
||||
- Add publicly-sourced codenames list to supply to gen_provides.sh; update
|
||||
the latter to handle the somewhat different format.
|
||||
- Add SUMMARY.intel-ucode file containing metadata information from
|
||||
the microcode file headers.
|
||||
|
||||
* Mon Jun 22 2020 Eugene Syromiatnikov <esyr@redhat.com> - 4:20200609-2
|
||||
- Blacklist latest microcode revision for 06-[89]e-0x CPUs (AML-Y,
|
||||
CFL-H/S/U/Xeon E, CML-Y, KBL-G/H/S/X/U/Y/Xeon E3 v6, WHL-U) on Dell systems,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user