diff --git a/.gitignore b/.gitignore
index ecf0786..2afa82f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,6 +1,6 @@
 /microcode-20190918.tar.gz
 /microcode-20191115.tar.gz
-/microcode-20240910.tar.gz
+/microcode-20241112.tar.gz
 /06-2d-07
 /06-4e-03
 /06-55-04
diff --git a/microcode_ctl.spec b/microcode_ctl.spec
index 2e684c2..2608bc7 100644
--- a/microcode_ctl.spec
+++ b/microcode_ctl.spec
@@ -1,4 +1,4 @@
-%define intel_ucode_version 20240910
+%define intel_ucode_version 20241112
 
 %define caveat_dir %{_datarootdir}/microcode_ctl/ucode_with_caveats
 %define microcode_ctl_libexec %{_libexecdir}/microcode_ctl
@@ -552,9 +552,122 @@ rm -rf %{buildroot}
 
 
 %changelog
+* Tue Nov 19 2024 Eugene Syromiatnikov <esyr@redhat.com> - 4:20241112-1
+- Update Intel CPU microcode to microcode-20241112 release, addresses
+  CVE-2024-21820, CVE-2024-21853, CVE-2024-23918, CVE-2024-23984 (RHEL-67336):
+  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode from revision 0x2b0005c0
+    up to 0x2b000603;
+  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-05) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode from revision 0x2b0005c0
+    up to 0x2b000603;
+  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-06) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode from revision
+    0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode (in
+    intel-ucode/06-8f-07) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-04/0x87 (SPR-SP E0/S1) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-05/0x87 (SPR-SP E2) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-06/0x87 (SPR-SP E3) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-07/0x87 (SPR-SP E4/S2) microcode (in
+    intel-ucode/06-8f-08) from revision 0x2b0005c0 up to 0x2b000603;
+  - Update of 06-8f-08/0x87 (SPR-SP E5/S3) microcode from revision
+    0x2b0005c0 up to 0x2b000603;
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode from revision
+    0x36 up to 0x37;
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
+    intel-ucode/06-97-02) from revision 0x36 up to 0x37;
+  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
+    from revision 0x36 up to 0x37;
+  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-02)
+    from revision 0x36 up to 0x37;
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
+    intel-ucode/06-97-05) from revision 0x36 up to 0x37;
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode from revision 0x36
+    up to 0x37;
+  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
+    from revision 0x36 up to 0x37;
+  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-97-05)
+    from revision 0x36 up to 0x37;
+  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode from revision
+    0x434 up to 0x435;
+  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode (in
+    intel-ucode/06-9a-03) from revision 0x434 up to 0x435;
+  - Update of 06-9a-03/0x80 (ADL-P 6+8/U 9W L0/R0) microcode (in
+    intel-ucode/06-9a-04) from revision 0x434 up to 0x435;
+  - Update of 06-9a-04/0x80 (ADL-P 2+8 R0) microcode from revision 0x434
+    up to 0x435;
+  - Update of 06-aa-04/0xe6 (MTL-H/U C0) microcode from revision 0x1f
+    up to 0x20;
+  - Update of 06-b7-01/0x32 (RPL-S B0) microcode from revision 0x129 up
+    to 0x12b;
+  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode from revision
+    0x4122 up to 0x4123;
+  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
+    intel-ucode/06-ba-02) from revision 0x4122 up to 0x4123;
+  - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-02) from
+    revision 0x4122 up to 0x4123;
+  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
+    intel-ucode/06-ba-03) from revision 0x4122 up to 0x4123;
+  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode from revision 0x4122
+    up to 0x4123;
+  - Update of 06-ba-08/0xe0 microcode (in intel-ucode/06-ba-03) from
+    revision 0x4122 up to 0x4123;
+  - Update of 06-ba-02/0xe0 (RPL-H 6+8/P 6+8 J0) microcode (in
+    intel-ucode/06-ba-08) from revision 0x4122 up to 0x4123;
+  - Update of 06-ba-03/0xe0 (RPL-U 2+8 Q0) microcode (in
+    intel-ucode/06-ba-08) from revision 0x4122 up to 0x4123;
+  - Update of 06-ba-08/0xe0 microcode from revision 0x4122 up to 0x4123;
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
+    intel-ucode/06-bf-02) from revision 0x36 up to 0x37;
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
+    intel-ucode/06-bf-02) from revision 0x36 up to 0x37;
+  - Update of 06-bf-02/0x07 (ADL C0) microcode from revision 0x36 up
+    to 0x37;
+  - Update of 06-bf-05/0x07 (ADL C0) microcode (in intel-ucode/06-bf-02)
+    from revision 0x36 up to 0x37;
+  - Update of 06-97-02/0x07 (ADL-HX/S 8+8 C0) microcode (in
+    intel-ucode/06-bf-05) from revision 0x36 up to 0x37;
+  - Update of 06-97-05/0x07 (ADL-S 6+0 K0) microcode (in
+    intel-ucode/06-bf-05) from revision 0x36 up to 0x37;
+  - Update of 06-bf-02/0x07 (ADL C0) microcode (in intel-ucode/06-bf-05)
+    from revision 0x36 up to 0x37;
+  - Update of 06-bf-05/0x07 (ADL C0) microcode from revision 0x36 up
+    to 0x37;
+  - Update of 06-cf-01/0x87 (EMR-SP A0) microcode from revision 0x21000230
+    up to 0x21000283;
+  - Update of 06-cf-02/0x87 (EMR-SP A1) microcode (in
+    intel-ucode/06-cf-01) from revision 0x21000230 up to 0x21000283;
+  - Update of 06-cf-01/0x87 (EMR-SP A0) microcode (in
+    intel-ucode/06-cf-02) from revision 0x21000230 up to 0x21000283;
+  - Update of 06-cf-02/0x87 (EMR-SP A1) microcode from revision 0x21000230
+    up to 0x21000283.
+
 * Mon Sep 23 2024 Eugene Syromiatnikov <esyr@redhat.com> - 4:20240910-1
 - Update Intel CPU microcode to microcode-20240910 release, addresses
-- Addresses CVE-2024-23984, CVE-2024-24853, CVE-2024-24968, CVE-2024-24980,
+  CVE-2024-23984, CVE-2024-24853, CVE-2024-24968, CVE-2024-24980,
   CVE-2024-25939 (RHEL-58057):
   - Update of 06-8c-01/0x80 (TGL-UP3/UP4 B1) microcode (in
     intel-06-8c-01/intel-ucode/06-8c-01) from revision 0xb6 up to 0xb8;
diff --git a/sources b/sources
index b78a6cf..a25e7f8 100644
--- a/sources
+++ b/sources
@@ -1,6 +1,6 @@
 SHA512 (microcode-20190918.tar.gz) = 82e5212238d3e35470d139240d9157877ac252725598ec31bfe1763755681539a4ecdf24e04c4e4270215578a9ca3c063c8fc353accf99999c3d4ac2780a6e0c
 SHA512 (microcode-20191115.tar.gz) = 11014c16bde83ac290bc75e458242f5e64b8dffd49de2e938f61f4a09979cd5e80dd1a85d2ccbac067e4398dc3d93ef3583e4aa9b2e545ba46d26e65ec1e2881
-SHA512 (microcode-20240910.tar.gz) = d996de4f045df33f4eb1a1dabfb2f55bd8941e8dc16241d7a6c361216f4b87b88c34ba57c88ee4d4b7b3cf2b3fac937c43806191681df031fa3d5cdd677a86fe
+SHA512 (microcode-20241112.tar.gz) = de4ddb0a77e17a4a5b6789537cf71db9ab884c795ef5c77b17d3392fda0fbb4d860cc27bcdbd7512d9412d6f934e6771e889be262b20e77433e0f72d3b6cf1f0
 SHA512 (06-2d-07) = 631ec8ad8ad3c9b32d9569689f673010d26c13c7cc377d66b8fc5150de52485076d1514ba867dfa4f468889a31d6701cd8a0789d465ad069d98c8ea0f5bd3204
 SHA512 (06-4e-03) = 248066b521bf512b5d8e4a8c7e921464ce52169c954d6e4ca580d8c172cd789519e22b4cf56c212e452b4191741f0202019f7061d322c9433b5af9ce5413b567
 SHA512 (06-55-04) = db2783cd62680510a7105e7c3fd9d5fffac6a33159ba811f4669f8afb9a5badde4c009bf1868e6a53eb3ac2286812404127bcd45fcbc65fe004788e25ae3e222