From 7b268cc6aef649c5700812b8a3c273de6345750d Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@fedoraproject.org>
Date: Thu, 26 Mar 2009 03:33:21 +0000
Subject: [PATCH] - fix r200 fbo + vram sizing bug

---
 mesa.spec            |   7 +-
 radeon-rewrite.patch | 489 +++++++++++++++++++++++--------------------
 2 files changed, 263 insertions(+), 233 deletions(-)

diff --git a/mesa.spec b/mesa.spec
index bb9363f..a732bd7 100644
--- a/mesa.spec
+++ b/mesa.spec
@@ -20,7 +20,7 @@
 Summary: Mesa graphics libraries
 Name: mesa
 Version: 7.5
-Release: 0.3%{?dist}
+Release: 0.4%{?dist}
 License: MIT
 Group: System Environment/Libraries
 URL: http://www.mesa3d.org
@@ -75,7 +75,7 @@ Requires(post): /sbin/ldconfig
 Requires(postun): /sbin/ldconfig
 Provides: libGL
 %if %{with_dri}
-Requires: libdrm >= 2.4.3
+Requires: libdrm >= 2.4.5-1
 Requires: mesa-dri-drivers%{?_isa} = %{version}-%{release}
 Conflicts: xorg-x11-server-Xorg < 1.4.99.901-14
 %endif
@@ -429,6 +429,9 @@ rm -rf $RPM_BUILD_ROOT
 %{_libdir}/mesa-demos-data
 
 %changelog
+* Thu Mar 26 2009 Dave Airlie <airlied@redhat.com> 7.5-0.4
+- fix r200 fbo + vram sizing bug
+
 * Tue Mar 24 2009 Dave Airlie <airlied@redhat.com> 7.5-0.3
 - radeon-rewrite: add FBO support for radeon on KMS/DRI2
 
diff --git a/radeon-rewrite.patch b/radeon-rewrite.patch
index 1d97d50..ec33607 100644
--- a/radeon-rewrite.patch
+++ b/radeon-rewrite.patch
@@ -39,7 +39,7 @@ index 46070fd..4164d37 100644
      if test "$x11_pkgconfig" = yes; then
          # add xcb modules if necessary
 diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile
-index e9144ac..e593ed9 100644
+index e9144ac..6a246ed 100644
 --- a/src/mesa/drivers/dri/r200/Makefile
 +++ b/src/mesa/drivers/dri/r200/Makefile
 @@ -3,6 +3,8 @@
@@ -51,7 +51,7 @@ index e9144ac..e593ed9 100644
  LIBNAME = r200_dri.so
  
  MINIGLX_SOURCES = server/radeon_dri.c 
-@@ -11,25 +13,35 @@ ifeq ($(USING_EGL), 1)
+@@ -11,25 +13,36 @@ ifeq ($(USING_EGL), 1)
  EGL_SOURCES = server/radeon_egl.c
  endif
  
@@ -64,7 +64,8 @@ index e9144ac..e593ed9 100644
 +	radeon_bo_legacy.c \
 +	radeon_cs_legacy.c \
 +	radeon_mipmap_tree.c \
-+	radeon_span.c
++	radeon_span.c \
++	radeon_fbo.c
 +
 +
  DRIVER_SOURCES = r200_context.c \
@@ -91,7 +92,7 @@ index e9144ac..e593ed9 100644
  
  C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES)
  
-@@ -48,7 +60,29 @@ SYMLINKS = \
+@@ -48,7 +61,30 @@ SYMLINKS = \
  COMMON_SYMLINKS = \
  	radeon_chipset.h \
  	radeon_screen.c \
@@ -116,14 +117,15 @@ index e9144ac..e593ed9 100644
 +	radeon_texture.c \
 +	radeon_texture.h \
 +	radeon_dma.c \
-+	radeon_dma.h
++	radeon_dma.h \
++	radeon_fbo.c
 +
 +DRI_LIB_DEPS += $(RADEON_LDFLAGS)
  
  ##### TARGETS #####
  
 diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
-index e163377..ae31bcb 100644
+index e163377..83375c8 100644
 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c
 +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
 @@ -38,6 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -338,10 +340,11 @@ index e163377..ae31bcb 100644
  }
  
  /* Fire a section of the retained (indexed_verts) buffer as a regular
-@@ -209,50 +113,81 @@ void r200EmitVbufPrim( r200ContextPtr rmesa,
+@@ -208,51 +112,80 @@ void r200EmitVbufPrim( r200ContextPtr rmesa,
+                        GLuint primitive,
                         GLuint vertex_nr )
  {
-    drm_radeon_cmd_header_t *cmd;
+-   drm_radeon_cmd_header_t *cmd;
 +   BATCH_LOCALS(&rmesa->radeon);
  
     assert(!(primitive & R200_VF_PRIM_WALK_IND));
@@ -406,9 +409,9 @@ index e163377..ae31bcb 100644
 +void r200FlushElts(GLcontext *ctx)
  {
 -   int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start);
-+  r200ContextPtr rmesa = R200_CONTEXT(ctx);
-    int dwords;
+-   int dwords;
 -   int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 12)) / 2;
++   r200ContextPtr rmesa = R200_CONTEXT(ctx);
 +   int nr, elt_used = rmesa->tcl.elt_used;
  
     if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS))
@@ -444,7 +447,7 @@ index e163377..ae31bcb 100644
     }
  }
  
-@@ -261,7 +196,6 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
+@@ -261,7 +194,6 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
  				    GLuint primitive,
  				    GLuint min_nr )
  {
@@ -452,7 +455,7 @@ index e163377..ae31bcb 100644
     GLushort *retval;
  
     if (R200_DEBUG & DEBUG_IOCTL)
-@@ -269,30 +203,25 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
+@@ -269,30 +201,25 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
  
     assert((primitive & R200_VF_PRIM_WALK_IND));
     
@@ -467,13 +470,13 @@ index e163377..ae31bcb 100644
 -	       R200_VF_PRIM_WALK_IND |
 -	       R200_VF_COLOR_ORDER_RGBA);
 +   radeonEmitState(&rmesa->radeon);
- 
++
 +   rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
 +					  0, R200_ELT_BUF_SZ, 4,
 +					  RADEON_GEM_DOMAIN_GTT, 0);
 +   rmesa->tcl.elt_dma_offset = 0;
 +   rmesa->tcl.elt_used = min_nr * 2;
-+
+ 
 +   radeon_bo_map(rmesa->tcl.elt_dma_bo, 1);
 +   retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset;
     
@@ -483,13 +486,13 @@ index e163377..ae31bcb 100644
 -      fprintf(stderr, "%s: header 0x%x prim %x \n",
 -	      __FUNCTION__,
 -	      cmd[1].i, primitive);
--
--   assert(!rmesa->dma.flush);
--   rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
--   rmesa->dma.flush = r200FlushElts;
 +      fprintf(stderr, "%s: header prim %x \n",
 +	      __FUNCTION__, primitive);
  
+-   assert(!rmesa->dma.flush);
+-   rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
+-   rmesa->dma.flush = r200FlushElts;
+-
 -   rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf;
 +   assert(!rmesa->radeon.dma.flush);
 +   rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
@@ -497,7 +500,7 @@ index e163377..ae31bcb 100644
  
     return retval;
  }
-@@ -300,129 +229,130 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
+@@ -300,129 +227,119 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
  
  
  void r200EmitVertexAOS( r200ContextPtr rmesa,
@@ -663,9 +666,8 @@ index e163377..ae31bcb 100644
 -      for (i = 0 ; i < sz ; i++)
 -	 fprintf(stderr, "   %d: %x\n", i, tmp[i]);
 -   }
-+   END_BATCH();
- }
- 
+-}
+-
 -void r200EmitBlit( r200ContextPtr rmesa,
 -		   GLuint color_fmt,
 -		   GLuint src_pitch,
@@ -675,11 +677,9 @@ index e163377..ae31bcb 100644
 -		   GLint srcx, GLint srcy,
 -		   GLint dstx, GLint dsty,
 -		   GLuint w, GLuint h )
-+void r200FireAOS(r200ContextPtr rmesa, int vertex_count, int type)
- {
+-{
 -   drm_radeon_cmd_header_t *cmd;
-+	BATCH_LOCALS(&rmesa->radeon);
- 
+-
 -   if (R200_DEBUG & DEBUG_IOCTL)
 -      fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
 -	      __FUNCTION__, 
@@ -715,12 +715,8 @@ index e163377..ae31bcb 100644
 -   cmd[5].i = (srcx << 16) | srcy;
 -   cmd[6].i = (dstx << 16) | dsty; /* dst */
 -   cmd[7].i = (w << 16) | h;
-+	BEGIN_BATCH(3);
-+	OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_VBUF_2, 0);
-+	OUT_BATCH(R200_VF_PRIM_WALK_LIST | (vertex_count << 16) | type);
-+	END_BATCH();
- }
- 
+-}
+-
 -
 -void r200EmitWait( r200ContextPtr rmesa, GLuint flags )
 -{
@@ -733,9 +729,10 @@ index e163377..ae31bcb 100644
 -   cmd[0].i = 0;
 -   cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
 -   cmd[0].wait.flags = flags;
--}
++   END_BATCH();
+ }
 diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
-index c067515..d3898d0 100644
+index c067515..564e168 100644
 --- a/src/mesa/drivers/dri/r200/r200_context.c
 +++ b/src/mesa/drivers/dri/r200/r200_context.c
 @@ -54,7 +54,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -813,7 +810,7 @@ index c067515..d3898d0 100644
  extern const struct tnl_pipeline_stage _r200_render_stage;
  extern const struct tnl_pipeline_stage _r200_tcl_stage;
  
-@@ -234,6 +239,40 @@ static const struct dri_debug_control debug_control[] =
+@@ -234,6 +239,39 @@ static const struct dri_debug_control debug_control[] =
      { NULL,    0 }
  };
  
@@ -821,7 +818,6 @@ index c067515..d3898d0 100644
 +{
 +   r200ContextPtr rmesa = (r200ContextPtr)radeon;
 +   drm_radeon_sarea_t *sarea = radeon->sarea;
-+   int i;
 +
 +   R200_STATECHANGE( rmesa, ctx );
 +   if (rmesa->radeon.sarea->tiling_enabled) {
@@ -854,7 +850,7 @@ index c067515..d3898d0 100644
  
  /* Create the device specific rendering context.
   */
-@@ -245,9 +284,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
+@@ -245,9 +283,9 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
     radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
     struct dd_function_table functions;
     r200ContextPtr rmesa;
@@ -866,7 +862,7 @@ index c067515..d3898d0 100644
  
     assert(glVisual);
     assert(driContextPriv);
-@@ -257,7 +296,8 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
+@@ -257,7 +295,8 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
     rmesa = (r200ContextPtr) CALLOC( sizeof(*rmesa) );
     if ( !rmesa )
        return GL_FALSE;
@@ -876,7 +872,7 @@ index c067515..d3898d0 100644
     /* init exp fog table data */
     r200InitStaticFogData();
  
-@@ -265,12 +305,12 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
+@@ -265,12 +304,12 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
      * Do this here so that initialMaxAnisotropy is set before we create
      * the default textures.
      */
@@ -893,7 +889,7 @@ index c067515..d3898d0 100644
        if ( sPriv->drm_version.minor < 13 )
  	 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
  			  "disabling.\n", sPriv->drm_version.minor );
-@@ -291,59 +331,15 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
+@@ -291,59 +330,15 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
     r200InitTextureFuncs(&functions);
     r200InitShaderFuncs(&functions); 
  
@@ -960,7 +956,7 @@ index c067515..d3898d0 100644
  
     /* Set the maximum texture size small enough that we can guarentee that
      * all texture units can bind a maximal texture and have all of them in
-@@ -351,29 +347,13 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
+@@ -351,29 +346,13 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
      * setting allow larger textures.
      */
  
@@ -993,7 +989,7 @@ index c067515..d3898d0 100644
  
     ctx->Const.MaxTextureMaxAnisotropy = 16.0;
  
-@@ -383,7 +363,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
+@@ -383,7 +362,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
     ctx->Const.MinPointSizeAA = 1.0;
     ctx->Const.MaxPointSizeAA = 1.0;
     ctx->Const.PointSizeGranularity = 0.0625;
@@ -1002,7 +998,7 @@ index c067515..d3898d0 100644
        ctx->Const.MaxPointSize = 2047.0;
     else
        ctx->Const.MaxPointSize = 1.0;
-@@ -439,32 +419,35 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
+@@ -439,32 +418,35 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
     _math_matrix_set_identity( &rmesa->tmpmat );
  
     driInitExtensions( ctx, card_extensions, GL_TRUE );
@@ -1047,7 +1043,7 @@ index c067515..d3898d0 100644
        driInitExtensions( ctx, point_extensions, GL_FALSE );
  #if 0
     r200InitDriverFuncs( ctx );
-@@ -474,33 +457,16 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
+@@ -474,33 +456,16 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
  #endif
     /* plug in a few more device driver functions */
     /* XXX these should really go right after _mesa_init_driver_functions() */
@@ -1083,7 +1079,7 @@ index c067515..d3898d0 100644
  #if DO_DEBUG
     R200_DEBUG  = driParseDebugString( getenv( "R200_DEBUG" ),
  				      debug_control );
-@@ -508,18 +474,18 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
+@@ -508,18 +473,18 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual,
  				      debug_control );
  #endif
  
@@ -1108,7 +1104,7 @@ index c067515..d3898d0 100644
     }
  
     return GL_TRUE;
-@@ -538,55 +504,33 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
+@@ -538,55 +503,33 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
  
     /* check if we're deleting the currently bound context */
     if (rmesa == current) {
@@ -1141,17 +1137,14 @@ index c067515..d3898d0 100644
 -      if (rmesa->dma.current.buf) {
 -	 r200ReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
 -	 r200FlushCmdBuf( rmesa, __FUNCTION__ );
-+      if (rmesa->radeon.dma.current) {
-+	 radeonReleaseDmaRegion( &rmesa->radeon );
-+	 rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
-       }
- 
+-      }
+-
 -      if (rmesa->state.scissor.pClipRects) {
 -	 FREE(rmesa->state.scissor.pClipRects);
 -	 rmesa->state.scissor.pClipRects = NULL;
-+      if (rmesa->radeon.state.scissor.pClipRects) {
-+	 FREE(rmesa->radeon.state.scissor.pClipRects);
-+	 rmesa->radeon.state.scissor.pClipRects = NULL;
++      if (rmesa->radeon.dma.current) {
++	 radeonReleaseDmaRegion( &rmesa->radeon );
++	 rcommonFlushCmdBuf( &rmesa->radeon, __FUNCTION__ );
        }
  
 -      if ( release_texture_heaps ) {
@@ -1166,8 +1159,11 @@ index c067515..d3898d0 100644
 -         }
 -
 -	 assert( is_empty_list( & rmesa->swapped ) );
--      }
--
++      if (rmesa->radeon.state.scissor.pClipRects) {
++	 FREE(rmesa->radeon.state.scissor.pClipRects);
++	 rmesa->radeon.state.scissor.pClipRects = NULL;
+       }
+ 
 -      /* free the Mesa context */
 -      rmesa->glCtx->DriverCtx = NULL;
 -      _mesa_destroy_context( rmesa->glCtx );
@@ -1178,7 +1174,7 @@ index c067515..d3898d0 100644
  
        FREE( rmesa );
     }
-@@ -594,107 +538,6 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
+@@ -594,107 +537,6 @@ void r200DestroyContext( __DRIcontextPrivate *driContextPriv )
  
  
  
@@ -1286,7 +1282,7 @@ index c067515..d3898d0 100644
  /* Force the context `c' to be unbound from its buffer.
   */
  GLboolean
-@@ -703,7 +546,7 @@ r200UnbindContext( __DRIcontextPrivate *driContextPriv )
+@@ -703,7 +545,7 @@ r200UnbindContext( __DRIcontextPrivate *driContextPriv )
     r200ContextPtr rmesa = (r200ContextPtr) driContextPriv->driverPrivate;
  
     if (R200_DEBUG & DEBUG_DRI)
@@ -1902,7 +1898,7 @@ index d514b28..85c1b7b 100644
     }
  }
 diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c
-index 0741e57..ccb5620 100644
+index 0741e57..b8e40da 100644
 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c
 +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c
 @@ -41,6 +41,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -2496,10 +2492,7 @@ index 0741e57..ccb5620 100644
 -      if ( dPriv->numClipRects == 0 ) 
 -	 return;
 -   }
-+   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
-+   GLint cx, cy, cw, ch, ret;
-+   GLuint i;
- 
+-
 -   r200Flush( ctx );
 -
 -   if ( mask & BUFFER_BIT_FRONT_LEFT ) {
@@ -2532,7 +2525,10 @@ index 0741e57..ccb5620 100644
 -
 -   if ( !flags ) 
 -      return;
--
++   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
++   GLint cx, cy, cw, ch, ret;
++   GLuint i;
+ 
 -   if (rmesa->using_hyperz) {
 -      flags |= RADEON_USE_COMP_ZBUF;
 -/*      if (rmesa->r200Screen->chip_family == CHIP_FAMILY_R200)
@@ -2591,13 +2587,13 @@ index 0741e57..ccb5620 100644
 -   r200FlushCmdBufLocked( rmesa, __FUNCTION__ );
 +   rcommonFlushCmdBufLocked( &rmesa->radeon, __FUNCTION__ );
 +
- 
++
 +  /* compute region after locking: */
 +   cx = ctx->DrawBuffer->_Xmin;
 +   cy = ctx->DrawBuffer->_Ymin;
 +   cw = ctx->DrawBuffer->_Xmax - cx;
 +   ch = ctx->DrawBuffer->_Ymax - cy;
-+
+ 
 +   /* Flip top to bottom */
 +   cx += dPriv->x;
 +   cy  = dPriv->y + dPriv->h - cy - ch;
@@ -2632,7 +2628,7 @@ index 0741e57..ccb5620 100644
        for ( ; n >= 0 ; n-- ) {
  	 depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1;
  	 depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1;
-@@ -774,83 +172,91 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
+@@ -774,83 +172,90 @@ static void r200Clear( GLcontext *ctx, GLbitfield mask )
  	 depth_boxes[n].f[CLEAR_DEPTH] = ctx->Depth.Clear;
        }
  
@@ -2680,7 +2676,6 @@ index 0741e57..ccb5620 100644
 +   __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable;
 +   GLuint flags = 0;
 +   GLuint color_mask = 0;
-+   GLint ret;
 +   GLuint orig_mask = mask;
  
 +   if ( R200_DEBUG & DEBUG_IOCTL ) {
@@ -2780,7 +2775,7 @@ index 0741e57..ccb5620 100644
  
  /* This version of AllocateMemoryMESA allocates only GART memory, and
   * only does so after the point at which the driver has been
-@@ -875,7 +281,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size,
+@@ -875,7 +280,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size,
        fprintf(stderr, "%s sz %d %f/%f/%f\n", __FUNCTION__, size, readfreq, 
  	      writefreq, priority);
  
@@ -2789,7 +2784,7 @@ index 0741e57..ccb5620 100644
        return NULL;
  
     if (getenv("R200_NO_ALLOC"))
-@@ -886,7 +292,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size,
+@@ -886,7 +291,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size,
     alloc.size = size;
     alloc.region_offset = &region_offset;
  
@@ -2798,7 +2793,7 @@ index 0741e57..ccb5620 100644
  			      DRM_RADEON_ALLOC,
  			      &alloc, sizeof(alloc));
     
-@@ -896,7 +302,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size,
+@@ -896,7 +301,7 @@ void *r200AllocateMemoryMESA(__DRIscreen *screen, GLsizei size,
     }
     
     {
@@ -2807,7 +2802,7 @@ index 0741e57..ccb5620 100644
        return (void *)(region_start + region_offset);
     }
  }
-@@ -914,24 +320,24 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer)
+@@ -914,24 +319,24 @@ void r200FreeMemoryMESA(__DRIscreen *screen, GLvoid *pointer)
     if (R200_DEBUG & DEBUG_IOCTL)
        fprintf(stderr, "%s %p\n", __FUNCTION__, pointer);
  
@@ -2837,7 +2832,7 @@ index 0741e57..ccb5620 100644
  			  DRM_RADEON_FREE,
  			  &memfree, sizeof(memfree));
     
-@@ -956,16 +362,16 @@ GLuint r200GetMemoryOffsetMESA(__DRIscreen *screen, const GLvoid *pointer)
+@@ -956,16 +361,16 @@ GLuint r200GetMemoryOffsetMESA(__DRIscreen *screen, const GLvoid *pointer)
  
     card_offset = r200GartOffsetFromVirtual( rmesa, pointer );
  
@@ -2857,7 +2852,7 @@ index 0741e57..ccb5620 100644
  
     if (R200_DEBUG & DEBUG_IOCTL)
        fprintf(stderr, "r200IsGartMemory( %p ) : %d\n", pointer, valid );
-@@ -976,12 +382,12 @@ GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer,
+@@ -976,12 +381,12 @@ GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer,
  
  GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer )
  {
@@ -2873,7 +2868,7 @@ index 0741e57..ccb5620 100644
  }
  
  
-@@ -989,7 +395,7 @@ GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer )
+@@ -989,7 +394,7 @@ GLuint r200GartOffsetFromVirtual( r200ContextPtr rmesa, const GLvoid *pointer )
  void r200InitIoctlFuncs( struct dd_function_table *functions )
  {
      functions->Clear = r200Clear;
@@ -8337,7 +8332,7 @@ index 3b81ac0..0000000
 -   return 0;
 -}
 diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c
-index 0ad5651..2212fe6 100644
+index 0ad5651..72b7f3d 100644
 --- a/src/mesa/drivers/dri/r200/r200_texstate.c
 +++ b/src/mesa/drivers/dri/r200/r200_texstate.c
 @@ -37,9 +37,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -8636,7 +8631,7 @@ index 0ad5651..2212fe6 100644
  	t->pp_txpitch = pitch - 32;
  
  	switch (depth) {
-@@ -1014,6 +765,122 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
+@@ -1014,6 +765,123 @@ void r200SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
  	}
  }
  
@@ -8711,6 +8706,7 @@ index 0ad5651..2212fe6 100644
 +	fprintf(stderr,"settexbuf %d %dx%d@%d\n", rb->pitch, rb->width, rb->height, rb->cpp);
 +	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
 +				   rb->width, rb->height, 1, 0, rb->cpp);
++	texImage->RowStride = rb->pitch / rb->cpp;
 +	texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx,
 +							internalFormat,
 +							type, format);
@@ -8759,7 +8755,7 @@ index 0ad5651..2212fe6 100644
  #define REF_COLOR 1
  #define REF_ALPHA 2
  
-@@ -1207,12 +1074,41 @@ static GLboolean r200UpdateAllTexEnv( GLcontext *ctx )
+@@ -1207,12 +1075,41 @@ static GLboolean r200UpdateAllTexEnv( GLcontext *ctx )
                                  R200_VOLUME_FILTER_MASK)
  
  
@@ -8803,7 +8799,7 @@ index 0ad5651..2212fe6 100644
  
     R200_STATECHANGE( rmesa, tex[unit] );
  
-@@ -1225,36 +1121,21 @@ static void import_tex_obj_state( r200ContextPtr rmesa,
+@@ -1225,36 +1122,21 @@ static void import_tex_obj_state( r200ContextPtr rmesa,
     cmd[TEX_PP_TXSIZE] = texobj->pp_txsize; /* NPOT only! */
     cmd[TEX_PP_TXPITCH] = texobj->pp_txpitch; /* NPOT only! */
     cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
@@ -8843,7 +8839,7 @@ index 0ad5651..2212fe6 100644
  static void set_texgen_matrix( r200ContextPtr rmesa, 
  			       GLuint unit,
  			       const GLfloat *s_plane,
-@@ -1377,7 +1258,6 @@ static GLboolean r200_validate_texgen( GLcontext *ctx, GLuint unit )
+@@ -1377,7 +1259,6 @@ static GLboolean r200_validate_texgen( GLcontext *ctx, GLuint unit )
     } else {
        tgcm |= R200_TEXGEN_COMP_T << (unit * 4);
     }
@@ -8851,7 +8847,7 @@ index 0ad5651..2212fe6 100644
     if (texUnit->TexGenEnabled & R_BIT) {
        if (texUnit->GenR.Mode != mode)
  	 mixed_fallback = GL_TRUE;
-@@ -1517,52 +1397,6 @@ static GLboolean r200_validate_texgen( GLcontext *ctx, GLuint unit )
+@@ -1517,52 +1398,6 @@ static GLboolean r200_validate_texgen( GLcontext *ctx, GLuint unit )
     return GL_TRUE;
  }
  
@@ -8904,7 +8900,7 @@ index 0ad5651..2212fe6 100644
  void set_re_cntl_d3d( GLcontext *ctx, int unit, GLboolean use_d3d )
  {
     r200ContextPtr rmesa = R200_CONTEXT(ctx);
-@@ -1579,237 +1413,169 @@ void set_re_cntl_d3d( GLcontext *ctx, int unit, GLboolean use_d3d )
+@@ -1579,237 +1414,169 @@ void set_re_cntl_d3d( GLcontext *ctx, int unit, GLboolean use_d3d )
     }
  }
  
@@ -9266,7 +9262,7 @@ index 0ad5651..2212fe6 100644
  }
  
  
-@@ -1850,11 +1616,11 @@ void r200UpdateTextureState( GLcontext *ctx )
+@@ -1850,11 +1617,11 @@ void r200UpdateTextureState( GLcontext *ctx )
  
     FALLBACK( rmesa, R200_FALLBACK_TEXTURE, !ok );
  
@@ -9280,7 +9276,7 @@ index 0ad5651..2212fe6 100644
  
        /*
         * T0 hang workaround -------------
-@@ -1867,7 +1633,7 @@ void r200UpdateTextureState( GLcontext *ctx )
+@@ -1867,7 +1634,7 @@ void r200UpdateTextureState( GLcontext *ctx )
  	 R200_STATECHANGE(rmesa, tex[1]);
  	 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_1_ENABLE;
  	 if (!(rmesa->hw.cst.cmd[CST_PP_CNTL_X] & R200_PPX_TEX_1_ENABLE))
@@ -13738,7 +13734,7 @@ index 8f1a663..ed552d0 100644
  #       define R300_TXO_ENDIAN_NO_SWAP           (0 << 0)
  #       define R300_TXO_ENDIAN_BYTE_SWAP         (1 << 0)
 diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c
-index 16ce4a1..402d2d7 100644
+index 16ce4a1..829d088 100644
 --- a/src/mesa/drivers/dri/r300/r300_render.c
 +++ b/src/mesa/drivers/dri/r300/r300_render.c
 @@ -66,8 +66,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -14035,7 +14031,17 @@ index 16ce4a1..402d2d7 100644
  	/* Do we need to use new-style shaders?
  	 * Also is there a better way to do this? */
  	if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
-@@ -432,6 +512,9 @@ static GLboolean r300RunTCLRender(GLcontext * ctx,
+@@ -410,6 +490,9 @@ static GLboolean r300RunNonTCLRender(GLcontext * ctx,
+ 	if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
+  	        return GL_TRUE;
+ 
++	if (!r300ValidateBuffers(ctx))
++	    return GL_TRUE;
++	
+ 	return r300RunRender(ctx, stage);
+ }
+ 
+@@ -432,6 +515,9 @@ static GLboolean r300RunTCLRender(GLcontext * ctx,
  		return GL_TRUE;
  	}
  
@@ -14046,10 +14052,18 @@ index 16ce4a1..402d2d7 100644
  
  	vp = (struct r300_vertex_program *)CURRENT_VERTEX_SHADER(ctx);
 diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c
-index 8095538..f49b43c 100644
+index 8095538..6796d36 100644
 --- a/src/mesa/drivers/dri/r300/r300_state.c
 +++ b/src/mesa/drivers/dri/r300/r300_state.c
-@@ -53,8 +53,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+@@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ #include "main/macros.h"
+ #include "main/context.h"
+ #include "main/dd.h"
++#include "main/framebuffer.h"
+ #include "main/simple_list.h"
+ #include "main/api_arrayelt.h"
+ #include "main/texformat.h"
+@@ -53,8 +54,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  #include "vbo/vbo.h"
  #include "tnl/tnl.h"
  
@@ -14058,7 +14072,7 @@ index 8095538..f49b43c 100644
  #include "r300_context.h"
  #include "r300_ioctl.h"
  #include "r300_state.h"
-@@ -589,8 +587,14 @@ static void r300SetDepthState(GLcontext * ctx)
+@@ -589,8 +588,14 @@ static void r300SetDepthState(GLcontext * ctx)
  static void r300SetStencilState(GLcontext * ctx, GLboolean state)
  {
  	r300ContextPtr r300 = R300_CONTEXT(ctx);
@@ -14074,7 +14088,7 @@ index 8095538..f49b43c 100644
  		R300_STATECHANGE(r300, zs);
  		if (state) {
  			r300->hw.zs.cmd[R300_ZS_CNTL_0] |=
-@@ -935,15 +939,25 @@ static void r300UpdateWindow(GLcontext * ctx)
+@@ -935,15 +940,25 @@ static void r300UpdateWindow(GLcontext * ctx)
  	GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
  	GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
  	const GLfloat *v = ctx->Viewport._WindowMap.m;
@@ -14105,7 +14119,7 @@ index 8095538..f49b43c 100644
  	R300_STATECHANGE(rmesa, vpt);
  
  	rmesa->hw.vpt.cmd[R300_VPT_XSCALE] = r300PackFloat32(sx);
-@@ -962,6 +976,8 @@ static void r300Viewport(GLcontext * ctx, GLint x, GLint y,
+@@ -962,6 +977,8 @@ static void r300Viewport(GLcontext * ctx, GLint x, GLint y,
  	 * values, or keep the originals hanging around.
  	 */
  	r300UpdateWindow(ctx);
@@ -14114,7 +14128,7 @@ index 8095538..f49b43c 100644
  }
  
  static void r300DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval)
-@@ -994,64 +1010,6 @@ void r300UpdateViewportOffset(GLcontext * ctx)
+@@ -994,64 +1011,6 @@ void r300UpdateViewportOffset(GLcontext * ctx)
  	radeonUpdateScissor(ctx);
  }
  
@@ -14179,7 +14193,7 @@ index 8095538..f49b43c 100644
  static void
  r300FetchStateParameter(GLcontext * ctx,
  			const gl_state_index state[STATE_LENGTH],
-@@ -1269,7 +1227,8 @@ static void r300SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings)
+@@ -1269,7 +1228,8 @@ static void r300SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings)
  	}
  
  	r300->hw.fpt.cmd[R300_FPT_CMD_0] =
@@ -14189,7 +14203,7 @@ index 8095538..f49b43c 100644
  }
  
  static void r500SetupFragmentShaderTextures(GLcontext *ctx, int *tmu_mappings)
-@@ -1320,7 +1279,7 @@ static GLuint translate_lod_bias(GLfloat bias)
+@@ -1320,7 +1280,7 @@ static GLuint translate_lod_bias(GLfloat bias)
  static void r300SetupTextures(GLcontext * ctx)
  {
  	int i, mtu;
@@ -14198,7 +14212,7 @@ index 8095538..f49b43c 100644
  	r300ContextPtr r300 = R300_CONTEXT(ctx);
  	int hw_tmu = 0;
  	int last_hw_tmu = -1;	/* -1 translates into no setup costs for fields */
-@@ -1354,21 +1313,16 @@ static void r300SetupTextures(GLcontext * ctx)
+@@ -1354,21 +1314,16 @@ static void r300SetupTextures(GLcontext * ctx)
  	/* We cannot let disabled tmu offsets pass DRM */
  	for (i = 0; i < mtu; i++) {
  		if (ctx->Texture.Unit[i]._ReallyEnabled) {
@@ -14223,7 +14237,7 @@ index 8095538..f49b43c 100644
  			}
  
  			if (RADEON_DEBUG & DEBUG_STATE)
-@@ -1379,29 +1333,28 @@ static void r300SetupTextures(GLcontext * ctx)
+@@ -1379,29 +1334,28 @@ static void r300SetupTextures(GLcontext * ctx)
  
  			r300->hw.tex.filter.cmd[R300_TEX_VALUE_0 +
  						hw_tmu] =
@@ -14262,7 +14276,7 @@ index 8095538..f49b43c 100644
  				WARN_ONCE("micro tiling enabled!\n");
  			}
  
-@@ -1418,21 +1371,21 @@ static void r300SetupTextures(GLcontext * ctx)
+@@ -1418,21 +1372,21 @@ static void r300SetupTextures(GLcontext * ctx)
  	}
  
  	r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
@@ -14292,7 +14306,7 @@ index 8095538..f49b43c 100644
  
  	if (!fp)		/* should only happenen once, just after context is created */
  		return;
-@@ -1444,7 +1397,7 @@ static void r300SetupTextures(GLcontext * ctx)
+@@ -1444,7 +1398,7 @@ static void r300SetupTextures(GLcontext * ctx)
  			r300->hw.txe.cmd[R300_TXE_ENABLE] |= 1;
  			r300->hw.tex.filter.cmd[R300_TEX_VALUE_0] = 0;
  			r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
@@ -14301,7 +14315,7 @@ index 8095538..f49b43c 100644
  		}
  		r300SetupFragmentShaderTextures(ctx, tmu_mappings);
  	} else
-@@ -1609,7 +1562,7 @@ static void r300SetupRSUnit(GLcontext * ctx)
+@@ -1609,7 +1563,7 @@ static void r300SetupRSUnit(GLcontext * ctx)
  	r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT)  | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN;
  	r300->hw.rc.cmd[2] |= high_rr - 1;
  
@@ -14310,7 +14324,7 @@ index 8095538..f49b43c 100644
  
  	if (InputsRead)
  		WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
-@@ -1787,7 +1740,7 @@ static void r500SetupRSUnit(GLcontext * ctx)
+@@ -1787,7 +1741,7 @@ static void r500SetupRSUnit(GLcontext * ctx)
  	r300->hw.rc.cmd[1] |= (rs_tex_count << R300_IT_COUNT_SHIFT)  | (col_ip << R300_IC_COUNT_SHIFT) | R300_HIRES_EN;
  	r300->hw.rc.cmd[2] |= 0xC0 | (high_rr - 1);
  
@@ -14319,7 +14333,7 @@ index 8095538..f49b43c 100644
  
  	if (InputsRead)
  		WARN_ONCE("Don't know how to satisfy InputsRead=0x%08x\n", InputsRead);
-@@ -1984,6 +1937,7 @@ static void r300SetupRealVertexProgram(r300ContextPtr rmesa)
+@@ -1984,6 +1938,7 @@ static void r300SetupRealVertexProgram(r300ContextPtr rmesa)
  	  (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
  }
  
@@ -14327,7 +14341,7 @@ index 8095538..f49b43c 100644
  static void r300SetupVertexProgram(r300ContextPtr rmesa)
  {
  	GLcontext *ctx = rmesa->radeon.glCtx;
-@@ -2013,6 +1967,7 @@ static void r300SetupVertexProgram(r300ContextPtr rmesa)
+@@ -2013,6 +1968,7 @@ static void r300SetupVertexProgram(r300ContextPtr rmesa)
   */
  static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
  {
@@ -14335,7 +14349,7 @@ index 8095538..f49b43c 100644
  	if (RADEON_DEBUG & DEBUG_STATE)
  		fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__,
  			_mesa_lookup_enum_by_nr(cap),
-@@ -2058,8 +2013,12 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
+@@ -2058,8 +2014,12 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
  	case GL_POLYGON_OFFSET_FILL:
  		r300SetPolygonOffsetState(ctx, state);
  		break;
@@ -14349,25 +14363,16 @@ index 8095538..f49b43c 100644
  		break;
  	}
  }
-@@ -2070,6 +2029,7 @@ static void r300Enable(GLcontext * ctx, GLenum cap, GLboolean state)
- static void r300ResetHwState(r300ContextPtr r300)
- {
- 	GLcontext *ctx = r300->radeon.glCtx;
-+	struct radeon_renderbuffer *rrb;
- 	int has_tcl = 1;
- 
- 	if (!(r300->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL))
-@@ -2078,7 +2038,8 @@ static void r300ResetHwState(r300ContextPtr r300)
+@@ -2078,7 +2038,7 @@ static void r300ResetHwState(r300ContextPtr r300)
  	if (RADEON_DEBUG & DEBUG_STATE)
  		fprintf(stderr, "%s\n", __FUNCTION__);
  
 -	r300UpdateWindow(ctx);
 +	radeon_firevertices(&r300->radeon);
-+	//r300UpdateWindow(ctx);
  
  	r300ColorMask(ctx,
  		      ctx->Color.ColorMask[RCOMP],
-@@ -2100,8 +2061,6 @@ static void r300ResetHwState(r300ContextPtr r300)
+@@ -2100,8 +2060,6 @@ static void r300ResetHwState(r300ContextPtr r300)
  
  	r300UpdateCulling(ctx);
  
@@ -14376,7 +14381,7 @@ index 8095538..f49b43c 100644
  	r300SetBlendState(ctx);
  	r300SetLogicOpState(ctx);
  
-@@ -2240,20 +2199,6 @@ static void r300ResetHwState(r300ContextPtr r300)
+@@ -2240,20 +2198,6 @@ static void r300ResetHwState(r300ContextPtr r300)
  
  	r300BlendColor(ctx, ctx->Color.BlendColor);
  
@@ -14397,7 +14402,7 @@ index 8095538..f49b43c 100644
  	r300->hw.rb3d_dither_ctl.cmd[1] = 0;
  	r300->hw.rb3d_dither_ctl.cmd[2] = 0;
  	r300->hw.rb3d_dither_ctl.cmd[3] = 0;
-@@ -2269,34 +2214,8 @@ static void r300ResetHwState(r300ContextPtr r300)
+@@ -2269,34 +2213,8 @@ static void r300ResetHwState(r300ContextPtr r300)
  	r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[1] = 0x00000000;
  	r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[2] = 0xffffffff;
  
@@ -14432,7 +14437,7 @@ index 8095538..f49b43c 100644
  	r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE;
  	r300->hw.zstencil_format.cmd[3] = 0x00000003;
  	r300->hw.zstencil_format.cmd[4] = 0x00000000;
-@@ -2317,7 +2236,7 @@ static void r300ResetHwState(r300ContextPtr r300)
+@@ -2317,7 +2235,7 @@ static void r300ResetHwState(r300ContextPtr r300)
  		r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0;
  	}
  
@@ -14441,7 +14446,7 @@ index 8095538..f49b43c 100644
  }
  
  void r300UpdateShaders(r300ContextPtr rmesa)
-@@ -2328,8 +2247,8 @@ void r300UpdateShaders(r300ContextPtr rmesa)
+@@ -2328,8 +2246,8 @@ void r300UpdateShaders(r300ContextPtr rmesa)
  
  	ctx = rmesa->radeon.glCtx;
  
@@ -14452,7 +14457,7 @@ index 8095538..f49b43c 100644
  
  		for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) {
  			rmesa->temp_attrib[i] =
-@@ -2408,10 +2327,10 @@ static void r300SetupPixelShader(r300ContextPtr rmesa)
+@@ -2408,10 +2326,10 @@ static void r300SetupPixelShader(r300ContextPtr rmesa)
  	R300_STATECHANGE(rmesa, fpi[1]);
  	R300_STATECHANGE(rmesa, fpi[2]);
  	R300_STATECHANGE(rmesa, fpi[3]);
@@ -14467,7 +14472,7 @@ index 8095538..f49b43c 100644
  	for (i = 0; i < code->alu.length; i++) {
  		rmesa->hw.fpi[0].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst0;
  		rmesa->hw.fpi[1].cmd[R300_FPI_INSTR_0 + i] = code->alu.inst[i].inst1;
-@@ -2442,7 +2361,7 @@ static void r300SetupPixelShader(r300ContextPtr rmesa)
+@@ -2442,7 +2360,7 @@ static void r300SetupPixelShader(r300ContextPtr rmesa)
  	}
  
  	R300_STATECHANGE(rmesa, fpp);
@@ -14476,7 +14481,7 @@ index 8095538..f49b43c 100644
  	for (i = 0; i < code->const_nr; i++) {
  		const GLfloat *constant = get_fragmentprogram_constant(ctx,
  			&fp->mesa_program.Base, code->constant[i]);
-@@ -2534,7 +2453,6 @@ void r300UpdateShaderStates(r300ContextPtr rmesa)
+@@ -2534,7 +2452,6 @@ void r300UpdateShaderStates(r300ContextPtr rmesa)
  	GLcontext *ctx;
  	ctx = rmesa->radeon.glCtx;
  
@@ -14484,7 +14489,7 @@ index 8095538..f49b43c 100644
  	r300SetEarlyZState(ctx);
  
  	/* w_fmt value is set to get best performance
-@@ -2587,12 +2505,16 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
+@@ -2587,12 +2504,16 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
  	_ae_invalidate_state(ctx, new_state);
  
  	if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL)) {
@@ -14503,10 +14508,13 @@ index 8095538..f49b43c 100644
  }
  
  /**
-@@ -2605,27 +2527,6 @@ void r300InitState(r300ContextPtr r300)
- 	GLcontext *ctx = r300->radeon.glCtx;
- 	GLuint depth_fmt;
- 
+@@ -2602,30 +2523,6 @@ static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
+  */
+ void r300InitState(r300ContextPtr r300)
+ {
+-	GLcontext *ctx = r300->radeon.glCtx;
+-	GLuint depth_fmt;
+-
 -	radeonInitState(&r300->radeon);
 -
 -	switch (ctx->Visual.depthBits) {
@@ -14531,7 +14539,7 @@ index 8095538..f49b43c 100644
  	memset(&(r300->state.texture), 0, sizeof(r300->state.texture));
  
  	r300ResetHwState(r300);
-@@ -2661,7 +2562,6 @@ void r300UpdateClipPlanes( GLcontext *ctx )
+@@ -2661,7 +2558,6 @@ void r300UpdateClipPlanes( GLcontext *ctx )
   */
  void r300InitStateFuncs(struct dd_function_table *functions)
  {
@@ -14539,7 +14547,7 @@ index 8095538..f49b43c 100644
  
  	functions->UpdateState = r300InvalidateState;
  	functions->AlphaFunc = r300AlphaFunc;
-@@ -2697,4 +2597,8 @@ void r300InitStateFuncs(struct dd_function_table *functions)
+@@ -2697,4 +2593,8 @@ void r300InitStateFuncs(struct dd_function_table *functions)
  	functions->RenderMode = r300RenderMode;
  
  	functions->ClipPlane = r300ClipPlane;
@@ -16577,7 +16585,7 @@ index b03eefa..0000000
 -	return 0;
 -}
 diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
-index e2329f0..d16cf68 100644
+index e2329f0..0c6d092 100644
 --- a/src/mesa/drivers/dri/r300/r300_texstate.c
 +++ b/src/mesa/drivers/dri/r300/r300_texstate.c
 @@ -47,7 +47,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -16622,7 +16630,7 @@ index e2329f0..d16cf68 100644
  		break;
  	default:
  		/* Error...which should have already been caught by higher
-@@ -190,479 +189,319 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj)
+@@ -190,479 +189,320 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj)
  
  
  /**
@@ -17262,9 +17270,10 @@ index e2329f0..d16cf68 100644
 +		radeon_miptree_unreference(rImage->mt);
 +		rImage->mt = NULL;
 +	}
-+	fprintf(stderr,"settexbuf %dx%d@%d targ %x format %x\n", rb->width, rb->height, rb->cpp, target, format);
++	fprintf(stderr,"settexbuf %dx%d@%d %d targ %x format %x\n", rb->width, rb->height, rb->cpp, rb->pitch, target, format);
 +	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
 +				   rb->width, rb->height, 1, 0, rb->cpp);
++	texImage->RowStride = rb->pitch / rb->cpp;
 +	texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx,
 +							internalFormat,
 +							type, format);
@@ -20593,7 +20602,7 @@ index 0000000..4b5116c
 +#endif
 diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
 new file mode 100644
-index 0000000..9f646c4
+index 0000000..3ce868d
 --- /dev/null
 +++ b/src/mesa/drivers/dri/radeon/radeon_common.c
 @@ -0,0 +1,1353 @@
@@ -21693,7 +21702,7 @@ index 0000000..9f646c4
 +
 +		if (!drmCommandWriteRead(rmesa->dri.fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo)))
 +		{
-+			radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, mminfo.vram_size);
++			radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_VRAM, mminfo.vram_visible);
 +			radeon_cs_set_limit(rmesa->cmdbuf.cs, RADEON_GEM_DOMAIN_GTT, mminfo.gart_size);
 +		}
 +	}
@@ -22055,10 +22064,10 @@ index 0000000..f3e2290
 +#endif
 diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
 new file mode 100644
-index 0000000..5b23473
+index 0000000..9964de7
 --- /dev/null
 +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
-@@ -0,0 +1,602 @@
+@@ -0,0 +1,603 @@
 +/**************************************************************************
 +
 +Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
@@ -22097,6 +22106,7 @@ index 0000000..5b23473
 +#include "xmlpool.h"		/* for symbolic values of enum-type options */
 +#include "utils.h"
 +#include "vblank.h"
++#include "drirenderbuffer.h"
 +#include "main/state.h"
 +
 +#define DRIVER_DATE "20090101"
@@ -22459,7 +22469,7 @@ index 0000000..5b23473
 +	struct radeon_framebuffer *draw;
 +	radeonContextPtr radeon;
 +	char *regname;
-+	struct radeon_bo *depth_bo, *bo;
++	struct radeon_bo *depth_bo = NULL, *bo;
 +
 +	if (RADEON_DEBUG & DEBUG_DRI)
 +	    fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
@@ -25752,10 +25762,10 @@ index 0000000..cee3744
 +#endif
 diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c
 new file mode 100644
-index 0000000..4094585
+index 0000000..96ba5d3
 --- /dev/null
 +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c
-@@ -0,0 +1,567 @@
+@@ -0,0 +1,568 @@
 +/**************************************************************************
 + * 
 + * Copyright 2008 Red Hat Inc.
@@ -26268,8 +26278,9 @@ index 0000000..4094585
 +                                            att->TextureLevel);
 +
 +   if (att->Texture->Target == GL_TEXTURE_3D) {
-+      const GLuint *offsets = radeon_miptree_depth_offsets(radeon_image->mt,
-+                                                          att->TextureLevel);
++      GLuint offsets[6];
++      radeon_miptree_depth_offsets(radeon_image->mt, att->TextureLevel,
++				   offsets);
 +      imageOffset += offsets[att->Zoffset];
 +   }
 +
@@ -28056,7 +28067,7 @@ index 4e3a44d..18805d4 100644
 +
  #endif /* __RADEON_IOCTL_H__ */
 diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c
-index 64bb3ca..e1bb2cd 100644
+index 64bb3ca..fe19218 100644
 --- a/src/mesa/drivers/dri/radeon/radeon_lock.c
 +++ b/src/mesa/drivers/dri/radeon/radeon_lock.c
 @@ -41,30 +41,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -28094,16 +28105,17 @@ index 64bb3ca..e1bb2cd 100644
  /* Update the hardware state.  This is called if another context has
   * grabbed the hardware lock, which includes the X server.  This
   * function also updates the driver's window state after the X server
-@@ -80,6 +63,8 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
+@@ -78,7 +61,8 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
+ 	__DRIdrawablePrivate *const drawable = rmesa->dri.drawable;
+ 	__DRIdrawablePrivate *const readable = rmesa->dri.readable;
  	__DRIscreenPrivate *sPriv = rmesa->dri.screen;
- 	drm_radeon_sarea_t *sarea = rmesa->sarea;
- 
-+	assert(drawable != NULL);
+-	drm_radeon_sarea_t *sarea = rmesa->sarea;
 +
++	assert(drawable != NULL);
+ 
  	drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags);
  
- 	/* The window might have moved, so we might need to get new clip
-@@ -96,29 +81,43 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
+@@ -96,29 +80,42 @@ void radeonGetLock(radeonContextPtr rmesa, GLuint flags)
  	}
  
  	if (rmesa->lastStamp != drawable->lastStamp) {
@@ -28133,7 +28145,6 @@ index 64bb3ca..e1bb2cd 100644
 -		sarea->ctx_owner = rmesa->dri.hwContext;
 +void radeon_lock_hardware(radeonContextPtr radeon)
 +{
-+	__DRIdrawable *dPriv = radeon->dri.drawable;
 +	char ret = 0;
 +	struct radeon_framebuffer *rfb = NULL;
 +	struct radeon_renderbuffer *rrb = NULL;
@@ -28951,7 +28962,7 @@ index 126d072..d468a97 100644
  }
 diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
 new file mode 100644
-index 0000000..228629e
+index 0000000..34d6261
 --- /dev/null
 +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c
 @@ -0,0 +1,386 @@
@@ -29051,8 +29062,6 @@ index 0000000..228629e
 +	/* Find image size in bytes */
 +	if (mt->compressed) {
 +		/* TODO: Is this correct? Need test cases for compressed textures! */
-+		GLuint align;
-+
 +		lvl->rowstride = (lvl->width * mt->bpp + 63) & ~63;
 +		lvl->size = radeon_compressed_texture_size(mt->radeon->glCtx,
 +							   lvl->width, lvl->height, lvl->depth, mt->compressed);
@@ -29322,14 +29331,16 @@ index 0000000..228629e
 + *
 + * These functions present that view to mesa:
 + */
-+const GLuint *
-+radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level)
++void
++radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets)
 +{
-+     static const GLuint zero = 0;
 +     if (mt->target != GL_TEXTURE_3D || mt->faces == 1)
-+       return &zero;
-+     else
-+       return mt->levels[level].faces[0].offset;
++        offsets[0] = 0;
++     else {
++	int i;
++	for (i = 0; i < 6; i++)
++		offsets[i] = mt->levels[level].faces[i].offset;
++     }
 +}
 +
 +GLuint
@@ -29343,10 +29354,10 @@ index 0000000..228629e
 +}
 diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
 new file mode 100644
-index 0000000..d9ad5ad
+index 0000000..697010b
 --- /dev/null
 +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
-@@ -0,0 +1,99 @@
+@@ -0,0 +1,98 @@
 +/*
 + * Copyright (C) 2008 Nicolai Haehnle.
 + *
@@ -29443,8 +29454,7 @@ index 0000000..d9ad5ad
 +			      struct gl_texture_image *texImage, GLuint face, GLuint level);
 +GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt,
 +				   GLuint face, GLuint level);
-+const GLuint *
-+radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level);
++void radeon_miptree_depth_offsets(radeon_mipmap_tree *mt, GLuint level, GLuint *offsets);
 +#endif /* __RADEON_MIPMAP_TREE_H_ */
 diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c
 index 6613757..bbed838 100644
@@ -30546,7 +30556,7 @@ index b84c70b..1c0f5bb 100644
  
  #define IS_R100_CLASS(screen) \
 diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
-index 12051ff..3d2c5da 100644
+index 12051ff..0b4eaae 100644
 --- a/src/mesa/drivers/dri/radeon/radeon_span.c
 +++ b/src/mesa/drivers/dri/radeon/radeon_span.c
 @@ -43,46 +43,190 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -30950,7 +30960,7 @@ index 12051ff..3d2c5da 100644
     d = (tmp & 0xff000000) >> 24;					\
  } while (0)
  #endif
-@@ -271,20 +376,84 @@ do {									\
+@@ -271,20 +376,83 @@ do {									\
  #define TAG(x) radeon##x##_z24_s8
  #include "stenciltmp.h"
  
@@ -30959,7 +30969,7 @@ index 12051ff..3d2c5da 100644
 - * culprit.
 - */
  
-+void map_unmap_rb(struct gl_renderbuffer *rb, int flag)
++static void map_unmap_rb(struct gl_renderbuffer *rb, int flag)
 +{
 +	struct radeon_renderbuffer *rrb = radeon_renderbuffer(rb);
 +	int r;
@@ -30985,7 +30995,6 @@ index 12051ff..3d2c5da 100644
 +static void
 +radeon_map_unmap_buffers(GLcontext *ctx, GLboolean map)
 +{
-+	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 +	GLuint i, j;
 +
 +	/* color draw buffers */
@@ -31045,7 +31054,7 @@ index 12051ff..3d2c5da 100644
  	LOCK_HARDWARE(rmesa);
  	radeonWaitForIdleLocked(rmesa);
  }
-@@ -292,8 +461,16 @@ static void radeonSpanRenderStart(GLcontext * ctx)
+@@ -292,8 +460,16 @@ static void radeonSpanRenderStart(GLcontext * ctx)
  static void radeonSpanRenderFinish(GLcontext * ctx)
  {
  	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
@@ -31062,7 +31071,7 @@ index 12051ff..3d2c5da 100644
  }
  
  void radeonInitSpanFuncs(GLcontext * ctx)
-@@ -307,20 +484,21 @@ void radeonInitSpanFuncs(GLcontext * ctx)
+@@ -307,20 +483,21 @@ void radeonInitSpanFuncs(GLcontext * ctx)
  /**
   * Plug in the Get/Put routines for the given driRenderbuffer.
   */
@@ -32902,7 +32911,7 @@ index 57dc380..3d0cd8d 100644
 +   rcommonInitCmdBuf(&rmesa->radeon);
  }
 diff --git a/src/mesa/drivers/dri/radeon/radeon_swtcl.c b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
-index ebea1fe..af933a3 100644
+index ebea1fe..2484006 100644
 --- a/src/mesa/drivers/dri/radeon/radeon_swtcl.c
 +++ b/src/mesa/drivers/dri/radeon/radeon_swtcl.c
 @@ -52,8 +52,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -33029,8 +33038,7 @@ index ebea1fe..af933a3 100644
 -/* Flush vertices in the current dma region.
 - */
 -static void flush_last_swtcl_prim( radeonContextPtr rmesa  )
-+void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
- {
+-{
 -   if (RADEON_DEBUG & DEBUG_IOCTL)
 -      fprintf(stderr, "%s\n", __FUNCTION__);
 -
@@ -33043,55 +33051,46 @@ index ebea1fe..af933a3 100644
 -			       current->start);
 -
 -      assert (!(rmesa->swtcl.hw_primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
-+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
- 
+-
 -      assert (current->start + 
 -	      rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
 -	      current->ptr);
-+   rcommonEnsureCmdBufSpace(&rmesa->radeon,
-+			    rmesa->radeon.hw.max_state_size + (12*sizeof(int)),
-+			    __FUNCTION__);
- 
+-
 -      if (rmesa->dma.current.start != rmesa->dma.current.ptr) {
 -	 radeonEnsureCmdBufSpace( rmesa, VERT_AOS_BUFSZ +
 -			          rmesa->hw.max_state_size + VBUF_BUFSZ );
- 
+-
 -	 radeonEmitVertexAOS( rmesa,
 -			      rmesa->swtcl.vertex_size,
 -			      current_offset);
-+   radeonEmitState(&rmesa->radeon);
-+   radeonEmitVertexAOS( rmesa,
-+			rmesa->radeon.swtcl.vertex_size,
-+			rmesa->radeon.dma.current,
-+			current_offset);
- 
+-
 -	 radeonEmitVbufPrim( rmesa,
 -			     rmesa->swtcl.vertex_format,
 -			     rmesa->swtcl.hw_primitive,
 -			     rmesa->swtcl.numverts);
 -      }
-+		      
-+   radeonEmitVbufPrim( rmesa,
-+		       rmesa->swtcl.vertex_format,
-+		       rmesa->radeon.swtcl.hw_primitive,
-+		       rmesa->radeon.swtcl.numverts);
- 
+-
 -      rmesa->swtcl.numverts = 0;
 -      current->start = current->ptr;
 -   }
- }
- 
+-}
+-
 -
 -/* Alloc space in the current dma region.
 - */
 -static INLINE void *
 -radeonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize )
--{
++void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
+ {
 -   GLuint bytes = vsize * nverts;
--
++   r100ContextPtr rmesa = R100_CONTEXT(ctx);
+ 
 -   if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) 
 -      radeonRefillCurrentDmaRegion( rmesa );
--
++   rcommonEnsureCmdBufSpace(&rmesa->radeon,
++			    rmesa->radeon.hw.max_state_size + (12*sizeof(int)),
++			    __FUNCTION__);
+ 
 -   if (!rmesa->dma.flush) {
 -      rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 -      rmesa->dma.flush = flush_last_swtcl_prim;
@@ -33102,17 +33101,27 @@ index ebea1fe..af933a3 100644
 -   assert (rmesa->dma.current.start + 
 -	   rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
 -	   rmesa->dma.current.ptr);
--
--
+ 
++   radeonEmitState(&rmesa->radeon);
++   radeonEmitVertexAOS( rmesa,
++			rmesa->radeon.swtcl.vertex_size,
++			rmesa->radeon.dma.current,
++			current_offset);
+ 
 -   {
 -      GLubyte *head = (GLubyte *)(rmesa->dma.current.address + rmesa->dma.current.ptr);
 -      rmesa->dma.current.ptr += bytes;
 -      rmesa->swtcl.numverts += nverts;
 -      return head;
 -   }
--
--}
--
++		      
++   radeonEmitVbufPrim( rmesa,
++		       rmesa->swtcl.vertex_format,
++		       rmesa->radeon.swtcl.hw_primitive,
++		       rmesa->radeon.swtcl.numverts);
+ 
+ }
+ 
 -
  /*
   * Render unclipped vertex buffers by emitting vertices directly to
@@ -33348,7 +33357,7 @@ index ebea1fe..af933a3 100644
     static int firsttime = 1;
  
     if (firsttime) {
-@@ -872,18 +816,15 @@ void radeonInitSwtcl( GLcontext *ctx )
+@@ -872,18 +816,13 @@ void radeonInitSwtcl( GLcontext *ctx )
     _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, 
  		       RADEON_MAX_TNL_VERTEX_SIZE);
     
@@ -33366,8 +33375,7 @@ index ebea1fe..af933a3 100644
  void radeonDestroySwtcl( GLcontext *ctx )
  {
 -   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
-+   r100ContextPtr rmesa = R100_CONTEXT(ctx);
- 
+-
 -   if (rmesa->swtcl.indexed_verts.buf) 
 -      radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts, 
 -			      __FUNCTION__ );
@@ -34633,7 +34641,7 @@ index 5f7bbe6..0000000
 -   return 0;
 -}
 diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
-index b165205..78e2a08 100644
+index b165205..dab0df0 100644
 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
 +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
 @@ -39,10 +39,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -34955,7 +34963,7 @@ index b165205..78e2a08 100644
  	t->pp_txpitch = pitch - 32;
  
  	switch (depth) {
-@@ -881,6 +637,121 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
+@@ -881,6 +637,122 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
  	}
  }
  
@@ -35029,6 +35037,7 @@ index b165205..78e2a08 100644
 +	}
 +	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
 +				   rb->width, rb->height, 1, 0, rb->cpp);
++	texImage->RowStride = rb->pitch / rb->cpp;
 +	texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx,
 +							internalFormat,
 +							type, format);
@@ -35077,7 +35086,7 @@ index b165205..78e2a08 100644
  #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK |	\
  			      RADEON_MIN_FILTER_MASK | 		\
  			      RADEON_MAG_FILTER_MASK |		\
-@@ -901,12 +772,58 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
+@@ -901,12 +773,53 @@ void radeonSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
                                RADEON_TXFORMAT_NON_POWER2)
  
  
@@ -35085,11 +35094,6 @@ index b165205..78e2a08 100644
 +static void disable_tex_obj_state( r100ContextPtr rmesa, 
 +				   int unit )
 +{
-+   /* do not use RADEON_DB_STATE to avoid stale texture caches */
-+   uint32_t *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0];
-+   GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
-+   GLuint *txr_cmd = RADEON_DB_STATE( txr[unit] );
-+
 +   RADEON_STATECHANGE( rmesa, tex[unit] );
 +
 +   RADEON_STATECHANGE( rmesa, tcl );
@@ -35138,7 +35142,7 @@ index b165205..78e2a08 100644
     GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
  
     RADEON_STATECHANGE( rmesa, tex[unit] );
-@@ -915,10 +832,9 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
+@@ -915,10 +828,9 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
     cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK;
     cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK;
     cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK;
@@ -35150,7 +35154,7 @@ index b165205..78e2a08 100644
        GLuint *txr_cmd = RADEON_DB_STATE( txr[unit] );
        txr_cmd[TXR_PP_TEX_SIZE] = texobj->pp_txsize; /* NPOT only! */
        txr_cmd[TXR_PP_TEX_PITCH] = texobj->pp_txpitch; /* NPOT only! */
-@@ -928,22 +844,12 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
+@@ -928,22 +840,12 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
     else {
        se_coord_fmt &= ~(RADEON_VTX_ST0_NONPARAMETRIC << unit);
  
@@ -35176,7 +35180,7 @@ index b165205..78e2a08 100644
        }
     }
  
-@@ -952,13 +858,11 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
+@@ -952,13 +854,11 @@ static void import_tex_obj_state( radeonContextPtr rmesa,
        rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
     }
  
@@ -35192,7 +35196,7 @@ index b165205..78e2a08 100644
  			       GLuint unit,
  			       const GLfloat *s_plane,
  			       const GLfloat *t_plane,
-@@ -986,14 +890,14 @@ static void set_texgen_matrix( radeonContextPtr rmesa,
+@@ -986,14 +886,14 @@ static void set_texgen_matrix( radeonContextPtr rmesa,
     rmesa->TexGenMatrix[unit].m[15] = q_plane[3];
  
     rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE << unit;
@@ -35209,16 +35213,17 @@ index b165205..78e2a08 100644
     struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
     GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
     GLuint tmp = rmesa->TexGenEnabled;
-@@ -1094,283 +998,189 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit )
+@@ -1094,283 +994,187 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit )
     }
  
     if (tmp != rmesa->TexGenEnabled) {
 -      rmesa->NewGLState |= _NEW_TEXTURE_MATRIX;
--   }
--
--   return GL_TRUE;
--}
--
++      rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
+    }
+ 
+    return GL_TRUE;
+ }
+ 
 -
 -static void disable_tex( GLcontext *ctx, int unit )
 -{
@@ -35298,12 +35303,11 @@ index b165205..78e2a08 100644
 -      radeonUploadTexImages( rmesa, (radeonTexObjPtr) tObj->DriverData, 0 );
 -      if ( !t->base.memBlock && !t->image_override ) 
 -	return GL_FALSE;
-+      rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
-    }
- 
-    return GL_TRUE;
- }
- 
+-   }
+-
+-   return GL_TRUE;
+-}
+-
 -static GLboolean enable_tex_cube( GLcontext *ctx, int unit )
 +/**
 + * Compute the cached hardware register values for the given texture object.
@@ -35551,8 +35555,8 @@ index b165205..78e2a08 100644
 -
  static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit )
  {
+-   struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
 +   r100ContextPtr rmesa = R100_CONTEXT(ctx);
-    struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
  
 -   if ( texUnit->_ReallyEnabled & (TEXTURE_RECT_BIT) ) {
 -      return (enable_tex_rect( ctx, unit ) &&
@@ -35565,7 +35569,6 @@ index b165205..78e2a08 100644
 -   else if ( texUnit->_ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
 -      return (enable_tex_cube( ctx, unit ) &&
 -	      update_tex_common( ctx, unit ));
-+
 +   if (ctx->Texture.Unit[unit]._ReallyEnabled & TEXTURE_3D_BIT) {
 +     return GL_FALSE;
     }
@@ -35614,10 +35617,10 @@ index b165205..78e2a08 100644
  }
 diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
 new file mode 100644
-index 0000000..d212898
+index 0000000..a38d76a
 --- /dev/null
 +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
-@@ -0,0 +1,969 @@
+@@ -0,0 +1,993 @@
 +/*
 + * Copyright (C) 2008 Nicolai Haehnle.
 + * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
@@ -35751,6 +35754,25 @@ index 0000000..d212898
 +	}
 +}
 +
++static void map_override(GLcontext *ctx, radeonTexObj *t)
++{
++	radeon_texture_image *img = get_radeon_texture_image(t->base.Image[0][0]);
++
++	radeon_bo_map(t->bo, GL_FALSE);
++
++	img->base.Data = t->bo->ptr;
++	_mesa_set_fetch_functions(&img->base, 2);
++}
++
++static void unmap_override(GLcontext *ctx, radeonTexObj *t)
++{
++	radeon_texture_image *img = get_radeon_texture_image(t->base.Image[0][0]);
++
++	radeon_bo_unmap(t->bo);
++
++	img->base.Data = NULL;
++}
++
 +/**
 + * Map a validated texture for reading during software rendering.
 + */
@@ -35763,8 +35785,11 @@ index 0000000..d212898
 +	  return;
 +
 +	/* for r100 3D sw fallbacks don't have mt */
++	if (t->image_override && t->bo)
++		map_override(ctx, t);
++
 +	if (!t->mt)
-+	    return;
++		return;
 +
 +	radeon_bo_map(t->mt->bo, GL_FALSE);
 +	for(face = 0; face < t->mt->faces; ++face) {
@@ -35778,6 +35803,8 @@ index 0000000..d212898
 +	radeonTexObj* t = radeon_tex_obj(texObj);
 +	int face, level;
 +
++	if (t->image_override && t->bo)
++		unmap_override(ctx, t);
 +	/* for r100 3D sw fallbacks don't have mt */
 +	if (!t->mt)
 +	  return;