From 12de98b9558c310ef0df24ed13fc34f9a64b2e34 Mon Sep 17 00:00:00 2001 From: eabdullin Date: Wed, 14 May 2025 15:09:46 +0000 Subject: [PATCH] import UBI mesa-24.2.8-2.el10_0 --- .gitignore | 6 +- .mesa.metadata | 3 - ... Mesa-MLAA-License-Clarification-Email.txt | 0 RHEL-53423.patch | 2565 +++++++++++++++++ ...ver-llvm-move-to-modern-pass-manager.patch | 127 - ...clude-old-Transform-includes-when-ne.patch | 41 - ...one-for-newblock-allocation-in-dlist.patch | 28 - ...rease-overallocation-on-shader-bo-to.patch | 37 - SOURCES/Makefile | 23 - SOURCES/fix-py-ver.patch | 12 - SOURCES/lavapipe-disable-env-var.patch | 13 - .../nouveau-work-around-linear-zs-issue.patch | 30 - SOURCES/radeonsi-turn-off-glthread.patch | 11 - SOURCES/vl_decoder.c | 20 - SOURCES/vl_mpeg12_decoder.c | 7 - SPECS/mesa.spec | 1438 --------- ...atch => gnome-shell-glthread-disable.patch | 0 mesa.spec | 1967 +++++++++++++ sources | 3 + 19 files changed, 4538 insertions(+), 1793 deletions(-) delete mode 100644 .mesa.metadata rename SOURCES/Mesa-MLAA-License-Clarification-Email.txt => Mesa-MLAA-License-Clarification-Email.txt (100%) create mode 100644 RHEL-53423.patch delete mode 100644 SOURCES/0001-clover-llvm-move-to-modern-pass-manager.patch delete mode 100644 SOURCES/0001-llvmpipe-only-include-old-Transform-includes-when-ne.patch delete mode 100644 SOURCES/0001-mesa-fix-off-by-one-for-newblock-allocation-in-dlist.patch delete mode 100644 SOURCES/0001-nouveau-nvc0-increase-overallocation-on-shader-bo-to.patch delete mode 100644 SOURCES/Makefile delete mode 100644 SOURCES/fix-py-ver.patch delete mode 100644 SOURCES/lavapipe-disable-env-var.patch delete mode 100644 SOURCES/nouveau-work-around-linear-zs-issue.patch delete mode 100644 SOURCES/radeonsi-turn-off-glthread.patch delete mode 100644 SOURCES/vl_decoder.c delete mode 100644 SOURCES/vl_mpeg12_decoder.c delete mode 100644 SPECS/mesa.spec rename SOURCES/gnome-shell-glthread-disable.patch => gnome-shell-glthread-disable.patch (100%) create mode 100644 mesa.spec create mode 100644 sources diff --git a/.gitignore b/.gitignore index 5fcc55c..3dd396c 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,3 @@ -SOURCES/dataclasses-0.8.tar.gz -SOURCES/mesa-23.1.4.tar.xz -SOURCES/meson-0.61.4.tar.gz +libclc-19.1.1.src.tar.xz +mesa-24.2.8.tar.xz +spirv-llvm-translator-90a9764.tar.gz diff --git a/.mesa.metadata b/.mesa.metadata deleted file mode 100644 index 7f273d1..0000000 --- a/.mesa.metadata +++ /dev/null @@ -1,3 +0,0 @@ -ef25d3e9e2523805baa314a4adcb915ae901740e SOURCES/dataclasses-0.8.tar.gz -8a48c0e1fbda2c9563ddcf95b05012ab00a8a692 SOURCES/mesa-23.1.4.tar.xz -b0ab169abd8ec87ce773a02b2c7d6a8664b8db00 SOURCES/meson-0.61.4.tar.gz diff --git a/SOURCES/Mesa-MLAA-License-Clarification-Email.txt b/Mesa-MLAA-License-Clarification-Email.txt similarity index 100% rename from SOURCES/Mesa-MLAA-License-Clarification-Email.txt rename to Mesa-MLAA-License-Clarification-Email.txt diff --git a/RHEL-53423.patch b/RHEL-53423.patch new file mode 100644 index 0000000..4a9c256 --- /dev/null +++ b/RHEL-53423.patch @@ -0,0 +1,2565 @@ +From 9797443fc2d655b8333ab80aec9d17a06706fe53 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= +Date: Wed, 20 Nov 2024 10:34:27 -0500 +Subject: [PATCH 01/27] ac/surface: adjust HiZ enablement + +Acked-by: Pierre-Eric Pelloux-Prayer +Part-of: +--- + src/amd/common/ac_surface.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c +index 3ecb5d57be4..69f722bc4cc 100644 +--- a/src/amd/common/ac_surface.c ++++ b/src/amd/common/ac_surface.c +@@ -3022,7 +3022,7 @@ static bool gfx12_compute_hiz_his_info(struct ac_addrlib *addrlib, const struct + { + assert(surf_in->flags.depth != surf_in->flags.stencil); + +- if (surf->flags & RADEON_SURF_NO_HTILE || (info->gfx_level == GFX12 && info->chip_rev == 0)) ++ if (surf->flags & RADEON_SURF_NO_HTILE || (info->gfx_level == GFX12 && info->chip_rev <= 1)) + return true; + + ADDR3_COMPUTE_SURFACE_INFO_OUTPUT out = {0}; +-- +2.48.1 + + +From 51f92a3545b42d4250da95e9623576b65e8260b9 Mon Sep 17 00:00:00 2001 +From: Pierre-Eric Pelloux-Prayer +Date: Thu, 21 Nov 2024 11:46:02 +0100 +Subject: [PATCH 02/27] radeonsi/gfx12: disable display dcc for front buffer + rendering +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Same logic as other chips, except we need to reallocate the texture +as we can't disable dcc. + +Reviewed-by: Marek Olšák +Part-of: +--- + src/gallium/drivers/radeonsi/si_texture.c | 33 ++++++++++++++++------- + 1 file changed, 24 insertions(+), 9 deletions(-) + +diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c +index ad234b2f018..ae65b725600 100644 +--- a/src/gallium/drivers/radeonsi/si_texture.c ++++ b/src/gallium/drivers/radeonsi/si_texture.c +@@ -797,16 +797,31 @@ static bool si_texture_get_handle(struct pipe_screen *screen, struct pipe_contex + assert(tex->surface.tile_swizzle == 0); + } + +- /* Since shader image stores don't support DCC on GFX8, +- * disable it for external clients that want write +- * access. ++ const bool debug_disable_dcc = sscreen->debug_flags & DBG(NO_EXPORTED_DCC); ++ /* Since shader image stores don't support DCC on GFX9 and older, ++ * disable it for external clients that want write access. + */ +- if (sscreen->debug_flags & DBG(NO_EXPORTED_DCC) || +- (usage & PIPE_HANDLE_USAGE_SHADER_WRITE && !tex->is_depth && tex->surface.meta_offset) || +- /* Displayable DCC requires an explicit flush. */ +- (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && +- si_displayable_dcc_needs_explicit_flush(tex))) { +- if (si_texture_disable_dcc(sctx, tex)) { ++ const bool shader_write = sscreen->info.gfx_level <= GFX9 && ++ usage & PIPE_HANDLE_USAGE_SHADER_WRITE && ++ !tex->is_depth && ++ tex->surface.meta_offset; ++ /* Another reason to disable display dcc is front buffer rendering. ++ * This can happens with Xorg. If the ddx driver uses GBM_BO_USE_FRONT_RENDERING, ++ * there's nothing to do because the texture is not using DCC. ++ * If the flag isn't set, we have to infer it to get correct rendering. ++ */ ++ const bool front_buffer_rendering = !(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && ++ tex->buffer.b.b.bind & PIPE_BIND_SCANOUT; ++ ++ /* If display dcc requires a retiling step, drop dcc. */ ++ const bool explicit_flush = !(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && ++ si_displayable_dcc_needs_explicit_flush(tex); ++ ++ if (debug_disable_dcc || shader_write || front_buffer_rendering || explicit_flush) { ++ if (sscreen->info.gfx_level >= GFX12) { ++ si_reallocate_texture_inplace(sctx, tex, PIPE_BIND_CONST_BW, false); ++ update_metadata = true; ++ } else if (si_texture_disable_dcc(sctx, tex)) { + update_metadata = true; + /* si_texture_disable_dcc flushes the context */ + flush = false; +-- +2.48.1 + + +From 89d3f1a550ade706459e6c2f0649608c084387ff Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= +Date: Mon, 16 Dec 2024 03:48:37 -0500 +Subject: [PATCH 03/27] radeonsi/gfx12: set DB_RENDER_OVERRIDE based on stencil + state + +Acked-by: Pierre-Eric Pelloux-Prayer +Part-of: +--- + src/gallium/drivers/radeonsi/si_gfx_cs.c | 1 + + src/gallium/drivers/radeonsi/si_state.c | 8 ++++++++ + src/gallium/drivers/radeonsi/si_state.h | 2 ++ + 3 files changed, 11 insertions(+) + +diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c +index 9b11eaf678e..31814bc94d2 100644 +--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c ++++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c +@@ -318,6 +318,7 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx) + ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ENA] = 0; + ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR] = 0; + ++ ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE] = 0; + ctx->tracked_regs.reg_value[SI_TRACKED_DB_EQAA] = 0; + ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0; + ctx->tracked_regs.reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0; +diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c +index 6bb1037a79b..018be3dbe4f 100644 +--- a/src/gallium/drivers/radeonsi/si_state.c ++++ b/src/gallium/drivers/radeonsi/si_state.c +@@ -1573,6 +1573,12 @@ static void *si_create_dsa_state(struct pipe_context *ctx, + S_028090_TESTMASK_BF(state->stencil[1].valuemask); + dsa->db_stencil_write_mask = S_028094_WRITEMASK(state->stencil[0].writemask) | + S_028094_WRITEMASK_BF(state->stencil[1].writemask); ++ ++ bool force_s_valid = state->stencil[0].zpass_op != state->stencil[0].zfail_op || ++ (state->stencil[1].enabled && ++ state->stencil[1].zpass_op != state->stencil[1].zfail_op); ++ dsa->db_render_override = S_02800C_FORCE_STENCIL_READ(1) | ++ S_02800C_FORCE_STENCIL_VALID(force_s_valid); + } + + bool zfunc_is_ordered = +@@ -1608,6 +1614,8 @@ static void si_pm4_emit_dsa(struct si_context *sctx, unsigned index) + if (sctx->gfx_level >= GFX12) { + radeon_begin(&sctx->gfx_cs); + gfx12_begin_context_regs(); ++ gfx12_opt_set_context_reg(R_02800C_DB_RENDER_OVERRIDE, SI_TRACKED_DB_RENDER_OVERRIDE, ++ state->db_render_override); + gfx12_opt_set_context_reg(R_028070_DB_DEPTH_CONTROL, SI_TRACKED_DB_DEPTH_CONTROL, + state->db_depth_control); + if (state->stencil_enabled) { +diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h +index a984c7d6918..f964fa21606 100644 +--- a/src/gallium/drivers/radeonsi/si_state.h ++++ b/src/gallium/drivers/radeonsi/si_state.h +@@ -130,6 +130,7 @@ struct si_state_dsa { + unsigned spi_shader_user_data_ps_alpha_ref; + unsigned db_stencil_read_mask; + unsigned db_stencil_write_mask; ++ unsigned db_render_override; /* only gfx12 */ + + /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */ + struct si_dsa_order_invariance order_invariance[2]; +@@ -314,6 +315,7 @@ enum si_tracked_reg + SI_TRACKED_SPI_PS_INPUT_ENA, + SI_TRACKED_SPI_PS_INPUT_ADDR, + ++ SI_TRACKED_DB_RENDER_OVERRIDE, + SI_TRACKED_DB_EQAA, + SI_TRACKED_DB_RENDER_OVERRIDE2, + SI_TRACKED_DB_SHADER_CONTROL, +-- +2.48.1 + + +From 9a0377096ab33b12c10913ecc2b5a1358da29923 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= +Date: Tue, 6 Aug 2024 16:23:01 -0400 +Subject: [PATCH 04/27] radeonsi: add a new PM4 helper radeon_event_write + +Reviewed-by: Pierre-Eric Pelloux-Prayer +Part-of: +--- + src/gallium/drivers/radeonsi/si_build_pm4.h | 11 +++ + src/gallium/drivers/radeonsi/si_compute.c | 7 +- + src/gallium/drivers/radeonsi/si_gfx_cs.c | 89 +++++++------------ + src/gallium/drivers/radeonsi/si_perfcounter.c | 21 ++--- + src/gallium/drivers/radeonsi/si_query.c | 3 +- + src/gallium/drivers/radeonsi/si_state.c | 24 +++-- + .../drivers/radeonsi/si_state_draw.cpp | 21 ++--- + .../drivers/radeonsi/si_state_shaders.cpp | 13 +-- + .../drivers/radeonsi/si_state_streamout.c | 3 +- + 9 files changed, 74 insertions(+), 118 deletions(-) + +diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h +index 15259aa329b..630b5885ff3 100644 +--- a/src/gallium/drivers/radeonsi/si_build_pm4.h ++++ b/src/gallium/drivers/radeonsi/si_build_pm4.h +@@ -503,6 +503,17 @@ + } \ + } while (0) + ++/* Other packet helpers. */ ++#define radeon_event_write(event_type) do { \ ++ unsigned __event_type = (event_type); \ ++ radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); \ ++ radeon_emit(EVENT_TYPE(__event_type) | \ ++ EVENT_INDEX(__event_type == V_028A90_VS_PARTIAL_FLUSH || \ ++ __event_type == V_028A90_PS_PARTIAL_FLUSH || \ ++ __event_type == V_028A90_CS_PARTIAL_FLUSH ? 4 : \ ++ __event_type == V_028A90_PIXEL_PIPE_STAT_CONTROL ? 1 : 0)); \ ++} while (0) ++ + /* This should be evaluated at compile time if all parameters are constants. */ + static ALWAYS_INLINE unsigned + si_get_user_data_base(enum amd_gfx_level gfx_level, enum si_has_tess has_tess, +diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c +index 727face471e..01aa75d222a 100644 +--- a/src/gallium/drivers/radeonsi/si_compute.c ++++ b/src/gallium/drivers/radeonsi/si_compute.c +@@ -1114,10 +1114,9 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_ + radeon_emit(dispatch_initiator); + } + +- if (unlikely(sctx->sqtt_enabled && sctx->gfx_level >= GFX9)) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0)); +- } ++ if (unlikely(sctx->sqtt_enabled && sctx->gfx_level >= GFX9)) ++ radeon_event_write(V_028A90_THREAD_TRACE_MARKER); ++ + radeon_end(); + } + +diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c +index 31814bc94d2..d8dccd9b008 100644 +--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c ++++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c +@@ -160,8 +160,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h + */ + if ((ctx->gfx_level == GFX11 || ctx->gfx_level == GFX11_5) && ctx->has_tessellation) { + radeon_begin(cs); +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0)); ++ radeon_event_write(V_028A90_SQ_NON_EVENT); + radeon_end(); + } + +@@ -797,10 +796,8 @@ void gfx10_emit_cache_flush(struct si_context *ctx, struct radeon_cmdbuf *cs) + + radeon_begin(cs); + +- if (flags & SI_CONTEXT_VGT_FLUSH) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); +- } ++ if (flags & SI_CONTEXT_VGT_FLUSH) ++ radeon_event_write(V_028A90_VGT_FLUSH); + + if (flags & SI_CONTEXT_INV_ICACHE) + gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL); +@@ -837,19 +834,15 @@ void gfx10_emit_cache_flush(struct si_context *ctx, struct radeon_cmdbuf *cs) + } + + if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) { +- if (ctx->gfx_level < GFX12 && flags & SI_CONTEXT_FLUSH_AND_INV_CB) { +- /* Flush CMASK/FMASK/DCC. Will wait for idle later. */ +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); +- } ++ /* Flush CMASK/FMASK/DCC. Will wait for idle later. */ ++ if (ctx->gfx_level < GFX12 && flags & SI_CONTEXT_FLUSH_AND_INV_CB) ++ radeon_event_write(V_028A90_FLUSH_AND_INV_CB_META); + + /* Gfx11 can't flush DB_META and should use a TS event instead. */ ++ /* Flush HTILE. Will wait for idle later. */ + if (ctx->gfx_level < GFX12 && ctx->gfx_level != GFX11 && +- flags & SI_CONTEXT_FLUSH_AND_INV_DB) { +- /* Flush HTILE. Will wait for idle later. */ +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); +- } ++ flags & SI_CONTEXT_FLUSH_AND_INV_DB) ++ radeon_event_write(V_028A90_FLUSH_AND_INV_DB_META); + + /* First flush CB/DB, then L1/L2. */ + gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD); +@@ -870,21 +863,18 @@ void gfx10_emit_cache_flush(struct si_context *ctx, struct radeon_cmdbuf *cs) + } else { + /* Wait for graphics shaders to go idle if requested. */ + if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); ++ radeon_event_write(V_028A90_PS_PARTIAL_FLUSH); + /* Only count explicit shader flushes, not implicit ones. */ + ctx->num_vs_flushes++; + ctx->num_ps_flushes++; + } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); ++ radeon_event_write(V_028A90_VS_PARTIAL_FLUSH); + ctx->num_vs_flushes++; + } + } + + if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4))); ++ radeon_event_write(V_028A90_CS_PARTIAL_FLUSH); + ctx->num_cs_flushes++; + ctx->compute_is_busy = false; + } +@@ -1026,12 +1016,10 @@ void gfx10_emit_cache_flush(struct si_context *ctx, struct radeon_cmdbuf *cs) + } + + if (flags & SI_CONTEXT_START_PIPELINE_STATS && ctx->pipeline_stats_enabled != 1) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); ++ radeon_event_write(V_028A90_PIPELINESTAT_START); + ctx->pipeline_stats_enabled = 1; + } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS && ctx->pipeline_stats_enabled != 0) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); ++ radeon_event_write(V_028A90_PIPELINESTAT_STOP); + ctx->pipeline_stats_enabled = 0; + } + radeon_end(); +@@ -1092,16 +1080,13 @@ void gfx6_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs) + + radeon_begin(cs); + +- if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) { +- /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */ +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); +- } +- if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_FLUSH_AND_INV_DB_META)) { +- /* Flush HTILE. SURFACE_SYNC will wait for idle. */ +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); +- } ++ /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */ ++ if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) ++ radeon_event_write(V_028A90_FLUSH_AND_INV_CB_META); ++ ++ /* Flush HTILE. SURFACE_SYNC will wait for idle. */ ++ if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_FLUSH_AND_INV_DB_META)) ++ radeon_event_write(V_028A90_FLUSH_AND_INV_DB_META); + + /* Wait for shader engines to go idle. + * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait +@@ -1109,36 +1094,28 @@ void gfx6_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs) + */ + if (!flush_cb_db) { + if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); +- /* Only count explicit shader flushes, not implicit ones +- * done by SURFACE_SYNC. +- */ ++ radeon_event_write(V_028A90_PS_PARTIAL_FLUSH); ++ /* Only count explicit shader flushes, not implicit ones done by SURFACE_SYNC. */ + sctx->num_vs_flushes++; + sctx->num_ps_flushes++; + } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); ++ radeon_event_write(V_028A90_VS_PARTIAL_FLUSH); + sctx->num_vs_flushes++; + } + } + + if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && sctx->compute_is_busy) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); ++ radeon_event_write(V_028A90_CS_PARTIAL_FLUSH); + sctx->num_cs_flushes++; + sctx->compute_is_busy = false; + } + + /* VGT state synchronization. */ +- if (flags & SI_CONTEXT_VGT_FLUSH) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); +- } +- if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0)); +- } ++ if (flags & SI_CONTEXT_VGT_FLUSH) ++ radeon_event_write(V_028A90_VGT_FLUSH); ++ ++ if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) ++ radeon_event_write(V_028A90_VGT_STREAMOUT_SYNC); + + radeon_end(); + +@@ -1267,14 +1244,12 @@ void gfx6_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs) + + if (flags & SI_CONTEXT_START_PIPELINE_STATS && sctx->pipeline_stats_enabled != 1) { + radeon_begin(cs); +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); ++ radeon_event_write(V_028A90_PIPELINESTAT_START); + radeon_end(); + sctx->pipeline_stats_enabled = 1; + } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS && sctx->pipeline_stats_enabled != 0) { + radeon_begin(cs); +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); ++ radeon_event_write(V_028A90_PIPELINESTAT_STOP); + radeon_end(); + sctx->pipeline_stats_enabled = 0; + } +diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c +index 9cbd08648af..785c98a9dc9 100644 +--- a/src/gallium/drivers/radeonsi/si_perfcounter.c ++++ b/src/gallium/drivers/radeonsi/si_perfcounter.c +@@ -114,8 +114,7 @@ static void si_pc_emit_start(struct si_context *sctx, struct si_resource *buffer + radeon_begin(cs); + radeon_set_uconfig_reg(R_036020_CP_PERFMON_CNTL, + S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_DISABLE_AND_RESET)); +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_PERFCOUNTER_START) | EVENT_INDEX(0)); ++ radeon_event_write(V_028A90_PERFCOUNTER_STOP); + radeon_set_uconfig_reg(R_036020_CP_PERFMON_CNTL, + S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_START_COUNTING)); + radeon_end(); +@@ -132,13 +131,10 @@ static void si_pc_emit_stop(struct si_context *sctx, struct si_resource *buffer, + si_cp_wait_mem(sctx, cs, va, 0, 0xffffffff, WAIT_REG_MEM_EQUAL); + + radeon_begin(cs); +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0)); ++ radeon_event_write(V_028A90_PERFCOUNTER_SAMPLE); + +- if (!sctx->screen->info.never_send_perfcounter_stop) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0)); +- } ++ if (!sctx->screen->info.never_send_perfcounter_stop) ++ radeon_event_write(V_028A90_PERFCOUNTER_STOP); + + radeon_set_uconfig_reg( + R_036020_CP_PERFMON_CNTL, +@@ -158,8 +154,7 @@ void si_pc_emit_spm_start(struct radeon_cmdbuf *cs) + S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_DISABLE_AND_RESET) | + S_036020_SPM_PERFMON_STATE(V_036020_STRM_PERFMON_STATE_START_COUNTING)); + /* Start windowed performance counters. */ +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_PERFCOUNTER_START) | EVENT_INDEX(0)); ++ radeon_event_write(V_028A90_PERFCOUNTER_START); + radeon_set_sh_reg(R_00B82C_COMPUTE_PERFCOUNT_ENABLE, S_00B82C_PERFCOUNT_ENABLE(1)); + + radeon_end(); +@@ -171,10 +166,8 @@ void si_pc_emit_spm_stop(struct radeon_cmdbuf *cs, bool never_stop_sq_perf_count + radeon_begin(cs); + + /* Stop windowed performance counters. */ +- if (!never_send_perfcounter_stop) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0)); +- } ++ if (!never_send_perfcounter_stop) ++ radeon_event_write(V_028A90_PERFCOUNTER_STOP); + + radeon_set_sh_reg(R_00B82C_COMPUTE_PERFCOUNT_ENABLE, S_00B82C_PERFCOUNT_ENABLE(0)); + +diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c +index 18c19b58063..eca647505ae 100644 +--- a/src/gallium/drivers/radeonsi/si_query.c ++++ b/src/gallium/drivers/radeonsi/si_query.c +@@ -980,8 +980,7 @@ static void si_query_hw_do_emit_stop(struct si_context *sctx, struct si_query_hw + + radeon_begin(cs); + if (sctx->screen->use_ngg && query->flags & SI_QUERY_EMULATE_GS_COUNTERS) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); ++ radeon_event_write(V_028A90_VS_PARTIAL_FLUSH); + + if (--sctx->num_pipeline_stat_emulated_queries == 0) { + si_set_internal_shader_buffer(sctx, SI_GS_QUERY_BUF, NULL); +diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c +index 018be3dbe4f..8af8bae58ae 100644 +--- a/src/gallium/drivers/radeonsi/si_state.c ++++ b/src/gallium/drivers/radeonsi/si_state.c +@@ -62,8 +62,7 @@ static void si_emit_cb_render_state(struct si_context *sctx, unsigned index) + sctx->last_cb_target_mask = cb_target_mask; + + radeon_begin(cs); +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); ++ radeon_event_write(V_028A90_BREAK_BATCH); + radeon_end(); + } + +@@ -3191,10 +3190,9 @@ static void gfx6_emit_framebuffer_state(struct si_context *sctx, unsigned index) + S_028208_BR_X(state->width) | S_028208_BR_Y(state->height)); + + if (sctx->screen->dpbb_allowed && +- sctx->screen->pbb_context_states_per_bin > 1) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); +- } ++ sctx->screen->pbb_context_states_per_bin > 1) ++ radeon_event_write(V_028A90_BREAK_BATCH); ++ + radeon_end(); + + si_update_display_dcc_dirty(sctx); +@@ -3341,10 +3339,9 @@ static void gfx11_dgpu_emit_framebuffer_state(struct si_context *sctx, unsigned + gfx11_end_packed_context_regs(); + + if (sctx->screen->dpbb_allowed && +- sctx->screen->pbb_context_states_per_bin > 1) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); +- } ++ sctx->screen->pbb_context_states_per_bin > 1) ++ radeon_event_write(V_028A90_BREAK_BATCH); ++ + radeon_end(); + + si_update_display_dcc_dirty(sctx); +@@ -3478,10 +3475,9 @@ static void gfx12_emit_framebuffer_state(struct si_context *sctx, unsigned index + gfx12_end_context_regs(); + + if (sctx->screen->dpbb_allowed && +- sctx->screen->pbb_context_states_per_bin > 1) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); +- } ++ sctx->screen->pbb_context_states_per_bin > 1) ++ radeon_event_write(V_028A90_BREAK_BATCH); ++ + radeon_end(); + + sctx->framebuffer.dirty_cbufs = 0; +diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp +index bd2c936306b..81565b7694e 100644 +--- a/src/gallium/drivers/radeonsi/si_state_draw.cpp ++++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp +@@ -1212,16 +1212,6 @@ void si_emit_buffered_compute_sh_regs(struct si_context *sctx) + + #endif + +-#define EMIT_SQTT_END_DRAW \ +- do { \ +- if (GFX_VERSION >= GFX9 && unlikely(sctx->sqtt_enabled)) { \ +- radeon_begin(&sctx->gfx_cs); \ +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); \ +- radeon_emit(EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0)); \ +- radeon_end(); \ +- } \ +- } while (0) +- + template ALWAYS_INLINE + static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw_info *info, +@@ -1638,10 +1628,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw + radeon_emit(0); + radeon_emit(V_0287F0_DI_SRC_SEL_AUTO_INDEX | use_opaque); + +- for (unsigned i = 0; i < 3; i++) { +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0)); +- } ++ for (unsigned i = 0; i < 3; i++) ++ radeon_event_write(V_028A90_SQ_NON_EVENT); + } else if (increment_draw_id) { + for (unsigned i = 0; i < num_draws; i++) { + if (i > 0) { +@@ -1675,9 +1663,10 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw + } + } + } +- radeon_end(); + +- EMIT_SQTT_END_DRAW; ++ if (GFX_VERSION >= GFX9 && unlikely(sctx->sqtt_enabled)) ++ radeon_event_write(V_028A90_THREAD_TRACE_MARKER); ++ radeon_end(); + } + + /* Return false if not bound. */ +diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp +index 3eb56675313..a3a1b613337 100644 +--- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp ++++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp +@@ -4081,12 +4081,10 @@ static void si_emit_vgt_flush(struct radeon_cmdbuf *cs) + radeon_begin(cs); + + /* This is required before VGT_FLUSH. */ +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); ++ radeon_event_write(V_028A90_VS_PARTIAL_FLUSH); + + /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */ +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); ++ radeon_event_write(V_028A90_VGT_FLUSH); + radeon_end(); + } + +@@ -4973,11 +4971,8 @@ static void si_emit_spi_ge_ring_state(struct si_context *sctx, unsigned index) + + radeon_begin(&sctx->gfx_cs); + /* Required before writing tessellation config registers. */ +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); +- +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); ++ radeon_event_write(V_028A90_VS_PARTIAL_FLUSH); ++ radeon_event_write(V_028A90_VGT_FLUSH); + + if (sctx->gfx_level >= GFX7) { + radeon_set_uconfig_reg_seq(R_030938_VGT_TF_RING_SIZE, 3); +diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c +index 8047965ff84..9a92b4a4f3d 100644 +--- a/src/gallium/drivers/radeonsi/si_state_streamout.c ++++ b/src/gallium/drivers/radeonsi/si_state_streamout.c +@@ -259,8 +259,7 @@ static void si_flush_vgt_streamout(struct si_context *sctx) + radeon_set_config_reg(reg_strmout_cntl, 0); + } + +- radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); +- radeon_emit(EVENT_TYPE(V_028A90_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); ++ radeon_event_write(V_028A90_SO_VGTSTREAMOUT_FLUSH); + + radeon_emit(PKT3(PKT3_WAIT_REG_MEM, 5, 0)); + radeon_emit(WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */ +-- +2.48.1 + + +From eefc15a11186a5b806ed5b2fcfbd2c9e1ad3d8e9 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= +Date: Mon, 16 Dec 2024 03:59:13 -0500 +Subject: [PATCH 05/27] radeonsi/gfx12: adjust HiZ/HiS logic + +Acked-by: Pierre-Eric Pelloux-Prayer +Part-of: +--- + src/amd/common/ac_gpu_info.c | 1 + + src/amd/common/ac_surface.c | 8 ++- + src/gallium/drivers/radeonsi/si_build_pm4.h | 14 +++++ + .../drivers/radeonsi/si_debug_options.h | 1 + + src/gallium/drivers/radeonsi/si_pipe.h | 1 + + src/gallium/drivers/radeonsi/si_state.c | 51 ++++++++++++---- + .../drivers/radeonsi/si_state_draw.cpp | 61 +++++++++++++++---- + 7 files changed, 110 insertions(+), 27 deletions(-) + +diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c +index 0d475cdab63..dd43af8dbb6 100644 +--- a/src/amd/common/ac_gpu_info.c ++++ b/src/amd/common/ac_gpu_info.c +@@ -593,6 +593,7 @@ static void handle_env_var_force_family(struct radeon_info *info) + info->gfx_level = ac_get_gfx_level(i); + info->family_id = ac_get_family_id(i); + info->family_overridden = true; ++ info->chip_rev = 1; + return; + } + } +diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c +index 69f722bc4cc..66d773921c4 100644 +--- a/src/amd/common/ac_surface.c ++++ b/src/amd/common/ac_surface.c +@@ -3022,7 +3022,7 @@ static bool gfx12_compute_hiz_his_info(struct ac_addrlib *addrlib, const struct + { + assert(surf_in->flags.depth != surf_in->flags.stencil); + +- if (surf->flags & RADEON_SURF_NO_HTILE || (info->gfx_level == GFX12 && info->chip_rev <= 1)) ++ if (surf->flags & RADEON_SURF_NO_HTILE || (info->gfx_level == GFX12 && info->chip_rev == 0)) + return true; + + ADDR3_COMPUTE_SURFACE_INFO_OUTPUT out = {0}; +@@ -3079,7 +3079,11 @@ static bool gfx12_compute_miptree(struct ac_addrlib *addrlib, const struct radeo + surf->surf_alignment_log2 = MAX2(surf->surf_alignment_log2, util_logbase2(out.baseAlign)); + surf->surf_size = surf->u.gfx9.zs.stencil_offset + out.surfSize; + +- return gfx12_compute_hiz_his_info(addrlib, info, surf, &surf->u.gfx9.zs.his, in); ++ if (info->chip_rev >= 2 && ++ !gfx12_compute_hiz_his_info(addrlib, info, surf, &surf->u.gfx9.zs.his, in)) ++ return false; ++ ++ return true; + } + + surf->u.gfx9.surf_slice_size = out.sliceSize; +diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h +index 630b5885ff3..c792d0fd2f8 100644 +--- a/src/gallium/drivers/radeonsi/si_build_pm4.h ++++ b/src/gallium/drivers/radeonsi/si_build_pm4.h +@@ -514,6 +514,20 @@ + __event_type == V_028A90_PIXEL_PIPE_STAT_CONTROL ? 1 : 0)); \ + } while (0) + ++#define radeon_emit_alt_hiz_logic() do { \ ++ static_assert(GFX_VERSION == GFX12 || !ALT_HIZ_LOGIC, ""); \ ++ if (GFX_VERSION == GFX12 && ALT_HIZ_LOGIC) { \ ++ radeon_emit(PKT3(PKT3_RELEASE_MEM, 6, 0)); \ ++ radeon_emit(S_490_EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | S_490_EVENT_INDEX(5)); \ ++ radeon_emit(0); /* DST_SEL, INT_SEL = no write confirm, DATA_SEL = no data */ \ ++ radeon_emit(0); /* ADDRESS_LO */ \ ++ radeon_emit(0); /* ADDRESS_HI */ \ ++ radeon_emit(0); /* DATA_LO */ \ ++ radeon_emit(0); /* DATA_HI */ \ ++ radeon_emit(0); /* INT_CTXID */ \ ++ } \ ++} while (0) ++ + /* This should be evaluated at compile time if all parameters are constants. */ + static ALWAYS_INLINE unsigned + si_get_user_data_base(enum amd_gfx_level gfx_level, enum si_has_tess has_tess, +diff --git a/src/gallium/drivers/radeonsi/si_debug_options.h b/src/gallium/drivers/radeonsi/si_debug_options.h +index ba2c2336ee0..a5057c4700e 100644 +--- a/src/gallium/drivers/radeonsi/si_debug_options.h ++++ b/src/gallium/drivers/radeonsi/si_debug_options.h +@@ -23,6 +23,7 @@ OPT_BOOL(zerovram, false, "Zero all VRAM allocations") + OPT_BOOL(clear_lds, false, "Clear LDS at the end of shaders. Might decrease performance.") + OPT_BOOL(cache_rb_gl2, false, "Enable GL2 caching for CB and DB.") + OPT_BOOL(optimize_io, true, "Run nir_opt_varyings in the GLSL linker.") ++OPT_BOOL(alt_hiz_logic, false, "Enable alternative HiZ logic") + + #undef OPT_BOOL + #undef OPT_INT +diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h +index a7f5b544051..0002a3056c9 100644 +--- a/src/gallium/drivers/radeonsi/si_pipe.h ++++ b/src/gallium/drivers/radeonsi/si_pipe.h +@@ -398,6 +398,7 @@ struct si_texture { + bool can_sample_z : 1; + bool can_sample_s : 1; + bool need_flush_after_depth_decompression: 1; ++ bool force_disable_hiz_his : 1; + + /* We need to track DCC dirtiness, because st/dri usually calls + * flush_resource twice per frame (not a bug) and we don't wanna +diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c +index 8af8bae58ae..a647defc26c 100644 +--- a/src/gallium/drivers/radeonsi/si_state.c ++++ b/src/gallium/drivers/radeonsi/si_state.c +@@ -1713,6 +1713,20 @@ static void si_bind_dsa_state(struct pipe_context *ctx, void *state) + si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref); + } + ++ struct pipe_surface *zssurf = sctx->framebuffer.state.zsbuf; ++ struct si_texture *zstex = (struct si_texture*)(zssurf ? zssurf->texture : NULL); ++ ++ if (sctx->gfx_level == GFX12 && !sctx->screen->options.alt_hiz_logic && ++ sctx->framebuffer.has_stencil && dsa->stencil_enabled && !zstex->force_disable_hiz_his) { ++ zstex->force_disable_hiz_his = true; ++ si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer); ++ ++ if (sctx->framebuffer.has_hiz_his) { ++ sctx->framebuffer.has_hiz_his = false; ++ si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config); ++ } ++ } ++ + if (old_dsa->alpha_func != dsa->alpha_func) { + si_ps_key_update_dsa(sctx); + si_update_ps_inputs_read_or_disabled(sctx); +@@ -2814,9 +2828,14 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, + if (util_format_has_stencil(util_format_description(zstex->buffer.b.b.format))) + sctx->framebuffer.has_stencil = true; + ++ if (sctx->gfx_level == GFX12 && !sctx->screen->options.alt_hiz_logic && ++ sctx->framebuffer.has_stencil && sctx->queued.named.dsa->stencil_enabled) ++ zstex->force_disable_hiz_his = true; ++ + if (sctx->gfx_level >= GFX12) { +- sctx->framebuffer.has_hiz_his = zstex->surface.u.gfx9.zs.hiz.offset || +- zstex->surface.u.gfx9.zs.his.offset; ++ sctx->framebuffer.has_hiz_his = (zstex->surface.u.gfx9.zs.hiz.offset || ++ zstex->surface.u.gfx9.zs.his.offset) && ++ !zstex->force_disable_hiz_his; + } + } + +@@ -3443,18 +3462,24 @@ static void gfx12_emit_framebuffer_state(struct si_context *sctx, unsigned index + gfx12_set_context_reg(R_028034_DB_STENCIL_READ_BASE_HI, zb->ds.db_stencil_base >> 32); + gfx12_set_context_reg(R_028038_DB_STENCIL_WRITE_BASE, zb->ds.db_stencil_base); + gfx12_set_context_reg(R_02803C_DB_STENCIL_WRITE_BASE_HI, zb->ds.db_stencil_base >> 32); +- gfx12_set_context_reg(R_028B94_PA_SC_HIZ_INFO, zb->ds.u.gfx12.hiz_info); +- gfx12_set_context_reg(R_028B98_PA_SC_HIS_INFO, zb->ds.u.gfx12.his_info); + +- if (zb->ds.u.gfx12.hiz_info) { +- gfx12_set_context_reg(R_028B9C_PA_SC_HIZ_BASE, zb->ds.u.gfx12.hiz_base); +- gfx12_set_context_reg(R_028BA0_PA_SC_HIZ_BASE_EXT, zb->ds.u.gfx12.hiz_base >> 32); +- gfx12_set_context_reg(R_028BA4_PA_SC_HIZ_SIZE_XY, zb->ds.u.gfx12.hiz_size_xy); +- } +- if (zb->ds.u.gfx12.his_info) { +- gfx12_set_context_reg(R_028BA8_PA_SC_HIS_BASE, zb->ds.u.gfx12.his_base); +- gfx12_set_context_reg(R_028BAC_PA_SC_HIS_BASE_EXT, zb->ds.u.gfx12.his_base >> 32); +- gfx12_set_context_reg(R_028BB0_PA_SC_HIS_SIZE_XY, zb->ds.u.gfx12.his_size_xy); ++ if (tex->force_disable_hiz_his) { ++ gfx12_set_context_reg(R_028B94_PA_SC_HIZ_INFO, S_028B94_SURFACE_ENABLE(0)); ++ gfx12_set_context_reg(R_028B98_PA_SC_HIS_INFO, S_028B98_SURFACE_ENABLE(0)); ++ } else { ++ gfx12_set_context_reg(R_028B94_PA_SC_HIZ_INFO, zb->ds.u.gfx12.hiz_info); ++ gfx12_set_context_reg(R_028B98_PA_SC_HIS_INFO, zb->ds.u.gfx12.his_info); ++ ++ if (zb->ds.u.gfx12.hiz_info) { ++ gfx12_set_context_reg(R_028B9C_PA_SC_HIZ_BASE, zb->ds.u.gfx12.hiz_base); ++ gfx12_set_context_reg(R_028BA0_PA_SC_HIZ_BASE_EXT, zb->ds.u.gfx12.hiz_base >> 32); ++ gfx12_set_context_reg(R_028BA4_PA_SC_HIZ_SIZE_XY, zb->ds.u.gfx12.hiz_size_xy); ++ } ++ if (zb->ds.u.gfx12.his_info) { ++ gfx12_set_context_reg(R_028BA8_PA_SC_HIS_BASE, zb->ds.u.gfx12.his_base); ++ gfx12_set_context_reg(R_028BAC_PA_SC_HIS_BASE_EXT, zb->ds.u.gfx12.his_base >> 32); ++ gfx12_set_context_reg(R_028BB0_PA_SC_HIS_SIZE_XY, zb->ds.u.gfx12.his_size_xy); ++ } + } + } else if (sctx->framebuffer.dirty_zsbuf) { + gfx12_set_context_reg(R_028018_DB_Z_INFO, +diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp +index 81565b7694e..bc4cf308936 100644 +--- a/src/gallium/drivers/radeonsi/si_state_draw.cpp ++++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp +@@ -823,6 +823,11 @@ enum si_has_sh_pairs_packed { + HAS_SH_PAIRS_PACKED_ON, + }; + ++enum si_alt_hiz_logic { ++ ALT_HIZ_LOGIC_OFF, ++ ALT_HIZ_LOGIC_ON, ++}; ++ + template ALWAYS_INLINE + static bool num_instanced_prims_less_than(const struct pipe_draw_indirect_info *indirect, + enum mesa_prim prim, +@@ -1213,7 +1218,8 @@ void si_emit_buffered_compute_sh_regs(struct si_context *sctx) + #endif + + template ALWAYS_INLINE ++ si_is_draw_vertex_state IS_DRAW_VERTEX_STATE, si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED, ++ si_alt_hiz_logic ALT_HIZ_LOGIC> ALWAYS_INLINE + static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw_info *info, + unsigned drawid_base, + const struct pipe_draw_indirect_info *indirect, +@@ -1405,6 +1411,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw + radeon_emit((sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); + radeon_emit((sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); + radeon_emit(di_src_sel); ++ ++ radeon_emit_alt_hiz_logic(); + } else { + uint64_t count_va = 0; + +@@ -1430,6 +1438,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw + radeon_emit(count_va >> 32); + radeon_emit(indirect->stride); + radeon_emit(di_src_sel); ++ ++ radeon_emit_alt_hiz_logic(); + } + } else { + if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN || +@@ -1549,6 +1559,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw + radeon_emit(va >> 32); + radeon_emit(draws[i].count); + radeon_emit(V_0287F0_DI_SRC_SEL_DMA); /* NOT_EOP disabled */ ++ ++ radeon_emit_alt_hiz_logic(); + } + if (num_draws > 1) { + BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */ +@@ -1568,6 +1580,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw + radeon_emit(va >> 32); + radeon_emit(draws[i].count); + radeon_emit(V_0287F0_DI_SRC_SEL_DMA); /* NOT_EOP disabled */ ++ ++ radeon_emit_alt_hiz_logic(); + } + if (num_draws > 1) { + BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg + 1); /* DrawID */ +@@ -1588,6 +1602,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw + radeon_emit(va >> 32); + radeon_emit(draws[i].count); + radeon_emit(V_0287F0_DI_SRC_SEL_DMA); /* NOT_EOP disabled */ ++ ++ radeon_emit_alt_hiz_logic(); + } + if (num_draws > 1) { + BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */ +@@ -1615,6 +1631,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw + radeon_emit(V_0287F0_DI_SRC_SEL_DMA | + S_0287F0_NOT_EOP(GFX_VERSION >= GFX10 && GFX_VERSION < GFX12 && + i < num_draws - 1)); ++ ++ radeon_emit_alt_hiz_logic(); + } + } + } +@@ -1628,6 +1646,7 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw + radeon_emit(0); + radeon_emit(V_0287F0_DI_SRC_SEL_AUTO_INDEX | use_opaque); + ++ radeon_emit_alt_hiz_logic(); + for (unsigned i = 0; i < 3; i++) + radeon_event_write(V_028A90_SQ_NON_EVENT); + } else if (increment_draw_id) { +@@ -1643,6 +1662,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw + radeon_emit(PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit)); + radeon_emit(draws[i].count); + radeon_emit(V_0287F0_DI_SRC_SEL_AUTO_INDEX | use_opaque); ++ ++ radeon_emit_alt_hiz_logic(); + } + if (num_draws > 1 && (IS_DRAW_VERTEX_STATE || !sctx->num_vs_blit_sgprs)) { + BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */ +@@ -1656,6 +1677,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw + radeon_emit(PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit)); + radeon_emit(draws[i].count); + radeon_emit(V_0287F0_DI_SRC_SEL_AUTO_INDEX | use_opaque); ++ ++ radeon_emit_alt_hiz_logic(); + } + if (num_draws > 1 && (IS_DRAW_VERTEX_STATE || !sctx->num_vs_blit_sgprs)) { + BITSET_CLEAR(sctx->tracked_regs.reg_saved_mask, tracked_base_vertex_reg); /* BaseVertex */ +@@ -2012,7 +2035,7 @@ static void si_emit_all_states(struct si_context *sctx, uint64_t skip_atom_mask) + + template ALWAYS_INLINE ++ util_popcnt POPCNT, si_alt_hiz_logic ALT_HIZ_LOGIC> ALWAYS_INLINE + static void si_draw(struct pipe_context *ctx, + const struct pipe_draw_info *info, + unsigned drawid_offset, +@@ -2312,7 +2335,8 @@ static void si_draw(struct pipe_context *ctx, + return; + } + +- si_emit_draw_packets ++ si_emit_draw_packets + (sctx, info, drawid_offset, indirect, draws, num_draws, indexbuf, + index_size, index_offset, instance_count); + /* <-- CUs start to get busy here if we waited. */ +@@ -2362,7 +2386,7 @@ static void si_draw(struct pipe_context *ctx, + } + + template ++ si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED, si_alt_hiz_logic ALT_HIZ_LOGIC> + static void si_draw_vbo(struct pipe_context *ctx, + const struct pipe_draw_info *info, + unsigned drawid_offset, +@@ -2370,12 +2394,14 @@ static void si_draw_vbo(struct pipe_context *ctx, + const struct pipe_draw_start_count_bias *draws, + unsigned num_draws) + { +- si_draw ++ si_draw + (ctx, info, drawid_offset, indirect, draws, num_draws, NULL, 0); + } + + template ++ si_has_sh_pairs_packed HAS_SH_PAIRS_PACKED, util_popcnt POPCNT, ++ si_alt_hiz_logic ALT_HIZ_LOGIC> + static void si_draw_vertex_state(struct pipe_context *ctx, + struct pipe_vertex_state *vstate, + uint32_t partial_velem_mask, +@@ -2391,7 +2417,8 @@ static void si_draw_vertex_state(struct pipe_context *ctx, + dinfo.instance_count = 1; + dinfo.index.resource = state->b.input.indexbuf; + +- si_draw ++ si_draw + (ctx, &dinfo, 0, NULL, draws, num_draws, vstate, partial_velem_mask); + + if (info.take_vertex_state_ownership) +@@ -2453,18 +2480,28 @@ static void si_init_draw_vbo(struct si_context *sctx) + if (!NGG && GFX_VERSION >= GFX11) + return; + +- if (GFX_VERSION >= GFX11 && GFX_VERSION < GFX12 && sctx->screen->info.has_set_sh_pairs_packed) { ++ if (GFX_VERSION == GFX12 && sctx->screen->options.alt_hiz_logic) { ++ sctx->draw_vbo[HAS_TESS][HAS_GS][NGG] = ++ si_draw_vbo; ++ ++ sctx->draw_vertex_state[HAS_TESS][HAS_GS][NGG] = ++ si_draw_vertex_state; ++ } else if (GFX_VERSION >= GFX11 && GFX_VERSION < GFX12 && ++ sctx->screen->info.has_set_sh_pairs_packed) { + sctx->draw_vbo[HAS_TESS][HAS_GS][NGG] = +- si_draw_vbo; ++ si_draw_vbo; + + sctx->draw_vertex_state[HAS_TESS][HAS_GS][NGG] = +- si_draw_vertex_state; ++ si_draw_vertex_state; + } else { + sctx->draw_vbo[HAS_TESS][HAS_GS][NGG] = +- si_draw_vbo; ++ si_draw_vbo; + + sctx->draw_vertex_state[HAS_TESS][HAS_GS][NGG] = +- si_draw_vertex_state; ++ si_draw_vertex_state; + } + } + +-- +2.48.1 + + +From a4f5130de6d737aa1264d3a981f95b81a9f13d05 Mon Sep 17 00:00:00 2001 +From: Pierre-Eric Pelloux-Prayer +Date: Thu, 21 Nov 2024 13:32:55 +0100 +Subject: [PATCH 06/27] radeonsi: disable DCC for PIPE_BIND_USE_FRONT_RENDERING +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Front rendering and (display) DCC are causing artifacts on screen. + +si_texture_get_handle deals with this problem by disabling dcc, but +we can make it simpler by not allocating DCC at all when this flag +is set. + +Reviewed-by: Marek Olšák +Part-of: +--- + src/gallium/drivers/radeonsi/si_texture.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c +index ae65b725600..9cc11a81669 100644 +--- a/src/gallium/drivers/radeonsi/si_texture.c ++++ b/src/gallium/drivers/radeonsi/si_texture.c +@@ -240,6 +240,8 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac + + if (modifier == DRM_FORMAT_MOD_INVALID && + (ptex->bind & PIPE_BIND_CONST_BW || ++ ptex->bind & PIPE_BIND_PROTECTED || ++ ptex->bind & PIPE_BIND_USE_FRONT_RENDERING || + sscreen->debug_flags & DBG(NO_DCC) || + (ptex->bind & PIPE_BIND_SCANOUT && sscreen->debug_flags & DBG(NO_DISPLAY_DCC)))) + flags |= RADEON_SURF_DISABLE_DCC; +@@ -289,6 +291,9 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac + if (ptex->bind & PIPE_BIND_CONST_BW) + flags |= RADEON_SURF_DISABLE_DCC; + ++ if (ptex->bind & PIPE_BIND_USE_FRONT_RENDERING) ++ flags |= RADEON_SURF_DISABLE_DCC; ++ + switch (sscreen->info.gfx_level) { + case GFX8: + /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */ +@@ -1638,6 +1643,20 @@ si_modifier_supports_resource(struct pipe_screen *screen, + struct si_screen *sscreen = (struct si_screen *)screen; + uint32_t max_width, max_height; + ++ if (((templ->bind & PIPE_BIND_LINEAR) || sscreen->debug_flags & DBG(NO_TILING)) && ++ modifier != DRM_FORMAT_MOD_LINEAR) ++ return false; ++ ++ if ((templ->bind & PIPE_BIND_USE_FRONT_RENDERING) && ac_modifier_has_dcc(modifier)) ++ return false; ++ ++ /* Protected content doesn't support DCC on GFX12. */ ++ if (sscreen->info.gfx_level >= GFX12 && templ->bind & PIPE_BIND_PROTECTED && ++ IS_AMD_FMT_MOD(modifier) && ++ AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12 && ++ AMD_FMT_MOD_GET(DCC, modifier)) ++ return false; ++ + ac_modifier_max_extent(&sscreen->info, modifier, &max_width, &max_height); + return templ->width0 <= max_width && templ->height0 <= max_height; + } +-- +2.48.1 + + +From 35435069c1063180814aff055365dce939d95e60 Mon Sep 17 00:00:00 2001 +From: Pierre-Eric Pelloux-Prayer +Date: Wed, 29 Jan 2025 18:10:12 +0100 +Subject: [PATCH 07/27] radeonsi: update si_need_gfx_cs_space upper bound +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +radeon_emit_alt_hiz_logic can add 8 extra dw per draw. + +Fixes: cdecbee9225 ("radeonsi/gfx12: adjust HiZ/HiS logic") +Reviewed-by: Marek Olšák +Part-of: +--- + src/gallium/drivers/radeonsi/si_compute.c | 2 +- + src/gallium/drivers/radeonsi/si_cp_dma.c | 2 +- + src/gallium/drivers/radeonsi/si_perfcounter.c | 2 +- + src/gallium/drivers/radeonsi/si_pipe.h | 12 ++++++++++-- + src/gallium/drivers/radeonsi/si_query.c | 6 +++--- + src/gallium/drivers/radeonsi/si_state_draw.cpp | 2 +- + 6 files changed, 17 insertions(+), 9 deletions(-) + +diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c +index 01aa75d222a..d2c2bc16500 100644 +--- a/src/gallium/drivers/radeonsi/si_compute.c ++++ b/src/gallium/drivers/radeonsi/si_compute.c +@@ -1218,7 +1218,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info + } + } + +- si_need_gfx_cs_space(sctx, 0); ++ si_need_gfx_cs_space(sctx, 0, 0); + + /* If we're using a secure context, determine if cs must be secure or not */ + if (unlikely(radeon_uses_secure_bos(sctx->ws))) { +diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c +index 89ee80e14f5..f0ba0796377 100644 +--- a/src/gallium/drivers/radeonsi/si_cp_dma.c ++++ b/src/gallium/drivers/radeonsi/si_cp_dma.c +@@ -146,7 +146,7 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst + bool *is_first, unsigned *packet_flags) + { + if (!(user_flags & SI_OP_CPDMA_SKIP_CHECK_CS_SPACE)) +- si_need_gfx_cs_space(sctx, 0); ++ si_need_gfx_cs_space(sctx, 0, 0); + + /* This must be done after need_cs_space. */ + if (dst) +diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c +index 785c98a9dc9..806a842a08d 100644 +--- a/src/gallium/drivers/radeonsi/si_perfcounter.c ++++ b/src/gallium/drivers/radeonsi/si_perfcounter.c +@@ -277,7 +277,7 @@ static void si_pc_query_resume(struct si_context *sctx, struct si_query *squery) + + if (!si_query_buffer_alloc(sctx, &query->buffer, NULL, query->result_size)) + return; +- si_need_gfx_cs_space(sctx, 0); ++ si_need_gfx_cs_space(sctx, 0, 0); + + if (query->shaders) + si_pc_emit_shaders(&sctx->gfx_cs, query->shaders); +diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h +index 0002a3056c9..f132e182b4f 100644 +--- a/src/gallium/drivers/radeonsi/si_pipe.h ++++ b/src/gallium/drivers/radeonsi/si_pipe.h +@@ -2026,11 +2026,19 @@ static inline bool util_rast_prim_is_lines_or_triangles(unsigned prim) + return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES | UTIL_ALL_PRIM_TRIANGLE_MODES)) != 0; + } + +-static inline void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws) ++static inline void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws, ++ unsigned extra_dw_per_draw) + { + struct radeon_cmdbuf *cs = &ctx->gfx_cs; ++ /* Don't count the needed CS space exactly and just use an upper bound. ++ * ++ * Also reserve space for stopping queries at the end of IB, because ++ * the number of active queries is unlimited in theory. ++ */ ++ unsigned reserve_dw = 2048 + ctx->num_cs_dw_queries_suspend + ++ num_draws * (10 + extra_dw_per_draw); + +- if (!ctx->ws->cs_check_space(cs, si_get_minimum_num_gfx_cs_dwords(ctx, num_draws))) ++ if (!ctx->ws->cs_check_space(cs, reserve_dw)) + si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL); + } + +diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c +index eca647505ae..67dd732f615 100644 +--- a/src/gallium/drivers/radeonsi/si_query.c ++++ b/src/gallium/drivers/radeonsi/si_query.c +@@ -918,7 +918,7 @@ static void si_query_hw_emit_start(struct si_context *sctx, struct si_query_hw * + si_update_prims_generated_query_state(sctx, query->b.type, 1); + si_update_hw_pipeline_stats(sctx, query->b.type, 1); + +- si_need_gfx_cs_space(sctx, 0); ++ si_need_gfx_cs_space(sctx, 0, 0); + + va = query->buffer.buf->gpu_address + query->buffer.results_end; + si_query_hw_do_emit_start(sctx, query, query->buffer.buf, va); +@@ -1014,7 +1014,7 @@ static void si_query_hw_emit_stop(struct si_context *sctx, struct si_query_hw *q + + /* The queries which need begin already called this in begin_query. */ + if (query->flags & SI_QUERY_HW_FLAG_NO_START) { +- si_need_gfx_cs_space(sctx, 0); ++ si_need_gfx_cs_space(sctx, 0, 0); + if (!si_query_buffer_alloc(sctx, &query->buffer, si_query_hw_prepare_buffer, + query->result_size)) + return; +@@ -1726,7 +1726,7 @@ void si_resume_queries(struct si_context *sctx) + struct si_query *query; + + /* Check CS space here. Resuming must not be interrupted by flushes. */ +- si_need_gfx_cs_space(sctx, 0); ++ si_need_gfx_cs_space(sctx, 0, 0); + + LIST_FOR_EACH_ENTRY (query, &sctx->active_queries, active_list) + query->ops->resume(sctx, query); +diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp +index bc4cf308936..8b57ddb3b70 100644 +--- a/src/gallium/drivers/radeonsi/si_state_draw.cpp ++++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp +@@ -2060,7 +2060,7 @@ static void si_draw(struct pipe_context *ctx, + else if (GFX_VERSION < GFX12) + gfx11_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)); + +- si_need_gfx_cs_space(sctx, num_draws); ++ si_need_gfx_cs_space(sctx, num_draws, ALT_HIZ_LOGIC ? 8 : 0); + + if (u_trace_perfetto_active(&sctx->ds.trace_context)) + trace_si_begin_draw(&sctx->trace); +-- +2.48.1 + + +From 1e95d1b0fec92e3cba014e32ac731705eb6e8425 Mon Sep 17 00:00:00 2001 +From: Samuel Pitoiset +Date: Wed, 15 Jan 2025 12:00:43 +0100 +Subject: [PATCH 08/27] radv: disable GFX12+ support + +It's mostly broken, but 25.0+ should be good enough. + +Signed-off-by: Samuel Pitoiset +Part-of: +--- + src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c +index 6ed5718e695..b6ce7ba6ac5 100644 +--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c ++++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c +@@ -22,12 +22,25 @@ + #include "vk_drm_syncobj.h" + #include "xf86drm.h" + ++static bool ++radv_is_gpu_supported(const struct radeon_info *info) ++{ ++ /* GFX12 isn't supported. */ ++ if (info->gfx_level >= GFX12) ++ return false; ++ ++ return true; ++} ++ + static bool + do_winsys_init(struct radv_amdgpu_winsys *ws, int fd) + { + if (!ac_query_gpu_info(fd, ws->dev, &ws->info, true)) + return false; + ++ if (!radv_is_gpu_supported(&ws->info)) ++ return false; ++ + /* + * Override the max submits on video queues. + * If you submit multiple session contexts in the same IB sequence the +-- +2.48.1 + + +From 317d71daef2588ff76c62aa54a5f1920e717a465 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= +Date: Wed, 18 Dec 2024 19:18:30 -0500 +Subject: [PATCH 09/27] radeonsi: fix a gfx10.3 regression due to a gfx12 + change + +This fixes: + Assertion `!"BITSET_TEST_RANGE: bit range crosses word boundary"' failed. + +Fixes: e3cef02c245 - radeonsi/gfx12: set DB_RENDER_OVERRIDE based on stencil state + +Reviewed-by: Qiang Yu +Part-of: +--- + src/gallium/drivers/radeonsi/si_gfx_cs.c | 7 +++++-- + src/gallium/drivers/radeonsi/si_state.h | 2 +- + 2 files changed, 6 insertions(+), 3 deletions(-) + +diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c +index d8dccd9b008..9782e1afaa1 100644 +--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c ++++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c +@@ -317,7 +317,6 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx) + ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ENA] = 0; + ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR] = 0; + +- ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE] = 0; + ctx->tracked_regs.reg_value[SI_TRACKED_DB_EQAA] = 0; + ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE2] = 0; + ctx->tracked_regs.reg_value[SI_TRACKED_DB_SHADER_CONTROL] = 0; +@@ -368,7 +367,11 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx) + ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2] = 0; + ctx->tracked_regs.reg_value[SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3] = 0; + +- ctx->tracked_regs.reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG] = 0; ++ if (ctx->gfx_level >= GFX12) ++ ctx->tracked_regs.reg_value[SI_TRACKED_DB_RENDER_OVERRIDE] = 0; ++ else ++ ctx->tracked_regs.reg_value[SI_TRACKED_SPI_VS_OUT_CONFIG] = 0; ++ + ctx->tracked_regs.reg_value[SI_TRACKED_VGT_PRIMITIVEID_EN] = 0; + ctx->tracked_regs.reg_value[SI_TRACKED_CB_DCC_CONTROL] = 0; + +diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h +index f964fa21606..75159c475e6 100644 +--- a/src/gallium/drivers/radeonsi/si_state.h ++++ b/src/gallium/drivers/radeonsi/si_state.h +@@ -315,7 +315,6 @@ enum si_tracked_reg + SI_TRACKED_SPI_PS_INPUT_ENA, + SI_TRACKED_SPI_PS_INPUT_ADDR, + +- SI_TRACKED_DB_RENDER_OVERRIDE, + SI_TRACKED_DB_EQAA, + SI_TRACKED_DB_RENDER_OVERRIDE2, + SI_TRACKED_DB_SHADER_CONTROL, +@@ -371,6 +370,7 @@ enum si_tracked_reg + SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3, /* GFX6-10 (GFX11+ can reuse this slot) */ + + SI_TRACKED_SPI_VS_OUT_CONFIG, /* GFX6-11 */ ++ SI_TRACKED_DB_RENDER_OVERRIDE = SI_TRACKED_SPI_VS_OUT_CONFIG, /* GFX12+ (slot reused) */ + SI_TRACKED_VGT_PRIMITIVEID_EN, /* GFX6-11 */ + SI_TRACKED_CB_DCC_CONTROL, /* GFX8-11 */ + SI_TRACKED_DB_STENCIL_READ_MASK, /* GFX12+ */ +-- +2.48.1 + + +From 5e4f6e7f2c644219f998672b90c6de9146ca6952 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= +Date: Wed, 8 Jan 2025 15:00:50 -0500 +Subject: [PATCH 10/27] radeonsi/gfx12: enable alt_hiz_logic + +Reviewed-by: Pierre-Eric Pelloux-Prayer +Part-of: +--- + src/gallium/drivers/radeonsi/si_debug_options.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/gallium/drivers/radeonsi/si_debug_options.h b/src/gallium/drivers/radeonsi/si_debug_options.h +index a5057c4700e..74b9b59a455 100644 +--- a/src/gallium/drivers/radeonsi/si_debug_options.h ++++ b/src/gallium/drivers/radeonsi/si_debug_options.h +@@ -23,7 +23,7 @@ OPT_BOOL(zerovram, false, "Zero all VRAM allocations") + OPT_BOOL(clear_lds, false, "Clear LDS at the end of shaders. Might decrease performance.") + OPT_BOOL(cache_rb_gl2, false, "Enable GL2 caching for CB and DB.") + OPT_BOOL(optimize_io, true, "Run nir_opt_varyings in the GLSL linker.") +-OPT_BOOL(alt_hiz_logic, false, "Enable alternative HiZ logic") ++OPT_BOOL(alt_hiz_logic, true, "Enable alternative HiZ logic") + + #undef OPT_BOOL + #undef OPT_INT +-- +2.48.1 + + +From 074851b27e9b59bf9b450907e3231824495e589a Mon Sep 17 00:00:00 2001 +From: Pierre-Eric Pelloux-Prayer +Date: Mon, 10 Feb 2025 12:27:48 +0100 +Subject: [PATCH 11/27] radeonsi: disable dcc when external shader stores are + used +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +See comment. + +Fixes: 666a6eb871d ("radeonsi/gfx12: disable display dcc for front buffer rendering") +Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12552 +Reviewed-by: Marek Olšák +Part-of: +--- + src/gallium/drivers/radeonsi/si_texture.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c +index 9cc11a81669..54e2bfe7e53 100644 +--- a/src/gallium/drivers/radeonsi/si_texture.c ++++ b/src/gallium/drivers/radeonsi/si_texture.c +@@ -803,10 +803,12 @@ static bool si_texture_get_handle(struct pipe_screen *screen, struct pipe_contex + } + + const bool debug_disable_dcc = sscreen->debug_flags & DBG(NO_EXPORTED_DCC); +- /* Since shader image stores don't support DCC on GFX9 and older, +- * disable it for external clients that want write access. ++ /* Disable DCC for external clients that might use shader image stores. ++ * They don't support DCC on GFX9 and older. GFX10/10.3 is also problematic ++ * if the view formats between clients are incompatible or if DCC clear is ++ * used. + */ +- const bool shader_write = sscreen->info.gfx_level <= GFX9 && ++ const bool shader_write = sscreen->info.gfx_level < GFX11 && + usage & PIPE_HANDLE_USAGE_SHADER_WRITE && + !tex->is_depth && + tex->surface.meta_offset; +-- +2.48.1 + + +From ec81fa2026aa8760158dcf4520bc307f627db40f Mon Sep 17 00:00:00 2001 +From: Rhys Perry +Date: Thu, 25 Jul 2024 21:39:25 +0100 +Subject: [PATCH 12/27] aco: split CounterMap off from VGPRCounterMap + +Signed-off-by: Rhys Perry +Reviewed-by: Georg Lehmann +Part-of: +--- + src/amd/compiler/aco_insert_NOPs.cpp | 38 ++++++++++++++++------------ + 1 file changed, 22 insertions(+), 16 deletions(-) + +diff --git a/src/amd/compiler/aco_insert_NOPs.cpp b/src/amd/compiler/aco_insert_NOPs.cpp +index a6290a7f457..3f4b5d6c85f 100644 +--- a/src/amd/compiler/aco_insert_NOPs.cpp ++++ b/src/amd/compiler/aco_insert_NOPs.cpp +@@ -164,14 +164,14 @@ struct NOP_ctx_gfx10 { + } + }; + +-template struct VGPRCounterMap { ++template struct CounterMap { + public: + int base = 0; +- BITSET_DECLARE(resident, 256); +- int val[256]; ++ BITSET_DECLARE(resident, Size); ++ int val[Size]; + + /* Initializes all counters to Max. */ +- VGPRCounterMap() { BITSET_ZERO(resident); } ++ CounterMap() { BITSET_ZERO(resident); } + + /* Increase all counters, clamping at Max. */ + void inc() { base++; } +@@ -185,11 +185,12 @@ public: + + void set(PhysReg reg, unsigned bytes) + { +- if (reg.reg() < 256) ++ if (reg.reg() < Start) + return; + +- for (unsigned i = 0; i < DIV_ROUND_UP(bytes, 4); i++) +- set(reg.reg() - 256 + i); ++ unsigned size = MIN2(DIV_ROUND_UP(bytes, 4), Start + Size - reg.reg()); ++ for (unsigned i = 0; i < size; i++) ++ set(reg.reg() - Start + i); + } + + /* Reset all counters to Max. */ +@@ -201,11 +202,12 @@ public: + + void reset(PhysReg reg, unsigned bytes) + { +- if (reg.reg() < 256) ++ if (reg.reg() < Start) + return; + +- for (unsigned i = 0; i < DIV_ROUND_UP(bytes, 4); i++) +- BITSET_CLEAR(resident, reg.reg() - 256 + i); ++ unsigned size = MIN2(DIV_ROUND_UP(bytes, 4), Start + Size - reg.reg()); ++ for (unsigned i = 0; i < size; i++) ++ BITSET_CLEAR(resident, reg.reg() - Start + i); + } + + uint8_t get(unsigned idx) +@@ -215,14 +217,14 @@ public: + + uint8_t get(PhysReg reg, unsigned offset = 0) + { +- assert(reg.reg() >= 256); +- return get(reg.reg() - 256 + offset); ++ assert(reg.reg() >= Start); ++ return get(reg.reg() - Start + offset); + } + +- void join_min(const VGPRCounterMap& other) ++ void join_min(const CounterMap& other) + { + unsigned i; +- BITSET_FOREACH_SET (i, other.resident, 256) { ++ BITSET_FOREACH_SET (i, other.resident, Size) { + if (BITSET_TEST(resident, i)) + val[i] = MIN2(val[i] + base, other.val[i] + other.base) - base; + else +@@ -231,13 +233,13 @@ public: + BITSET_OR(resident, resident, other.resident); + } + +- bool operator==(const VGPRCounterMap& other) const ++ bool operator==(const CounterMap& other) const + { + if (!BITSET_EQUAL(resident, other.resident)) + return false; + + unsigned i; +- BITSET_FOREACH_SET (i, other.resident, 256) { ++ BITSET_FOREACH_SET (i, other.resident, Size) { + if (!BITSET_TEST(resident, i)) + return false; + if (val[i] + base != other.val[i] + other.base) +@@ -245,8 +247,12 @@ public: + } + return true; + } ++ ++ unsigned size() const { return Size; } + }; + ++template using VGPRCounterMap = CounterMap<256, 256, Max>; ++ + struct NOP_ctx_gfx11 { + /* VcmpxPermlaneHazard */ + bool has_Vcmpx = false; +-- +2.48.1 + + +From 8cfd8daf2e0ed1783f3aeac6a5274bc70e1d103a Mon Sep 17 00:00:00 2001 +From: Rhys Perry +Date: Thu, 25 Jul 2024 21:36:29 +0100 +Subject: [PATCH 13/27] aco: minor CounterMap::operator== fix + +I don't think this matters for how we use CounterMap::operator==. + +The BITSET_TEST() was unnecessary because of the BITSET_EQUAL above. + +Signed-off-by: Rhys Perry +Reviewed-by: Georg Lehmann +Part-of: +--- + src/amd/compiler/aco_insert_NOPs.cpp | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +diff --git a/src/amd/compiler/aco_insert_NOPs.cpp b/src/amd/compiler/aco_insert_NOPs.cpp +index 3f4b5d6c85f..d6df9190864 100644 +--- a/src/amd/compiler/aco_insert_NOPs.cpp ++++ b/src/amd/compiler/aco_insert_NOPs.cpp +@@ -240,9 +240,7 @@ public: + + unsigned i; + BITSET_FOREACH_SET (i, other.resident, Size) { +- if (!BITSET_TEST(resident, i)) +- return false; +- if (val[i] + base != other.val[i] + other.base) ++ if (MIN2(val[i] + base, Max) != MIN2(other.val[i] + other.base, Max)) + return false; + } + return true; +-- +2.48.1 + + +From 62f14df1ca6435f30e13f44e7246fa763706cd9e Mon Sep 17 00:00:00 2001 +From: Rhys Perry +Date: Thu, 25 Jul 2024 21:40:02 +0100 +Subject: [PATCH 14/27] aco: workaround VALUReadSGPRHazard + +fossil-db (gfx1200): +Totals from 65112 (82.01% of 79395) affected shaders: +Instrs: 41732906 -> 42987198 (+3.01%); split: -0.00%, +3.01% +CodeSize: 222451964 -> 226942644 (+2.02%); split: -0.01%, +2.03% +Latency: 290411063 -> 290944688 (+0.18%); split: -0.00%, +0.18% +InvThroughput: 45854913 -> 45910275 (+0.12%); split: -0.00%, +0.12% + +Signed-off-by: Rhys Perry +Reviewed-by: Georg Lehmann +Part-of: +--- + src/amd/compiler/aco_insert_NOPs.cpp | 91 +++++++++++++++++++++++++--- + 1 file changed, 84 insertions(+), 7 deletions(-) + +diff --git a/src/amd/compiler/aco_insert_NOPs.cpp b/src/amd/compiler/aco_insert_NOPs.cpp +index d6df9190864..1bf53050e78 100644 +--- a/src/amd/compiler/aco_insert_NOPs.cpp ++++ b/src/amd/compiler/aco_insert_NOPs.cpp +@@ -273,6 +273,10 @@ struct NOP_ctx_gfx11 { + /* WMMAHazards */ + std::bitset<256> vgpr_written_by_wmma; + ++ /* VALUReadSGPRHazard */ ++ std::bitset sgpr_read_by_valu; /* SGPR pairs, excluding null, exec, m0 and scc */ ++ CounterMap<0, m0.reg(), 11> sgpr_read_by_valu_then_wr_by_salu; ++ + void join(const NOP_ctx_gfx11& other) + { + has_Vcmpx |= other.has_Vcmpx; +@@ -287,6 +291,8 @@ struct NOP_ctx_gfx11 { + sgpr_read_by_valu_as_lanemask_then_wr_by_salu |= + other.sgpr_read_by_valu_as_lanemask_then_wr_by_salu; + vgpr_written_by_wmma |= other.vgpr_written_by_wmma; ++ sgpr_read_by_valu |= other.sgpr_read_by_valu; ++ sgpr_read_by_valu_then_wr_by_salu.join_min(other.sgpr_read_by_valu_then_wr_by_salu); + } + + bool operator==(const NOP_ctx_gfx11& other) +@@ -302,7 +308,9 @@ struct NOP_ctx_gfx11 { + sgpr_read_by_valu_as_lanemask == other.sgpr_read_by_valu_as_lanemask && + sgpr_read_by_valu_as_lanemask_then_wr_by_salu == + other.sgpr_read_by_valu_as_lanemask_then_wr_by_salu && +- vgpr_written_by_wmma == other.vgpr_written_by_wmma; ++ vgpr_written_by_wmma == other.vgpr_written_by_wmma && ++ sgpr_read_by_valu == other.sgpr_read_by_valu && ++ sgpr_read_by_valu_then_wr_by_salu == other.sgpr_read_by_valu_then_wr_by_salu; + } + }; + +@@ -1527,6 +1535,48 @@ handle_instruction_gfx11(State& state, NOP_ctx_gfx11& ctx, aco_ptr& + } + } + } ++ } else { ++ /* VALUReadSGPRHazard ++ * VALU reads SGPR and later written by SALU cannot safely be read by VALU/SALU. ++ */ ++ if (instr->isVALU() || instr->isSALU()) { ++ unsigned expiry_count = instr->isSALU() ? 10 : 11; ++ for (Operand& op : instr->operands) { ++ if (sa_sdst == 0) ++ break; ++ ++ for (unsigned i = 0; i < op.size(); i++) { ++ unsigned reg = op.physReg() + i; ++ if (reg < ctx.sgpr_read_by_valu_then_wr_by_salu.size() && ++ ctx.sgpr_read_by_valu_then_wr_by_salu.get(reg) < expiry_count) { ++ bld.sopp(aco_opcode::s_waitcnt_depctr, 0xfffe); ++ sa_sdst = 0; ++ break; ++ } ++ } ++ } ++ } ++ ++ if (sa_sdst == 0) ++ ctx.sgpr_read_by_valu_then_wr_by_salu.reset(); ++ else if (instr->isSALU() && !instr->isSOPP()) ++ ctx.sgpr_read_by_valu_then_wr_by_salu.inc(); ++ ++ if (instr->isVALU()) { ++ for (const Operand& op : instr->operands) { ++ for (unsigned i = 0; i < DIV_ROUND_UP(op.size(), 2); i++) { ++ unsigned reg = (op.physReg() / 2) + i; ++ if (reg < ctx.sgpr_read_by_valu.size()) ++ ctx.sgpr_read_by_valu.set(reg); ++ } ++ } ++ } else if (instr->isSALU() && !instr->definitions.empty()) { ++ for (unsigned i = 0; i < instr->definitions[0].size(); i++) { ++ unsigned def_reg = instr->definitions[0].physReg() + i; ++ if ((def_reg / 2) < ctx.sgpr_read_by_valu.size() && ctx.sgpr_read_by_valu[def_reg / 2]) ++ ctx.sgpr_read_by_valu_then_wr_by_salu.set(def_reg); ++ } ++ } + } + + /* LdsDirectVMEMHazard +@@ -1683,6 +1733,15 @@ resolve_all_gfx11(State& state, NOP_ctx_gfx11& ctx, + } + } + ++ /* VALUReadSGPRHazard */ ++ if (state.program->gfx_level >= GFX12) { ++ for (unsigned i = 0; i < ctx.sgpr_read_by_valu_then_wr_by_salu.size(); i++) { ++ if (ctx.sgpr_read_by_valu_then_wr_by_salu.get(i) < 11) ++ waitcnt_depctr &= 0xfffe; ++ } ++ ctx.sgpr_read_by_valu_then_wr_by_salu.reset(); ++ } ++ + /* LdsDirectVMEMHazard */ + if (ctx.vgpr_used_by_vmem_load.any() || ctx.vgpr_used_by_vmem_store.any() || + ctx.vgpr_used_by_ds.any() || ctx.vgpr_used_by_vmem_sample.any() || +@@ -1758,7 +1817,7 @@ handle_block(Program* program, Ctx& ctx, Block& block) + + template Handle, ResolveAll Resolve> + void +-mitigate_hazards(Program* program) ++mitigate_hazards(Program* program, Ctx initial_ctx = Ctx()) + { + std::vector all_ctx(program->blocks.size()); + std::stack> loop_header_indices; +@@ -1767,6 +1826,9 @@ mitigate_hazards(Program* program) + Block& block = program->blocks[i]; + Ctx& ctx = all_ctx[i]; + ++ if (i == 0 || (block.kind & block_kind_resume)) ++ ctx = initial_ctx; ++ + if (block.kind & block_kind_loop_header) { + loop_header_indices.push(i); + } else if (block.kind & block_kind_loop_exit) { +@@ -1864,14 +1926,29 @@ required_export_priority(Program* program) + void + insert_NOPs(Program* program) + { +- if (program->gfx_level >= GFX11) +- mitigate_hazards(program); +- else if (program->gfx_level >= GFX10_3) ++ if (program->gfx_level >= GFX11) { ++ NOP_ctx_gfx11 initial_ctx; ++ ++ bool has_previous_part = ++ program->is_epilog || program->info.vs.has_prolog || program->info.ps.has_prolog || ++ (program->info.merged_shader_compiled_separately && program->stage.sw != SWStage::VS && ++ program->stage.sw != SWStage::TES) || program->stage == raytracing_cs; ++ if (program->gfx_level >= GFX12 && has_previous_part) { ++ /* resolve_all_gfx11 can't resolve VALUReadSGPRHazard entirely. We have to assume that any ++ * SGPR might have been read by VALU if there was a previous shader part. ++ */ ++ initial_ctx.sgpr_read_by_valu.flip(); ++ } ++ ++ mitigate_hazards(program, ++ initial_ctx); ++ } else if (program->gfx_level >= GFX10_3) { + ; /* no hazards/bugs to mitigate */ +- else if (program->gfx_level >= GFX10) ++ } else if (program->gfx_level >= GFX10) { + mitigate_hazards(program); +- else ++ } else { + mitigate_hazards(program); ++ } + + if (program->gfx_level == GFX11_5 && (program->stage.hw == AC_HW_NEXT_GEN_GEOMETRY_SHADER || + program->stage.hw == AC_HW_PIXEL_SHADER)) +-- +2.48.1 + + +From d6d58210c9658d759622022c7d196849c8f4e28d Mon Sep 17 00:00:00 2001 +From: Rhys Perry +Date: Tue, 26 Nov 2024 12:00:35 +0000 +Subject: [PATCH 15/27] aco/gfx12: insert wait between VMEM WaW + +https://github.com/llvm/llvm-project/pull/105549 + +fossil-db (gfx1200): +Totals from 1783 (2.25% of 79395) affected shaders: +Instrs: 7398391 -> 7404566 (+0.08%); split: -0.00%, +0.08% +CodeSize: 38862456 -> 38886364 (+0.06%); split: -0.00%, +0.06% +Latency: 83191513 -> 84211504 (+1.23%); split: -0.00%, +1.23% +InvThroughput: 15185936 -> 15345744 (+1.05%); split: -0.01%, +1.06% + +Signed-off-by: Rhys Perry +Part-of: +--- + src/amd/compiler/aco_insert_waitcnt.cpp | 8 ++++++-- + src/amd/compiler/tests/test_insert_waitcnt.cpp | 5 +++++ + 2 files changed, 11 insertions(+), 2 deletions(-) + +diff --git a/src/amd/compiler/aco_insert_waitcnt.cpp b/src/amd/compiler/aco_insert_waitcnt.cpp +index ae079dcd755..b19f49e8571 100644 +--- a/src/amd/compiler/aco_insert_waitcnt.cpp ++++ b/src/amd/compiler/aco_insert_waitcnt.cpp +@@ -385,9 +385,13 @@ check_instr(wait_ctx& ctx, wait_imm& wait, alu_delay_info& delay, Instruction* i + + wait_imm reg_imm = it->second.imm; + +- /* Vector Memory reads and writes return in the order they were issued */ ++ /* Vector Memory reads and writes decrease the counter in the order they were issued. ++ * Before GFX12, they also write VGPRs in order if they're of the same type. ++ * TODO: We can do this for GFX12 and different types for GFX11 if we know that the two ++ * VMEM loads do not write the same lanes. Since GFX11, we track VMEM operations on the ++ * linear CFG, so this is difficult */ + uint8_t vmem_type = get_vmem_type(ctx.gfx_level, instr); +- if (vmem_type) { ++ if (vmem_type && ctx.gfx_level < GFX12) { + wait_event event = get_vmem_event(ctx, instr, vmem_type); + wait_type type = (wait_type)(ffs(ctx.info->get_counters_for_event(event)) - 1); + if ((it->second.events & ctx.info->events[type]) == event && +diff --git a/src/amd/compiler/tests/test_insert_waitcnt.cpp b/src/amd/compiler/tests/test_insert_waitcnt.cpp +index edc34bfc7f8..c69772c5d05 100644 +--- a/src/amd/compiler/tests/test_insert_waitcnt.cpp ++++ b/src/amd/compiler/tests/test_insert_waitcnt.cpp +@@ -192,6 +192,7 @@ BEGIN_TEST(insert_waitcnt.waw.vmem_types) + + //>> p_unit_test 0 + //! v1: %0:v[4] = buffer_load_dword %0:s[0-3], %0:v[0], 0 ++ //~gfx12! s_wait_loadcnt imm:0 + //! v1: %0:v[4] = buffer_load_dword %0:s[0-3], %0:v[0], 0 + bld.pseudo(aco_opcode::p_unit_test, Operand::c32(0)); + bld.mubuf(aco_opcode::buffer_load_dword, def_v4, desc_s4, op_v0, Operand::zero(), 0, false); +@@ -220,6 +221,7 @@ BEGIN_TEST(insert_waitcnt.waw.vmem_types) + + //>> p_unit_test 3 + //! v1: %0:v[4] = image_sample %0:s[8-15], %0:s[0-3], v1: undef, %0:v[0] 1d ++ //~gfx12! s_wait_samplecnt imm:0 + //! v1: %0:v[4] = image_sample %0:s[8-15], %0:s[0-3], v1: undef, %0:v[0] 1d + bld.reset(program->create_and_insert_block()); + bld.pseudo(aco_opcode::p_unit_test, Operand::c32(3)); +@@ -249,6 +251,7 @@ BEGIN_TEST(insert_waitcnt.waw.vmem_types) + + //>> p_unit_test 6 + //! v1: %0:v[4] = image_bvh64_intersect_ray %0:s[0-3], s4: undef, v1: undef, %0:v[16-26] 1d ++ //~gfx12! s_wait_bvhcnt imm:0 + //! v1: %0:v[4] = image_bvh64_intersect_ray %0:s[0-3], s4: undef, v1: undef, %0:v[16-26] 1d + bld.reset(program->create_and_insert_block()); + bld.pseudo(aco_opcode::p_unit_test, Operand::c32(6)); +@@ -300,6 +303,7 @@ BEGIN_TEST(insert_waitcnt.waw.vmem_types) + //>> BB11 + //! /* logical preds: BB9, BB10, / linear preds: BB9, BB10, / kind: uniform, */ + //! p_unit_test 9 ++ //~gfx12! s_wait_loadcnt imm:0 + //! v1: %0:v[4] = buffer_load_dword %0:s[0-3], %0:v[0], 0 + bld.pseudo(aco_opcode::p_unit_test, Operand::c32(9)); + bld.mubuf(aco_opcode::buffer_load_dword, def_v4, desc_s4, op_v0, Operand::zero(), 0, false); +@@ -326,6 +330,7 @@ BEGIN_TEST(insert_waitcnt.waw.vmem_types) + //! /* logical preds: BB12, BB13, / linear preds: BB12, BB13, / kind: uniform, */ + //! p_unit_test 10 + //~gfx11! s_waitcnt vmcnt(0) ++ //~gfx12! s_wait_loadcnt imm:0 + //~gfx12! s_wait_samplecnt imm:0 + //! v1: %0:v[4] = buffer_load_dword %0:s[0-3], %0:v[0], 0 + bld.pseudo(aco_opcode::p_unit_test, Operand::c32(10)); +-- +2.48.1 + + +From 41edfd3cd9470ab4e54efb0b3af9eab7242f5e5f Mon Sep 17 00:00:00 2001 +From: Rhys Perry +Date: Wed, 27 Nov 2024 14:51:32 +0000 +Subject: [PATCH 16/27] aco: force linear for event_vmem_sample and + event_vmem_bvh + +I don't know if this issue affects GFX12, but workaround it anyway to be +safe. + +fossil-db (gfx1200): +Totals from 3463 (4.36% of 79395) affected shaders: +Instrs: 9794280 -> 9833253 (+0.40%); split: -0.00%, +0.40% +CodeSize: 52306040 -> 52457988 (+0.29%); split: -0.01%, +0.30% +Latency: 90549385 -> 93617517 (+3.39%); split: -0.00%, +3.39% +InvThroughput: 13189030 -> 13602942 (+3.14%); split: -0.00%, +3.14% + +Signed-off-by: Rhys Perry +Reviewed-by: Georg Lehmann +Part-of: +--- + src/amd/compiler/aco_insert_waitcnt.cpp | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/src/amd/compiler/aco_insert_waitcnt.cpp b/src/amd/compiler/aco_insert_waitcnt.cpp +index b19f49e8571..66ce8603ea4 100644 +--- a/src/amd/compiler/aco_insert_waitcnt.cpp ++++ b/src/amd/compiler/aco_insert_waitcnt.cpp +@@ -735,7 +735,8 @@ insert_wait_entry(wait_ctx& ctx, Definition def, wait_event event, uint8_t vmem_ + * Also, follow linear control flow for ALU because it's unlikely that the hardware does per-lane + * dependency checks. + */ +- uint32_t ds_vmem_events = event_lds | event_gds | event_vmem | event_flat; ++ uint32_t ds_vmem_events = ++ event_lds | event_gds | event_vmem | event_vmem_sample | event_vmem_bvh | event_flat; + uint32_t alu_events = event_trans | event_valu | event_salu; + bool force_linear = ctx.gfx_level >= GFX11 && (event & (ds_vmem_events | alu_events)); + +-- +2.48.1 + + +From c56875aa56504eab06cc07245b78f9acfb3a1bf6 Mon Sep 17 00:00:00 2001 +From: Georg Lehmann +Date: Thu, 5 Dec 2024 11:33:08 +0100 +Subject: [PATCH 17/27] aco/gfx12+: do not use v_pack_b32_f16 to pack untyped + data +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +GFX12 removed IEEE_MODE, and made its signalling NaN quieting the default. + +Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12251 +Reviewed-by: Daniel Schürmann +Part-of: +--- + src/amd/compiler/aco_lower_to_hw_instr.cpp | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +diff --git a/src/amd/compiler/aco_lower_to_hw_instr.cpp b/src/amd/compiler/aco_lower_to_hw_instr.cpp +index ed955a32a1e..bceaa0d25e9 100644 +--- a/src/amd/compiler/aco_lower_to_hw_instr.cpp ++++ b/src/amd/compiler/aco_lower_to_hw_instr.cpp +@@ -1562,9 +1562,15 @@ do_pack_2x16(lower_context* ctx, Builder& bld, Definition def, Operand lo, Opera + return; + } + ++ /* v_pack_b32_f16 can be used for bit exact copies if: ++ * - fp16 input denorms are enabled, otherwise they get flushed to zero ++ * - signalling input NaNs are kept, which is the case with IEEE_MODE=0 ++ * GFX12+ always quiets signalling NaNs, IEEE_MODE was removed ++ */ + bool can_use_pack = (ctx->block->fp_mode.denorm16_64 & fp_denorm_keep_in) && + (ctx->program->gfx_level >= GFX10 || +- (ctx->program->gfx_level >= GFX9 && !lo.isLiteral() && !hi.isLiteral())); ++ (ctx->program->gfx_level >= GFX9 && !lo.isLiteral() && !hi.isLiteral())) && ++ ctx->program->gfx_level < GFX12; + + if (can_use_pack) { + Instruction* instr = bld.vop3(aco_opcode::v_pack_b32_f16, def, lo, hi); +-- +2.48.1 + + +From 04d7f9ed9e5b0cd98c32a9d8b35c92698e427dfa Mon Sep 17 00:00:00 2001 +From: Rhys Perry +Date: Wed, 4 Dec 2024 13:36:04 +0000 +Subject: [PATCH 18/27] aco: don't CSE p_shader_cycles_hi_lo_hi + +Signed-off-by: Rhys Perry +Reviewed-by: Georg Lehmann +Fixes: fae2a85d57a4 ("aco/gfx12: implement subgroup shader clock") +Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12243 +Part-of: +--- + src/amd/compiler/aco_opt_value_numbering.cpp | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/amd/compiler/aco_opt_value_numbering.cpp b/src/amd/compiler/aco_opt_value_numbering.cpp +index e040221be61..e0c8eeffbbb 100644 +--- a/src/amd/compiler/aco_opt_value_numbering.cpp ++++ b/src/amd/compiler/aco_opt_value_numbering.cpp +@@ -306,6 +306,7 @@ can_eliminate(aco_ptr& instr) + if (instr->definitions.empty() || instr->opcode == aco_opcode::p_phi || + instr->opcode == aco_opcode::p_linear_phi || + instr->opcode == aco_opcode::p_pops_gfx9_add_exiting_wave_id || ++ instr->opcode == aco_opcode::p_shader_cycles_hi_lo_hi || + instr->definitions[0].isNoCSE()) + return false; + +-- +2.48.1 + + +From 8de2e82ca04d973c70eec66c650809a89000e90d Mon Sep 17 00:00:00 2001 +From: Georg Lehmann +Date: Mon, 9 Dec 2024 13:40:49 +0100 +Subject: [PATCH 19/27] aco/gfx12: don't assume memory operations complete in + order + +Reviewed-by: Rhys Perry +Part-of: +--- + src/amd/compiler/aco_insert_waitcnt.cpp | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/amd/compiler/aco_insert_waitcnt.cpp b/src/amd/compiler/aco_insert_waitcnt.cpp +index 66ce8603ea4..22822d92f24 100644 +--- a/src/amd/compiler/aco_insert_waitcnt.cpp ++++ b/src/amd/compiler/aco_insert_waitcnt.cpp +@@ -449,9 +449,9 @@ perform_barrier(wait_ctx& ctx, wait_imm& imm, memory_sync_info sync, unsigned se + if (bar_scope_lds <= subgroup_scope) + events &= ~event_lds; + +- /* in non-WGP, the L1 (L0 on GFX10+) cache keeps all memory operations ++ /* Until GFX12, in non-WGP, the L1 (L0 on GFX10+) cache keeps all memory operations + * in-order for the same workgroup */ +- if (!ctx.program->wgp_mode && sync.scope <= scope_workgroup) ++ if (ctx.gfx_level < GFX12 && !ctx.program->wgp_mode && sync.scope <= scope_workgroup) + events &= ~(event_vmem | event_vmem_store | event_smem); + + if (events) +-- +2.48.1 + + +From 054163a6be4c130b5a95fb5fa2d39d64ea8ee259 Mon Sep 17 00:00:00 2001 +From: Qiang Yu +Date: Mon, 9 Dec 2024 10:01:21 +0800 +Subject: [PATCH 20/27] aco: enable gfx12 support for radeonsi + +Part-of: +--- + src/amd/compiler/aco_interface.cpp | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/amd/compiler/aco_interface.cpp b/src/amd/compiler/aco_interface.cpp +index ab518aa14ef..8508cc0445e 100644 +--- a/src/amd/compiler/aco_interface.cpp ++++ b/src/amd/compiler/aco_interface.cpp +@@ -422,6 +422,7 @@ aco_is_gpu_supported(const struct radeon_info* info) + case GFX10_3: + case GFX11: + case GFX11_5: ++ case GFX12: + return true; + default: + return false; +-- +2.48.1 + + +From a3006214823ffacb34383fad792b3184a171c135 Mon Sep 17 00:00:00 2001 +From: Samuel Pitoiset +Date: Fri, 3 Jan 2025 08:29:34 -0800 +Subject: [PATCH 21/27] aco: fix VS prologs on GFX12 + +MTBUF/MUBUF instructions must use zero for SOFFSET, use const_offset +instead. + +Signed-off-by: Samuel Pitoiset +Part-of: +--- + .../compiler/aco_instruction_selection.cpp | 30 +++++++++++++++---- + 1 file changed, 25 insertions(+), 5 deletions(-) + +diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp +index 93a88c74d30..5e4806f608f 100644 +--- a/src/amd/compiler/aco_instruction_selection.cpp ++++ b/src/amd/compiler/aco_instruction_selection.cpp +@@ -12903,8 +12903,16 @@ load_unaligned_vs_attrib(Builder& bld, PhysReg dst, Operand desc, Operand index, + } else { + for (unsigned i = 0; i < size; i++) { + Definition def(i ? scratch.advance(i * 4 - 4) : dst, v1); +- bld.mubuf(aco_opcode::buffer_load_ubyte, def, desc, index, Operand::c32(offset + i), 0, +- false, true); ++ unsigned soffset = 0, const_offset = 0; ++ ++ if (bld.program->gfx_level >= GFX12) { ++ const_offset = offset + i; ++ } else { ++ soffset = offset + i; ++ } ++ ++ bld.mubuf(aco_opcode::buffer_load_ubyte, def, desc, index, Operand::c32(soffset), ++ const_offset, false, true); + } + } + +@@ -13082,6 +13090,17 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh + for (unsigned j = 0; j < (vtx_info->chan_byte_size ? vtx_info->num_channels : 1); j++) { + bool post_shuffle = pinfo->post_shuffle & (1u << loc); + unsigned offset = vtx_info->chan_byte_size * (post_shuffle && j < 3 ? 2 - j : j); ++ unsigned soffset = 0, const_offset = 0; ++ ++ /* We need to use soffset on GFX6-7 to avoid being considered ++ * out-of-bounds when offset>=stride. GFX12 doesn't support a ++ * non-zero constant soffset. ++ */ ++ if (program->gfx_level >= GFX12) { ++ const_offset = offset; ++ } else { ++ soffset = offset; ++ } + + if ((pinfo->unaligned_mask & (1u << loc)) && vtx_info->chan_byte_size <= 4) + load_unaligned_vs_attrib(bld, dest.advance(j * 4u), Operand(cur_desc, s4), +@@ -13089,11 +13108,12 @@ select_vs_prolog(Program* program, const struct aco_vs_prolog_info* pinfo, ac_sh + else if (vtx_info->chan_byte_size == 8) + bld.mtbuf(aco_opcode::tbuffer_load_format_xy, + Definition(dest.advance(j * 8u), v2), Operand(cur_desc, s4), +- fetch_index, Operand::c32(offset), dfmt, nfmt, 0, false, true); ++ fetch_index, Operand::c32(soffset), dfmt, nfmt, const_offset, false, ++ true); + else + bld.mtbuf(aco_opcode::tbuffer_load_format_x, Definition(dest.advance(j * 4u), v1), +- Operand(cur_desc, s4), fetch_index, Operand::c32(offset), dfmt, nfmt, +- 0, false, true); ++ Operand(cur_desc, s4), fetch_index, Operand::c32(soffset), dfmt, nfmt, ++ const_offset, false, true); + } + + unsigned slots = vtx_info->chan_byte_size == 8 && vtx_info->num_channels > 2 ? 2 : 1; +-- +2.48.1 + + +From 9aeed54b7f1050648612f59844c4cfbedfe1b182 Mon Sep 17 00:00:00 2001 +From: Samuel Pitoiset +Date: Wed, 8 Jan 2025 02:03:09 -0800 +Subject: [PATCH 22/27] aco: always use ds_bpermute for shuffle/rotate on GFX12 + +ds_bpermute supports both 32 and 64 lanes now. + +Signed-off-by: Samuel Pitoiset +Part-of: +--- + src/amd/compiler/aco_instruction_selection.cpp | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp +index 5e4806f608f..8ab9c18ee2a 100644 +--- a/src/amd/compiler/aco_instruction_selection.cpp ++++ b/src/amd/compiler/aco_instruction_selection.cpp +@@ -189,9 +189,9 @@ emit_bpermute(isel_context* ctx, Builder& bld, Temp index, Temp data) + + return bld.pseudo(aco_opcode::p_bpermute_readlane, bld.def(v1), bld.def(bld.lm), + bld.def(bld.lm, vcc), index_op, input_data); +- } else if (ctx->options->gfx_level >= GFX10 && ctx->program->wave_size == 64) { +- +- /* GFX10 wave64 mode: emulate full-wave bpermute */ ++ } else if (ctx->options->gfx_level >= GFX10 && ctx->options->gfx_level <= GFX11_5 && ++ ctx->program->wave_size == 64) { ++ /* GFX10-11.5 wave64 mode: emulate full-wave bpermute */ + Temp index_is_lo = + bld.vopc(aco_opcode::v_cmp_ge_u32, bld.def(bld.lm), Operand::c32(31u), index); + Builder::Result index_is_lo_split = +@@ -221,7 +221,7 @@ emit_bpermute(isel_context* ctx, Builder& bld, Temp index, Temp data) + same_half); + } + } else { +- /* GFX8-9 or GFX10 wave32: bpermute works normally */ ++ /* wave32 or GFX8-9, GFX12+: bpermute works normally */ + Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand::c32(2u), index); + return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data); + } +@@ -8747,8 +8747,9 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) + Temp tid = emit_mbcnt(ctx, bld.tmp(v1)); + Temp src_lane = bld.vadd32(bld.def(v1), tid, delta); + +- if (ctx->program->gfx_level >= GFX10 && cluster_size == 32) { +- /* ds_bpermute is restricted to 32 lanes on GFX10+. */ ++ if (ctx->program->gfx_level >= GFX10 && ctx->program->gfx_level <= GFX11_5 && ++ cluster_size == 32) { ++ /* ds_bpermute is restricted to 32 lanes on GFX10-GFX11.5. */ + Temp index_x4 = + bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand::c32(2u), src_lane); + tmp = bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, src); +-- +2.48.1 + + +From 4929c358e0d44cb25cb486cc634ee96536a674db Mon Sep 17 00:00:00 2001 +From: Georg Lehmann +Date: Sun, 19 Jan 2025 10:17:12 +0100 +Subject: [PATCH 23/27] aco: update is_dual_issue_capable for gfx11.5+ +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Reviewed-by: Daniel Schürmann +Reviewed-by: Daniel Schürmann +Part-of: +--- + src/amd/compiler/aco_statistics.cpp | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/src/amd/compiler/aco_statistics.cpp b/src/amd/compiler/aco_statistics.cpp +index 552bfd2cee4..00934b89ceb 100644 +--- a/src/amd/compiler/aco_statistics.cpp ++++ b/src/amd/compiler/aco_statistics.cpp +@@ -142,7 +142,12 @@ is_dual_issue_capable(const Program& program, const Instruction& instr) + } + return false; + } +- default: return false; ++ default: ++ if (instr.isVINTERP_INREG()) ++ return program.gfx_level >= GFX11_5; ++ if (instr.isVOPC() && instr_info.classes[(int)instr.opcode] == instr_class::valu32) ++ return program.gfx_level == GFX11_5; ++ return false; + } + } + +-- +2.48.1 + + +From 9f0671af164968432750d7b1be5da6d838765179 Mon Sep 17 00:00:00 2001 +From: Samuel Pitoiset +Date: Thu, 12 Sep 2024 15:46:29 +0200 +Subject: [PATCH 24/27] aco,radv,radeonsi: move has_epilog to the fragment + shader info + +Signed-off-by: Samuel Pitoiset +Part-of: +--- + src/amd/compiler/aco_assembler.cpp | 3 ++- + src/amd/compiler/aco_instruction_selection.cpp | 8 ++++---- + src/amd/compiler/aco_interface.cpp | 2 +- + src/amd/compiler/aco_shader_info.h | 2 +- + src/amd/vulkan/radv_aco_shader_info.h | 2 +- + src/amd/vulkan/radv_cmd_buffer.c | 6 +++--- + src/amd/vulkan/radv_pipeline.c | 2 +- + src/amd/vulkan/radv_pipeline_graphics.c | 2 +- + src/amd/vulkan/radv_shader_args.c | 2 +- + src/amd/vulkan/radv_shader_info.c | 6 +++--- + src/amd/vulkan/radv_shader_info.h | 3 ++- + src/gallium/drivers/radeonsi/si_shader_aco.c | 2 +- + 12 files changed, 21 insertions(+), 19 deletions(-) + +diff --git a/src/amd/compiler/aco_assembler.cpp b/src/amd/compiler/aco_assembler.cpp +index 714648b252c..cf57a7e95c6 100644 +--- a/src/amd/compiler/aco_assembler.cpp ++++ b/src/amd/compiler/aco_assembler.cpp +@@ -1727,7 +1727,8 @@ emit_program(Program* program, std::vector& code, std::vectorinfo.merged_shader_compiled_separately; + + /* Prolog has no exports. */ +- if (!program->is_prolog && !program->info.has_epilog && !is_separately_compiled_ngg_vs_or_es && ++ if (!program->is_prolog && !program->info.ps.has_epilog && ++ !is_separately_compiled_ngg_vs_or_es && + (program->stage.hw == AC_HW_VERTEX_SHADER || program->stage.hw == AC_HW_PIXEL_SHADER || + program->stage.hw == AC_HW_NEXT_GEN_GEOMETRY_SHADER)) + fix_exports(ctx, code, program); +diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp +index 8ab9c18ee2a..987ba7d22ae 100644 +--- a/src/amd/compiler/aco_instruction_selection.cpp ++++ b/src/amd/compiler/aco_instruction_selection.cpp +@@ -177,7 +177,7 @@ emit_bpermute(isel_context* ctx, Builder& bld, Temp index, Temp data) + const bool avoid_shared_vgprs = + ctx->options->gfx_level >= GFX10 && ctx->options->gfx_level < GFX11 && + ctx->program->wave_size == 64 && +- (ctx->program->info.has_epilog || ctx->program->info.merged_shader_compiled_separately || ++ (ctx->program->info.ps.has_epilog || ctx->program->info.merged_shader_compiled_separately || + ctx->program->info.vs.has_prolog || ctx->stage == raytracing_cs); + + if (ctx->options->gfx_level <= GFX7 || avoid_shared_vgprs) { +@@ -5611,7 +5611,7 @@ store_output_to_temps(isel_context* ctx, nir_intrinsic_instr* instr) + idx++; + } + +- if (ctx->stage == fragment_fs && ctx->program->info.has_epilog && base >= FRAG_RESULT_DATA0) { ++ if (ctx->stage == fragment_fs && ctx->program->info.ps.has_epilog && base >= FRAG_RESULT_DATA0) { + unsigned index = base - FRAG_RESULT_DATA0; + + if (nir_intrinsic_src_type(instr) == nir_type_float16) { +@@ -11927,7 +11927,7 @@ select_shader(isel_context& ctx, nir_shader* nir, const bool need_startpgm, cons + nir_function_impl* func = nir_shader_get_entrypoint(nir); + visit_cf_list(&ctx, &func->body); + +- if (ctx.program->info.has_epilog) { ++ if (ctx.program->info.ps.has_epilog) { + if (ctx.stage == fragment_fs) { + if (ctx.options->is_opengl) + create_fs_end_for_epilog(&ctx); +@@ -11965,7 +11965,7 @@ select_shader(isel_context& ctx, nir_shader* nir, const bool need_startpgm, cons + append_logical_end(ctx.block); + ctx.block->kind |= block_kind_uniform; + +- if ((!program->info.has_epilog && !is_first_stage_of_merged_shader) || ++ if ((!program->info.ps.has_epilog && !is_first_stage_of_merged_shader) || + (nir->info.stage == MESA_SHADER_TESS_CTRL && program->gfx_level >= GFX9)) { + Builder(program, ctx.block).sopp(aco_opcode::s_endpgm); + } +diff --git a/src/amd/compiler/aco_interface.cpp b/src/amd/compiler/aco_interface.cpp +index 8508cc0445e..64396cfbc75 100644 +--- a/src/amd/compiler/aco_interface.cpp ++++ b/src/amd/compiler/aco_interface.cpp +@@ -277,7 +277,7 @@ aco_compile_shader(const struct aco_compiler_options* options, const struct aco_ + /* OpenGL combine multi shader parts into one continous code block, + * so only last part need the s_endpgm instruction. + */ +- bool append_endpgm = !(options->is_opengl && info->has_epilog); ++ bool append_endpgm = !(options->is_opengl && info->ps.has_epilog); + unsigned exec_size = emit_program(program.get(), code, &symbols, append_endpgm); + + if (program->collect_statistics) +diff --git a/src/amd/compiler/aco_shader_info.h b/src/amd/compiler/aco_shader_info.h +index 1cc2bc11db4..7f6fe7a5e9e 100644 +--- a/src/amd/compiler/aco_shader_info.h ++++ b/src/amd/compiler/aco_shader_info.h +@@ -102,7 +102,6 @@ struct aco_shader_info { + bool has_ngg_early_prim_export; + bool image_2d_view_of_3d; + unsigned workgroup_size; +- bool has_epilog; /* Only for TCS or PS. */ + bool merged_shader_compiled_separately; /* GFX9+ */ + struct ac_arg next_stage_pc; + struct ac_arg epilog_pc; /* Vulkan only */ +@@ -127,6 +126,7 @@ struct aco_shader_info { + uint32_t num_interp; + unsigned spi_ps_input_ena; + unsigned spi_ps_input_addr; ++ bool has_epilog; + + /* OpenGL only */ + struct ac_arg alpha_reference; +diff --git a/src/amd/vulkan/radv_aco_shader_info.h b/src/amd/vulkan/radv_aco_shader_info.h +index b9665b2b20f..912d6b6ca4e 100644 +--- a/src/amd/vulkan/radv_aco_shader_info.h ++++ b/src/amd/vulkan/radv_aco_shader_info.h +@@ -31,7 +31,7 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv + ASSIGN_FIELD(has_ngg_culling); + ASSIGN_FIELD(has_ngg_early_prim_export); + ASSIGN_FIELD(workgroup_size); +- ASSIGN_FIELD(has_epilog); ++ ASSIGN_FIELD(ps.has_epilog); + ASSIGN_FIELD(merged_shader_compiled_separately); + ASSIGN_FIELD(vs.tcs_in_out_eq); + ASSIGN_FIELD(vs.tcs_temp_only_input_mask); +diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c +index d0cf1f1123b..671b35cb972 100644 +--- a/src/amd/vulkan/radv_cmd_buffer.c ++++ b/src/amd/vulkan/radv_cmd_buffer.c +@@ -8096,7 +8096,7 @@ radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_ + cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DB_SHADER_CONTROL; + + /* Re-emit the PS epilog when a new fragment shader is bound. */ +- if (ps->info.has_epilog) ++ if (ps->info.ps.has_epilog) + cmd_buffer->state.emitted_ps_epilog = NULL; + } + +@@ -10703,7 +10703,7 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r + struct radv_shader_part *ps_epilog = NULL; + + if (cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT] && +- cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]->info.has_epilog) { ++ cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]->info.ps.has_epilog) { + if ((cmd_buffer->state.emitted_graphics_pipeline != cmd_buffer->state.graphics_pipeline || + ((cmd_buffer->state.dirty & (RADV_CMD_DIRTY_GRAPHICS_SHADERS | RADV_CMD_DIRTY_FRAMEBUFFER)) || + (cmd_buffer->state.dirty_dynamic & +@@ -10921,7 +10921,7 @@ radv_bind_graphics_shaders(struct radv_cmd_buffer *cmd_buffer) + } + + const struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]; +- if (ps && !ps->info.has_epilog) { ++ if (ps && !ps->info.ps.has_epilog) { + uint32_t col_format = 0, cb_shader_mask = 0; + if (radv_needs_null_export_workaround(device, ps, 0)) + col_format = V_028714_SPI_SHADER_32_R; +diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c +index e07737cd742..738fc736b2c 100644 +--- a/src/amd/vulkan/radv_pipeline.c ++++ b/src/amd/vulkan/radv_pipeline.c +@@ -551,7 +551,7 @@ radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_stat + .use_aco = !radv_use_llvm_for_stage(pdev, stage->stage), + .uses_discard = true, + .alpha_func = COMPARE_FUNC_ALWAYS, +- .no_color_export = stage->info.has_epilog, ++ .no_color_export = stage->info.ps.has_epilog, + .no_depth_export = stage->info.ps.exports_mrtz_via_epilog, + + .bc_optimize_for_persp = G_0286CC_PERSP_CENTER_ENA(stage->info.ps.spi_ps_input_ena) && +diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c +index ed380341ba5..daab8ce2ed6 100644 +--- a/src/amd/vulkan/radv_pipeline_graphics.c ++++ b/src/amd/vulkan/radv_pipeline_graphics.c +@@ -3150,7 +3150,7 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv + radv_pipeline_init_dynamic_state(device, pipeline, &gfx_state.vk, pCreateInfo); + + const struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT]; +- if (ps && !ps->info.has_epilog) { ++ if (ps && !ps->info.ps.has_epilog) { + pipeline->spi_shader_col_format = ps->info.ps.spi_shader_col_format; + pipeline->cb_shader_mask = ps->info.ps.cb_shader_mask; + } +diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c +index 10f1ee3ad07..479bc49c803 100644 +--- a/src/amd/vulkan/radv_shader_args.c ++++ b/src/amd/vulkan/radv_shader_args.c +@@ -846,7 +846,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics + case MESA_SHADER_FRAGMENT: + declare_global_input_sgprs(gfx_level, info, user_sgpr_info, args); + +- if (info->has_epilog) { ++ if (info->ps.has_epilog) { + add_ud_arg(args, 1, AC_ARG_INT, &args->epilog_pc, AC_UD_EPILOG_PC); + } + +diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c +index c8c0b77201d..a1050a9ec07 100644 +--- a/src/amd/vulkan/radv_shader_info.c ++++ b/src/amd/vulkan/radv_shader_info.c +@@ -972,9 +972,9 @@ gather_shader_info_fs(const struct radv_device *device, const nir_shader *nir, + info->ps.spi_ps_input_addr &= C_02865C_COVERAGE_TO_SHADER_SELECT; + } + +- info->has_epilog = gfx_state->ps.has_epilog && info->ps.colors_written; ++ info->ps.has_epilog = gfx_state->ps.has_epilog && info->ps.colors_written; + +- if (!info->has_epilog) { ++ if (!info->ps.has_epilog) { + info->ps.mrt0_is_dual_src = gfx_state->ps.epilog.mrt0_is_dual_src; + info->ps.spi_shader_col_format = gfx_state->ps.epilog.spi_shader_col_format; + +@@ -988,7 +988,7 @@ gather_shader_info_fs(const struct radv_device *device, const nir_shader *nir, + (info->ps.color0_written & 0x8) && (info->ps.writes_z || info->ps.writes_stencil || info->ps.writes_sample_mask); + + info->ps.exports_mrtz_via_epilog = +- info->has_epilog && gfx_state->ps.exports_mrtz_via_epilog && export_alpha_and_mrtz; ++ info->ps.has_epilog && gfx_state->ps.exports_mrtz_via_epilog && export_alpha_and_mrtz; + + if (!info->ps.exports_mrtz_via_epilog) { + info->ps.writes_mrt0_alpha = gfx_state->ms.alpha_to_coverage_via_mrtz && export_alpha_and_mrtz; +diff --git a/src/amd/vulkan/radv_shader_info.h b/src/amd/vulkan/radv_shader_info.h +index e072c9ffd5b..0ffa972b078 100644 +--- a/src/amd/vulkan/radv_shader_info.h ++++ b/src/amd/vulkan/radv_shader_info.h +@@ -106,7 +106,6 @@ struct radv_shader_info { + uint32_t user_data_0; + bool inputs_linked; + bool outputs_linked; +- bool has_epilog; /* Only for TCS or PS */ + bool merged_shader_compiled_separately; /* GFX9+ */ + bool force_indirect_desc_sets; + +@@ -213,6 +212,8 @@ struct radv_shader_info { + bool load_provoking_vtx; + bool load_rasterization_prim; + bool force_sample_iter_shading_rate; ++ bool uses_fbfetch_output; ++ bool has_epilog; + } ps; + struct { + bool uses_grid_size; +diff --git a/src/gallium/drivers/radeonsi/si_shader_aco.c b/src/gallium/drivers/radeonsi/si_shader_aco.c +index 67ba140ed67..232104954fb 100644 +--- a/src/gallium/drivers/radeonsi/si_shader_aco.c ++++ b/src/gallium/drivers/radeonsi/si_shader_aco.c +@@ -100,7 +100,7 @@ si_fill_aco_shader_info(struct si_shader *shader, struct aco_shader_info *info, + info->ps.spi_ps_input_ena = shader->config.spi_ps_input_ena; + info->ps.spi_ps_input_addr = shader->config.spi_ps_input_addr; + info->ps.alpha_reference = args->alpha_reference; +- info->has_epilog = !shader->is_monolithic; ++ info->ps.has_epilog = !shader->is_monolithic; + break; + default: + break; +-- +2.48.1 + + +From 82939c7825d3a45d5e992e10491e43183e511a9d Mon Sep 17 00:00:00 2001 +From: Rhys Perry +Date: Thu, 24 Oct 2024 11:01:46 +0100 +Subject: [PATCH 25/27] aco,radv,radeonsi: add aco_shader_info::ps::has_prolog + +Signed-off-by: Rhys Perry +Reviewed-by: Georg Lehmann +Part-of: +--- + src/amd/compiler/aco_shader_info.h | 1 + + src/amd/vulkan/radv_aco_shader_info.h | 1 + + src/gallium/drivers/radeonsi/si_shader_aco.c | 1 + + 3 files changed, 3 insertions(+) + +diff --git a/src/amd/compiler/aco_shader_info.h b/src/amd/compiler/aco_shader_info.h +index 7f6fe7a5e9e..ad615e19992 100644 +--- a/src/amd/compiler/aco_shader_info.h ++++ b/src/amd/compiler/aco_shader_info.h +@@ -126,6 +126,7 @@ struct aco_shader_info { + uint32_t num_interp; + unsigned spi_ps_input_ena; + unsigned spi_ps_input_addr; ++ bool has_prolog; + bool has_epilog; + + /* OpenGL only */ +diff --git a/src/amd/vulkan/radv_aco_shader_info.h b/src/amd/vulkan/radv_aco_shader_info.h +index 912d6b6ca4e..9a0b4d562e0 100644 +--- a/src/amd/vulkan/radv_aco_shader_info.h ++++ b/src/amd/vulkan/radv_aco_shader_info.h +@@ -41,6 +41,7 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv + ASSIGN_FIELD(cs.uses_full_subgroups); + aco_info->ps.spi_ps_input_ena = radv->ps.spi_ps_input_ena; + aco_info->ps.spi_ps_input_addr = radv->ps.spi_ps_input_addr; ++ aco_info->ps.has_prolog = false; + aco_info->gfx9_gs_ring_lds_size = radv->gs_ring_info.lds_size; + aco_info->is_trap_handler_shader = radv->type == RADV_SHADER_TYPE_TRAP_HANDLER; + aco_info->image_2d_view_of_3d = radv_key->image_2d_view_of_3d; +diff --git a/src/gallium/drivers/radeonsi/si_shader_aco.c b/src/gallium/drivers/radeonsi/si_shader_aco.c +index 232104954fb..dd0b3759a2b 100644 +--- a/src/gallium/drivers/radeonsi/si_shader_aco.c ++++ b/src/gallium/drivers/radeonsi/si_shader_aco.c +@@ -100,6 +100,7 @@ si_fill_aco_shader_info(struct si_shader *shader, struct aco_shader_info *info, + info->ps.spi_ps_input_ena = shader->config.spi_ps_input_ena; + info->ps.spi_ps_input_addr = shader->config.spi_ps_input_addr; + info->ps.alpha_reference = args->alpha_reference; ++ info->ps.has_prolog = !shader->is_monolithic; + info->ps.has_epilog = !shader->is_monolithic; + break; + default: +-- +2.48.1 + + +From af418b1dcedd56326872945c18dff6dae79ebfdf Mon Sep 17 00:00:00 2001 +From: Samuel Pitoiset +Date: Thu, 12 Sep 2024 15:44:43 +0200 +Subject: [PATCH 26/27] radv,radeonsi: remove remaining occurrences of TCS + epilog + +TCS epilog has been removed few months ago. + +Signed-off-by: Samuel Pitoiset +Part-of: +--- + src/amd/vulkan/radv_shader_args.c | 8 -------- + src/gallium/drivers/radeonsi/si_shader_aco.c | 1 - + 2 files changed, 9 deletions(-) + +diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c +index 479bc49c803..100797c7389 100644 +--- a/src/amd/vulkan/radv_shader_args.c ++++ b/src/amd/vulkan/radv_shader_args.c +@@ -683,10 +683,6 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics + add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_offchip_layout, AC_UD_TCS_OFFCHIP_LAYOUT); + } + +- if (info->has_epilog) { +- add_ud_arg(args, 1, AC_ARG_INT, &args->epilog_pc, AC_UD_EPILOG_PC); +- } +- + ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_patch_id); + ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_rel_ids); + +@@ -703,10 +699,6 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics + add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_offchip_layout, AC_UD_TCS_OFFCHIP_LAYOUT); + } + +- if (info->has_epilog) { +- add_ud_arg(args, 1, AC_ARG_INT, &args->epilog_pc, AC_UD_EPILOG_PC); +- } +- + ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset); + ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tcs_factor_offset); + if (args->explicit_scratch_args) { +diff --git a/src/gallium/drivers/radeonsi/si_shader_aco.c b/src/gallium/drivers/radeonsi/si_shader_aco.c +index dd0b3759a2b..dacfe15bb5a 100644 +--- a/src/gallium/drivers/radeonsi/si_shader_aco.c ++++ b/src/gallium/drivers/radeonsi/si_shader_aco.c +@@ -88,7 +88,6 @@ si_fill_aco_shader_info(struct si_shader *shader, struct aco_shader_info *info, + case MESA_SHADER_TESS_CTRL: + info->vs.tcs_in_out_eq = key->ge.opt.same_patch_vertices; + info->vs.tcs_temp_only_input_mask = sel->info.tcs_vgpr_only_inputs; +- info->has_epilog = !shader->is_monolithic; + info->tcs.pass_tessfactors_by_reg = sel->info.tessfactors_are_def_in_all_invocs; + info->tcs.patch_stride = si_get_tcs_out_patch_stride(&sel->info); + info->tcs.tcs_offchip_layout = args->tcs_offchip_layout; +-- +2.48.1 + + +From fdd1b46c2683b34bb7171038999e0dc4620a9296 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= +Date: Wed, 8 Jan 2025 15:03:32 -0500 +Subject: [PATCH 27/27] radeonsi/gfx12: use ACO if LLVM is 19 or older + +LLVM 19 is missing a SALU hazard fix. + +(cherry-picked + adapted from 239840556f99aaa1b71c450a3b389bd9be1a24f3) + +Reviewed-by: Pierre-Eric Pelloux-Prayer +Part-of: +--- + src/gallium/drivers/radeonsi/si_pipe.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c +index 4e063c1ce3e..f3f23ab0dd0 100644 +--- a/src/gallium/drivers/radeonsi/si_pipe.c ++++ b/src/gallium/drivers/radeonsi/si_pipe.c +@@ -1198,7 +1198,14 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, + sscreen->info.register_shadowing_required = true; + + #if AMD_LLVM_AVAILABLE +- sscreen->use_aco = (sscreen->debug_flags & DBG(USE_ACO)); ++ /* For GFX11.5, LLVM < 19 is missing a workaround that can cause GPU hangs. ACO is the only ++ * alternative that has the workaround and is always available. Same for GFX12. ++ */ ++ if ((sscreen->info.gfx_level == GFX12 && LLVM_VERSION_MAJOR < 20) || ++ (sscreen->info.gfx_level == GFX11_5 && LLVM_VERSION_MAJOR < 19)) ++ sscreen->use_aco = true; ++ else ++ sscreen->use_aco = sscreen->debug_flags & DBG(USE_ACO); + #else + sscreen->use_aco = true; + #endif +-- +2.48.1 + diff --git a/SOURCES/0001-clover-llvm-move-to-modern-pass-manager.patch b/SOURCES/0001-clover-llvm-move-to-modern-pass-manager.patch deleted file mode 100644 index cb6971e..0000000 --- a/SOURCES/0001-clover-llvm-move-to-modern-pass-manager.patch +++ /dev/null @@ -1,127 +0,0 @@ -From 2d4fe5f229791fde52846b3f583c12508b5109d6 Mon Sep 17 00:00:00 2001 -From: Dave Airlie -Date: Fri, 25 Aug 2023 12:43:44 +1000 -Subject: [PATCH] clover/llvm: move to modern pass manager. -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This seems like it should work, but I haven't tested it yet. - -Tested-by: Dieter Nützel -Part-of: ---- - .../frontends/clover/llvm/invocation.cpp | 64 +++++++++++++++---- - 1 file changed, 51 insertions(+), 13 deletions(-) - -diff --git a/src/gallium/frontends/clover/llvm/invocation.cpp b/src/gallium/frontends/clover/llvm/invocation.cpp -index 7a50fea3323..43d26fe1abb 100644 ---- a/src/gallium/frontends/clover/llvm/invocation.cpp -+++ b/src/gallium/frontends/clover/llvm/invocation.cpp -@@ -27,13 +27,17 @@ - #include - #include - #include -+#include - #include --#include -+#include - #include - #ifdef HAVE_CLOVER_SPIRV - #include - #endif - -+#include -+#include -+#include - #include - #include - #include -@@ -439,10 +443,10 @@ clover::llvm::compile_program(const std::string &source, - - namespace { - void -- optimize(Module &mod, unsigned optimization_level, -+ optimize(Module &mod, -+ const std::string& ir_target, -+ unsigned optimization_level, - bool internalize_symbols) { -- ::llvm::legacy::PassManager pm; -- - // By default, the function internalizer pass will look for a function - // called "main" and then mark all other functions as internal. Marking - // functions as internal enables the optimizer to perform optimizations -@@ -458,19 +462,53 @@ namespace { - if (internalize_symbols) { - std::vector names = - map(std::mem_fn(&Function::getName), get_kernels(mod)); -- pm.add(::llvm::createInternalizePass( -+ internalizeModule(mod, - [=](const ::llvm::GlobalValue &gv) { - return std::find(names.begin(), names.end(), - gv.getName()) != names.end(); -- })); -+ }); - } - -- ::llvm::PassManagerBuilder pmb; -- pmb.OptLevel = optimization_level; -- pmb.LibraryInfo = new ::llvm::TargetLibraryInfoImpl( -- ::llvm::Triple(mod.getTargetTriple())); -- pmb.populateModulePassManager(pm); -- pm.run(mod); -+ -+ const char *opt_str = NULL; -+ LLVMCodeGenOptLevel level; -+ switch (optimization_level) { -+ case 0: -+ default: -+ opt_str = "default"; -+ level = LLVMCodeGenLevelNone; -+ break; -+ case 1: -+ opt_str = "default"; -+ level = LLVMCodeGenLevelLess; -+ break; -+ case 2: -+ opt_str = "default"; -+ level = LLVMCodeGenLevelDefault; -+ break; -+ case 3: -+ opt_str = "default"; -+ level = LLVMCodeGenLevelAggressive; -+ break; -+ } -+ -+ const target &target = ir_target; -+ LLVMTargetRef targ; -+ char *err_message; -+ -+ if (LLVMGetTargetFromTriple(target.triple.c_str(), &targ, &err_message)) -+ return; -+ LLVMTargetMachineRef tm = -+ LLVMCreateTargetMachine(targ, target.triple.c_str(), -+ target.cpu.c_str(), "", level, -+ LLVMRelocDefault, LLVMCodeModelDefault); -+ -+ if (!tm) -+ return; -+ LLVMPassBuilderOptionsRef opts = LLVMCreatePassBuilderOptions(); -+ LLVMRunPasses(wrap(&mod), opt_str, tm, opts); -+ -+ LLVMDisposeTargetMachine(tm); - } - - std::unique_ptr -@@ -500,7 +538,7 @@ clover::llvm::link_program(const std::vector &binaries, - auto c = create_compiler_instance(dev, dev.ir_target(), options, r_log); - auto mod = link(*ctx, *c, binaries, r_log); - -- optimize(*mod, c->getCodeGenOpts().OptimizationLevel, !create_library); -+ optimize(*mod, dev.ir_target(), c->getCodeGenOpts().OptimizationLevel, !create_library); - - static std::atomic_uint seq(0); - const std::string id = "." + mod->getModuleIdentifier() + "-" + --- -2.42.0 - diff --git a/SOURCES/0001-llvmpipe-only-include-old-Transform-includes-when-ne.patch b/SOURCES/0001-llvmpipe-only-include-old-Transform-includes-when-ne.patch deleted file mode 100644 index 064d5eb..0000000 --- a/SOURCES/0001-llvmpipe-only-include-old-Transform-includes-when-ne.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 9ba416cdc67073cdda9a73fe9d37304b82bdd526 Mon Sep 17 00:00:00 2001 -From: Pierre-Eric Pelloux-Prayer -Date: Fri, 12 May 2023 09:58:26 +0200 -Subject: [PATCH] llvmpipe: only include old Transform includes when needed - -This fixes building with recent LLVM where these 2 .h files -were removed. - -Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8671 -Acked-By: Mike Blumenkrantz -Part-of: ---- - src/gallium/auxiliary/gallivm/lp_bld_init.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c -index 24d082398e9..9e0d6a5f643 100644 ---- a/src/gallium/auxiliary/gallivm/lp_bld_init.c -+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c -@@ -42,14 +42,14 @@ - - #include - #include --#include --#if LLVM_VERSION_MAJOR >= 7 --#include --#endif - #include - #if GALLIVM_USE_NEW_PASS == 1 - #include - #elif GALLIVM_HAVE_CORO == 1 -+#include -+#if LLVM_VERSION_MAJOR >= 7 -+#include -+#endif - #if LLVM_VERSION_MAJOR <= 8 && (DETECT_ARCH_AARCH64 || DETECT_ARCH_ARM || DETECT_ARCH_S390 || DETECT_ARCH_MIPS64) - #include - #endif --- -2.42.0 - diff --git a/SOURCES/0001-mesa-fix-off-by-one-for-newblock-allocation-in-dlist.patch b/SOURCES/0001-mesa-fix-off-by-one-for-newblock-allocation-in-dlist.patch deleted file mode 100644 index 6862136..0000000 --- a/SOURCES/0001-mesa-fix-off-by-one-for-newblock-allocation-in-dlist.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 460d2c46a903fed295a1528c8b6273dd6b0e0d19 Mon Sep 17 00:00:00 2001 -From: thfrwn <11335318+rfht@users.noreply.github.com> -Date: Fri, 9 Feb 2024 17:00:55 -0500 -Subject: [PATCH] mesa: fix off-by-one for newblock allocation in dlist_alloc - -Cc: mesa-stable -Reviewed-by: Pierre-Eric Pelloux-Prayer -Part-of: ---- - src/mesa/main/dlist.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c -index b0184a24e20..9213641699a 100644 ---- a/src/mesa/main/dlist.c -+++ b/src/mesa/main/dlist.c -@@ -1220,7 +1220,7 @@ dlist_alloc(struct gl_context *ctx, OpCode opcode, GLuint bytes, bool align8) - ctx->ListState.CurrentPos++; - } - -- if (ctx->ListState.CurrentPos + numNodes + contNodes > BLOCK_SIZE) { -+ if (ctx->ListState.CurrentPos + numNodes + contNodes >= BLOCK_SIZE) { - /* This block is full. Allocate a new block and chain to it */ - Node *newblock; - Node *n = ctx->ListState.CurrentBlock + ctx->ListState.CurrentPos; --- -2.45.2 - diff --git a/SOURCES/0001-nouveau-nvc0-increase-overallocation-on-shader-bo-to.patch b/SOURCES/0001-nouveau-nvc0-increase-overallocation-on-shader-bo-to.patch deleted file mode 100644 index 9c2e4e5..0000000 --- a/SOURCES/0001-nouveau-nvc0-increase-overallocation-on-shader-bo-to.patch +++ /dev/null @@ -1,37 +0,0 @@ -From f7434d7576032cf97e3c74ef09912f59617a4bad Mon Sep 17 00:00:00 2001 -From: Dave Airlie -Date: Fri, 14 Jun 2024 12:22:58 +1000 -Subject: [PATCH] nouveau/nvc0: increase overallocation on shader bo to 2K - -I've been seeing a bunch of read page faults at the end of the -shader allocation, nvk uses a full page at the end to overallocate -so align with that and see if it goes away. - -ahulliet and skeggsb both said 2k was used. - -Cc: mesa-stable -Reviewed-by: Arthur Huillet -Reviewed-by: Karol Herbst -Part-of: ---- - src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -diff -up mesa-23.1.4/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c.dma mesa-23.1.4/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c ---- mesa-23.1.4/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c.dma 2023-07-21 22:42:42.000000000 +1000 -+++ mesa-23.1.4/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c 2024-08-16 12:49:13.532998512 +1000 -@@ -886,10 +886,11 @@ nvc0_screen_resize_text_area(struct nvc0 - nouveau_heap_free(&screen->lib_code); - nouveau_heap_destroy(&screen->text_heap); - -- /* XXX: getting a page fault at the end of the code buffer every few -- * launches, don't use the last 256 bytes to work around them - prefetch ? -+ /* -+ * Shader storage needs a 2K (from NVIDIA) overallocations at the end -+ * to avoid prefetch bugs. - */ -- nouveau_heap_init(&screen->text_heap, 0, size - 0x100); -+ nouveau_heap_init(&screen->text_heap, 0, size - 0x800); - - /* update the code segment setup */ - if (screen->eng3d->oclass < GV100_3D_CLASS) { diff --git a/SOURCES/Makefile b/SOURCES/Makefile deleted file mode 100644 index bbe6f0a..0000000 --- a/SOURCES/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -VERSION ?= 23.1.4 -SANITIZE ?= 1 - -DIRNAME = mesa-${VERSION} - -all: archive - -clean: - rm -rf $(DIRNAME)/ - rm -f mesa-${VERSION}.tar.xz - -clone: clean - curl -O https://archive.mesa3d.org/mesa-${VERSION}.tar.xz - tar xf mesa-${VERSION}.tar.xz - -sanitize: clone vl_mpeg12_decoder.c vl_decoder.c -ifdef SANITIZE - cat < vl_mpeg12_decoder.c > $(DIRNAME)/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c - cat < vl_decoder.c > $(DIRNAME)/src/gallium/auxiliary/vl/vl_decoder.c -endif - -archive: clone sanitize - tar caf ${DIRNAME}.tar.xz ${DIRNAME} diff --git a/SOURCES/fix-py-ver.patch b/SOURCES/fix-py-ver.patch deleted file mode 100644 index 053ab54..0000000 --- a/SOURCES/fix-py-ver.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -up mesa-23.1.4/meson.build.dma mesa-23.1.4/meson.build ---- mesa-23.1.4/meson.build.dma 2023-07-28 10:15:41.807945483 +1000 -+++ mesa-23.1.4/meson.build 2023-07-28 10:15:46.465030794 +1000 -@@ -835,7 +835,7 @@ if get_option('allow-kcmp') \ - pre_args += '-DALLOW_KCMP' - endif - --prog_python = import('python').find_installation('python3') -+prog_python = import('python').find_installation('python3.6') - has_mako = run_command( - prog_python, '-c', - ''' diff --git a/SOURCES/lavapipe-disable-env-var.patch b/SOURCES/lavapipe-disable-env-var.patch deleted file mode 100644 index 4992a3c..0000000 --- a/SOURCES/lavapipe-disable-env-var.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff -up mesa-21.3.0/src/gallium/frontends/lavapipe/lvp_device.cdma mesa-21.3.0/src/gallium/frontends/lavapipe/lvp_device.c ---- mesa-21.3.0/src/gallium/frontends/lavapipe/lvp_device.cdma 2021-11-18 06:16:20.000000000 +1000 -+++ mesa-21.3.0/src/gallium/frontends/lavapipe/lvp_device.c 2021-11-18 07:03:17.652283186 +1000 -@@ -213,6 +213,9 @@ VKAPI_ATTR VkResult VKAPI_CALL lvp_Creat - if (pAllocator == NULL) - pAllocator = vk_default_allocator(); - -+ if (!getenv("RH_SW_VULKAN")) -+ return VK_ERROR_INITIALIZATION_FAILED; -+ - instance = vk_zalloc(pAllocator, sizeof(*instance), 8, - VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE); - if (!instance) diff --git a/SOURCES/nouveau-work-around-linear-zs-issue.patch b/SOURCES/nouveau-work-around-linear-zs-issue.patch deleted file mode 100644 index 48d134c..0000000 --- a/SOURCES/nouveau-work-around-linear-zs-issue.patch +++ /dev/null @@ -1,30 +0,0 @@ -diff -up mesa-23.1.4/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c.da mesa-23.1.4/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c ---- mesa-23.1.4/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c.da 2025-01-10 13:14:31.119630821 +1000 -+++ mesa-23.1.4/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c 2025-01-10 13:15:11.917433170 +1000 -@@ -149,6 +149,7 @@ nvc0_validate_fb(struct nvc0_context *nv - unsigned ms_mode = NVC0_3D_MULTISAMPLE_MODE_MS1; - unsigned nr_cbufs = fb->nr_cbufs; - bool serialize = false; -+ bool cbuf_is_linear = false; - - nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB); - -@@ -203,8 +204,7 @@ nvc0_validate_fb(struct nvc0_context *nv - PUSH_DATA(push, 0); - - nvc0_resource_fence(nvc0, res, NOUVEAU_BO_WR); -- -- assert(!fb->zsbuf); -+ cbuf_is_linear = true; - } - - if (res->status & NOUVEAU_BUFFER_STATUS_GPU_READING) -@@ -216,7 +216,7 @@ nvc0_validate_fb(struct nvc0_context *nv - BCTX_REFN(nvc0->bufctx_3d, 3D_FB, res, WR); - } - -- if (fb->zsbuf) { -+ if (fb->zsbuf && !cbuf_is_linear) { - struct nv50_miptree *mt = nv50_miptree(fb->zsbuf->texture); - struct nv50_surface *sf = nv50_surface(fb->zsbuf); - int unk = mt->base.base.target == PIPE_TEXTURE_2D; diff --git a/SOURCES/radeonsi-turn-off-glthread.patch b/SOURCES/radeonsi-turn-off-glthread.patch deleted file mode 100644 index 4d35f9c..0000000 --- a/SOURCES/radeonsi-turn-off-glthread.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -up mesa-22.3.3/src/gallium/drivers/radeonsi/driinfo_radeonsi.h.dma mesa-22.3.3/src/gallium/drivers/radeonsi/driinfo_radeonsi.h ---- mesa-22.3.3/src/gallium/drivers/radeonsi/driinfo_radeonsi.h.dma 2023-01-25 06:17:54.993167334 +1000 -+++ mesa-22.3.3/src/gallium/drivers/radeonsi/driinfo_radeonsi.h 2023-01-25 06:17:57.363203425 +1000 -@@ -1,7 +1,6 @@ - // DriConf options specific to radeonsi - DRI_CONF_SECTION_PERFORMANCE - DRI_CONF_ADAPTIVE_SYNC(true) --DRI_CONF_MESA_GLTHREAD(true) - DRI_CONF_SECTION_END - - DRI_CONF_SECTION_DEBUG diff --git a/SOURCES/vl_decoder.c b/SOURCES/vl_decoder.c deleted file mode 100644 index 1e715b6..0000000 --- a/SOURCES/vl_decoder.c +++ /dev/null @@ -1,20 +0,0 @@ -#include "vl_decoder.h" -bool -vl_profile_supported(struct pipe_screen *screen, enum pipe_video_profile profile, - enum pipe_video_entrypoint entrypoint) -{ - return false; -} - -int -vl_level_supported(struct pipe_screen *screen, enum pipe_video_profile profile) -{ - return 0; -} - -struct pipe_video_codec * -vl_create_decoder(struct pipe_context *pipe, - const struct pipe_video_codec *templat) -{ - return NULL; -} diff --git a/SOURCES/vl_mpeg12_decoder.c b/SOURCES/vl_mpeg12_decoder.c deleted file mode 100644 index 85ac2c9..0000000 --- a/SOURCES/vl_mpeg12_decoder.c +++ /dev/null @@ -1,7 +0,0 @@ -#include "vl_mpeg12_decoder.h" -struct pipe_video_codec * -vl_create_mpeg12_decoder(struct pipe_context *context, - const struct pipe_video_codec *templat) -{ - return NULL; -} diff --git a/SPECS/mesa.spec b/SPECS/mesa.spec deleted file mode 100644 index 0e172d6..0000000 --- a/SPECS/mesa.spec +++ /dev/null @@ -1,1438 +0,0 @@ -%global llvm_toolset %{nil} -%global llvm_pkg_prefix %{nil} - -%ifarch s390x -%define with_hardware 0 -%else -%define with_hardware 1 -%define with_vdpau 1 -%endif - -%ifarch %{ix86} x86_64 -%define with_vmware 1 -%define with_xa 1 -%define with_iris 1 -%define with_crocus 1 -%endif - -%ifarch %{ix86} x86_64 -%define with_vulkan_hw 1 -%else -%define with_vulkan_hw 0 -%endif - -%ifarch %{arm} aarch64 -%define with_xa 1 -%endif - -%if 0%{?with_vulkan_hw} -%define vulkan_drivers swrast,intel,intel_hasvk,amd -%else -%define vulkan_drivers swrast -%endif - -%global sanitize 0 - -#global rctag rc4 - -Name: mesa -Summary: Mesa graphics libraries -Version: 23.1.4 -Release: 4%{?rctag:.%{rctag}}%{?dist} - -License: MIT -URL: http://www.mesa3d.org -#Source0: https://mesa.freedesktop.org/archive/%{name}-%{version}%{?rctag:-%{rctag}}.tar.xz -Source0: %{name}-%{version}%{?rctag:-%{rctag}}.tar.xz -Source1: vl_decoder.c -Source2: vl_mpeg12_decoder.c -Source3: Makefile -# src/gallium/auxiliary/postprocess/pp_mlaa* have an ... interestingly worded license. -# Source4 contains email correspondence clarifying the license terms. -# Fedora opts to ignore the optional part of clause 2 and treat that code as 2 clause BSD. -Source4: Mesa-MLAA-License-Clarification-Email.txt - -# build our own newer meson -Source5: meson-0.61.4.tar.gz -Source6: dataclasses-0.8.tar.gz - -Patch0: lavapipe-disable-env-var.patch - -Patch1: fix-py-ver.patch -Patch10: gnome-shell-glthread-disable.patch -Patch12: radeonsi-turn-off-glthread.patch - -# Required to build against LLVM 17 -Patch13: 0001-llvmpipe-only-include-old-Transform-includes-when-ne.patch -Patch14: 0001-clover-llvm-move-to-modern-pass-manager.patch - -# https://issues.redhat.com/browse/RHEL-40566 -Patch15: 0001-mesa-fix-off-by-one-for-newblock-allocation-in-dlist.patch - -# two nouveau fixes to avoid kernel crashes with multiple cards -Patch20: 0001-nouveau-nvc0-increase-overallocation-on-shader-bo-to.patch -Patch21: nouveau-work-around-linear-zs-issue.patch - -BuildRequires: gcc -BuildRequires: gcc-c++ - -BuildRequires: meson -%if %{with_hardware} -BuildRequires: kernel-headers -%endif -BuildRequires: libdrm-devel >= 2.4.103 -BuildRequires: libXxf86vm-devel -BuildRequires: expat-devel -BuildRequires: xorg-x11-proto-devel -BuildRequires: libselinux-devel -BuildRequires: libXext-devel -BuildRequires: libXfixes-devel -BuildRequires: libXdamage-devel -BuildRequires: libXi-devel -BuildRequires: libXrandr-devel -BuildRequires: libXmu-devel -BuildRequires: libxshmfence-devel -BuildRequires: elfutils -BuildRequires: python3-devel -BuildRequires: gettext -BuildRequires: glslang -BuildRequires: %{llvm_pkg_prefix}llvm-compat-devel >= 3.4-7 -%if 0%{?with_opencl} -BuildRequires: %{llvm_pkg_prefix}clang-devel >= 3.0 -%endif -BuildRequires: elfutils-libelf-devel -BuildRequires: libudev-devel -BuildRequires: bison flex -BuildRequires: pkgconfig(wayland-client) >= 1.21.0 -BuildRequires: pkgconfig(wayland-server) -BuildRequires: pkgconfig(wayland-protocols) -%if 0%{?with_vdpau} -BuildRequires: libvdpau-devel -%endif -%if 0%{?with_vaapi} -BuildRequires: libva-devel -%endif -BuildRequires: pkgconfig(zlib) -%if 0%{?with_omx} -BuildRequires: libomxil-bellagio-devel -%endif -%if 0%{?with_opencl} -BuildRequires: libclc-devel opencl-filesystem -%endif -BuildRequires: python3-mako -%ifarch %{valgrind_arches} -BuildRequires: pkgconfig(valgrind) -%endif -BuildRequires: pkgconfig(libglvnd) >= 1.2.0 - -%if 0%{?rhel} == 7 -BuildRequires: llvm-toolset-7-runtime -%enable_llvmtoolset7 -%endif - - -%description -%{summary}. - -%package filesystem -Summary: Mesa driver filesystem -Provides: mesa-dri-filesystem = %{?epoch:%{epoch}:}%{version}-%{release} -Obsoletes: mesa-dri-filesystem < %{?epoch:%{epoch}:}%{version}-%{release} - -%description filesystem -%{summary}. - -%package libGL -Summary: Mesa libGL runtime libraries -Requires: %{name}-libglapi%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} -Requires: libglvnd-glx%{?_isa} >= 1:1.2.0-1 - -%description libGL -%{summary}. - -%package libGL-devel -Summary: Mesa libGL development package -Requires: %{name}-libGL%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} -Requires: libglvnd-devel%{?_isa} >= 1:1.2.0-1 -Provides: libGL-devel -Provides: libGL-devel%{?_isa} - -%description libGL-devel -%{summary}. - -%package libEGL -Summary: Mesa libEGL runtime libraries -Requires: libglvnd-egl%{?_isa} >= 1:1.2.0-1 - -%description libEGL -%{summary}. - -%package libEGL-devel -Summary: Mesa libEGL development package -Requires: %{name}-libEGL%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} -Requires: libglvnd-devel%{?_isa} >= 1:1.2.0-1 -Requires: libwayland-client >= 1.21.0 -Provides: libEGL-devel -Provides: libEGL-devel%{?_isa} - -%description libEGL-devel -%{summary}. - -%package dri-drivers -Summary: Mesa-based DRI drivers -Requires: %{name}-filesystem%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} -Requires: libdrm >= 2.4.103 - -%description dri-drivers -%{summary}. - -%if 0%{?with_omx} -%package omx-drivers -Summary: Mesa-based OMX drivers -Requires: %{name}-filesystem%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} - -%description omx-drivers -%{summary}. -%endif - -%if 0%{?with_vdpau} -%package vdpau-drivers -Summary: Mesa-based VDPAU drivers -Requires: %{name}-filesystem%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} - -%description vdpau-drivers -%{summary}. -%endif - -%package libOSMesa -Summary: Mesa offscreen rendering libraries -Requires: %{name}-libglapi%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} -Provides: libOSMesa -Provides: libOSMesa%{?_isa} - -%description libOSMesa -%{summary}. - -%package libOSMesa-devel -Summary: Mesa offscreen rendering development package -Requires: %{name}-libOSMesa%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} - -%description libOSMesa-devel -%{summary}. - -%package libgbm -Summary: Mesa gbm runtime library -Provides: libgbm -Provides: libgbm%{?_isa} - -%description libgbm -%{summary}. - -%package libgbm-devel -Summary: Mesa libgbm development package -Requires: %{name}-libgbm%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} -Provides: libgbm-devel -Provides: libgbm-devel%{?_isa} - -%description libgbm-devel -%{summary}. - -%if 0%{?with_xa} -%package libxatracker -Summary: Mesa XA state tracker -Provides: libxatracker -Provides: libxatracker%{?_isa} - -%description libxatracker -%{summary}. - -%package libxatracker-devel -Summary: Mesa XA state tracker development package -Requires: %{name}-libxatracker%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} -Provides: libxatracker-devel -Provides: libxatracker-devel%{?_isa} - -%description libxatracker-devel -%{summary}. -%endif - -%package libglapi -Summary: Mesa shared glapi -Provides: libglapi -Provides: libglapi%{?_isa} - -%description libglapi -%{summary}. - -%if 0%{?with_opencl} -%package libOpenCL -Summary: Mesa OpenCL runtime library -Requires: ocl-icd%{?_isa} -Requires: libclc%{?_isa} -Requires: %{name}-libgbm%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} -Requires: opencl-filesystem - -%description libOpenCL -%{summary}. - -%package libOpenCL-devel -Summary: Mesa OpenCL development package -Requires: %{name}-libOpenCL%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} - -%description libOpenCL-devel -%{summary}. -%endif - -%if 0%{?with_nine} -%package libd3d -Summary: Mesa Direct3D9 state tracker - -%description libd3d -%{summary}. - -%package libd3d-devel -Summary: Mesa Direct3D9 state tracker development package -Requires: %{name}-libd3d%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} - -%description libd3d-devel -%{summary}. -%endif - -%package vulkan-drivers -Summary: Mesa Vulkan drivers -Requires: vulkan%{_isa} -Requires: libwayland-client >= 1.21.0 - -%description vulkan-drivers -The drivers with support for the Vulkan API. - -%if 0%{?with_vulkan_hw} -%package vulkan-devel -Summary: Mesa Vulkan development files -Requires: %{name}-vulkan-drivers%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} -Requires: vulkan-devel - -%description vulkan-devel -Headers for development with the Vulkan API. -%endif - -%prep -%if 0%{sanitize} -%setup -q -n %{name}-%{version}%{?rctag:-%{rctag}} - cp -f %{SOURCE1} src/gallium/auxiliary/vl/vl_decoder.c - cp -f %{SOURCE2} src/gallium/auxiliary/vl/vl_mpeg12_decoder.c - exit -%else -%autosetup -n %{name}-%{version}%{?rctag:-%{rctag}} -p1 - cmp %{SOURCE1} src/gallium/auxiliary/vl/vl_decoder.c - cmp %{SOURCE2} src/gallium/auxiliary/vl/vl_mpeg12_decoder.c -%endif - -cp %{SOURCE4} docs/ - -tar -xvf %{SOURCE5} -tar -xvf %{SOURCE6} - -pathfix.py -i %{__python3} -pn bin/*.py src/egl/generate/*.py \ - src/gallium/tools/trace/*.py \ - src/compiler/glsl/tests/*.py \ - src/compiler/glsl/glcpp/tests/*.py - -%build -cd meson-0.61.4 -%py3_build -%py3_install -cd - -cd dataclasses-0.8 -%py3_build -%py3_install -cd - -export ASFLAGS="--generate-missing-build-notes=yes" -%global __meson %{buildroot}/usr/bin/meson -export PYTHONPATH=/usr/lib/python3.6/site-packages/:%{buildroot}/usr/lib/python3.6/site-packages/ -export PATH=%{_libdir}/llvm17/bin:$PATH -%meson -Dcpp_std=gnu++17 \ - -Db_ndebug=true \ - -Dplatforms=x11,wayland \ - -Ddri3=enabled \ - -Dosmesa=true \ -%if 0%{?with_hardware} - -Dgallium-drivers=swrast%{?with_crocus:,crocus}%{?with_iris:,iris},virgl,nouveau%{?with_vmware:,svga},radeonsi,r600%{?with_freedreno:,freedreno}%{?with_etnaviv:,etnaviv}%{?with_tegra:,tegra}%{?with_vc4:,vc4}%{?with_kmsro:,kmsro} \ -%else - -Dgallium-drivers=swrast,virgl \ -%endif - -Dgallium-vdpau=%{?with_vdpau:enabled}%{!?with_vdpau:disabled} \ - -Dgallium-omx=%{?with_omx:bellagio}%{!?with_omx:disabled} \ - -Dgallium-va=%{?with_vaapi:true}%{!?with_vaapi:false} \ - -Dgallium-xa=%{?with_xa:true}%{!?with_xa:false} \ - -Dgallium-nine=%{?with_nine:true}%{!?with_nine:false} \ - -Dgallium-opencl=%{?with_opencl:icd}%{!?with_opencl:disabled} \ - -Dvulkan-drivers=%{?vulkan_drivers} \ - -Dvulkan-layers=device-select \ - -Dshared-glapi=enabled \ - -Dgles1=disabled \ - -Dgles2=enabled \ - -Dopengl=true \ - -Dgbm=enabled \ - -Dglx=dri \ - -Degl=enabled \ - -Dglvnd=true \ - -Dmicrosoft-clc=disabled \ - -Dllvm=true \ - -Dshared-llvm=true \ - -Dvalgrind=%{?with_valgrind:true}%{!?with_valgrind:false} \ - -Dbuild-tests=false \ - -Dselinux=true \ - -Dlibunwind=disabled \ - -Dlmsensors=disabled \ - -Dandroid-libbacktrace=disabled \ - %{nil} -%meson_build - -%install -cd meson-0.61.4 -%py3_install -cd - -export PYTHONPATH=%{buildroot}/usr/lib/python3.6/site-packages/ -%meson_install - -#nuke the meson install bits -rm -rf %{buildroot}/usr/lib/python3.6/ -rm -f %{buildroot}/usr/bin/meson -rm -rf %{buildroot}/usr/share/man/ -rm -f %{buildroot}/usr/share/polkit-1/actions/com.mesonbuild.install.policy - -# libvdpau opens the versioned name, don't bother including the unversioned -rm -vf %{buildroot}%{_libdir}/vdpau/*.so -# likewise glvnd -rm -vf %{buildroot}%{_libdir}/libGLX_mesa.so -rm -vf %{buildroot}%{_libdir}/libEGL_mesa.so -# XXX can we just not build this -rm -vf %{buildroot}%{_libdir}/libGLES* - -# glvnd needs a default provider for indirect rendering where it cannot -# determine the vendor -ln -s %{_libdir}/libGLX_mesa.so.0 %{buildroot}%{_libdir}/libGLX_system.so.0 - -# strip out useless headers -rm -f %{buildroot}%{_includedir}/GL/w*.h - -# these are shipped already in vulkan-devel -rm -f %{buildroot}/%{_includedir}/vulkan/vk_platform.h -rm -f %{buildroot}/%{_includedir}/vulkan/vulkan.h - -# remove .la files -find %{buildroot} -name '*.la' -delete - -# this keeps breaking, check it early. note that the exit from eu-ftr is odd. -pushd %{buildroot}%{_libdir} -for i in libOSMesa*.so libGL.so ; do - eu-findtextrel $i && exit 1 -done - -%files filesystem -%doc docs/Mesa-MLAA-License-Clarification-Email.txt -%dir %{_libdir}/dri -%if %{with_hardware} -%if 0%{?with_vdpau} -%dir %{_libdir}/vdpau -%endif -%endif - -%files libGL -%{_libdir}/libGLX_mesa.so.0* -%{_libdir}/libGLX_system.so.0* -%files libGL-devel -%dir %{_includedir}/GL/internal -%{_includedir}/GL/internal/dri_interface.h -%{_libdir}/pkgconfig/dri.pc -%{_libdir}/libglapi.so - -%files libEGL -%{_datadir}/glvnd/egl_vendor.d/50_mesa.json -%{_libdir}/libEGL_mesa.so.0* -%files libEGL-devel -%dir %{_includedir}/EGL -%{_includedir}/EGL/eglmesaext.h -%{_includedir}/EGL/eglext_angle.h - -%post libglapi -p /sbin/ldconfig -%postun libglapi -p /sbin/ldconfig -%files libglapi -%{_libdir}/libglapi.so.0 -%{_libdir}/libglapi.so.0.* - -%post libOSMesa -p /sbin/ldconfig -%postun libOSMesa -p /sbin/ldconfig -%files libOSMesa -%{_libdir}/libOSMesa.so.8* -%files libOSMesa-devel -%dir %{_includedir}/GL -%{_includedir}/GL/osmesa.h -%{_libdir}/libOSMesa.so -%{_libdir}/pkgconfig/osmesa.pc - -%post libgbm -p /sbin/ldconfig -%postun libgbm -p /sbin/ldconfig -%files libgbm -%{_libdir}/libgbm.so.1 -%{_libdir}/libgbm.so.1.* -%files libgbm-devel -%{_libdir}/libgbm.so -%{_includedir}/gbm.h -%{_libdir}/pkgconfig/gbm.pc - -%if 0%{?with_xa} -%post libxatracker -p /sbin/ldconfig -%postun libxatracker -p /sbin/ldconfig -%files libxatracker -%if %{with_hardware} -%{_libdir}/libxatracker.so.2 -%{_libdir}/libxatracker.so.2.* -%endif - -%files libxatracker-devel -%if %{with_hardware} -%{_libdir}/libxatracker.so -%{_includedir}/xa_tracker.h -%{_includedir}/xa_composite.h -%{_includedir}/xa_context.h -%{_libdir}/pkgconfig/xatracker.pc -%endif -%endif - -%if 0%{?with_opencl} -%post libOpenCL -p /sbin/ldconfig -%postun libOpenCL -p /sbin/ldconfig -%files libOpenCL -%{_libdir}/libMesaOpenCL.so.* -%{_sysconfdir}/OpenCL/vendors/mesa.icd -%files libOpenCL-devel -%{_libdir}/libMesaOpenCL.so -%endif - -%if 0%{?with_nine} -%files libd3d -%dir %{_libdir}/d3d/ -%{_libdir}/d3d/*.so.* - -%files libd3d-devel -%{_libdir}/pkgconfig/d3d.pc -%{_includedir}/d3dadapter/ -%{_libdir}/d3d/*.so -%endif - -%files dri-drivers -%dir %{_datadir}/drirc.d -%{_datadir}/drirc.d/00-mesa-defaults.conf -%if %{with_hardware} -%{_libdir}/dri/r600_dri.so -%{_libdir}/dri/radeonsi_dri.so -%ifarch %{ix86} x86_64 -%{_libdir}/dri/crocus_dri.so -%{_libdir}/dri/iris_dri.so -%endif -%if 0%{?with_vc4} -%{_libdir}/dri/vc4_dri.so -%endif -%if 0%{?with_freedreno} -%{_libdir}/dri/kgsl_dri.so -%{_libdir}/dri/msm_dri.so -%endif -%if 0%{?with_etnaviv} -%{_libdir}/dri/etnaviv_dri.so -%{_libdir}/dri/imx-drm_dri.so -%endif -%{_libdir}/dri/nouveau_dri.so -%if 0%{?with_vmware} -%{_libdir}/dri/vmwgfx_dri.so -%endif -#{_libdir}/dri/nouveau_drv_video.so -#{_libdir}/dri/r600_drv_video.so -#{_libdir}/dri/radeonsi_drv_video.so -%endif -%{_libdir}/dri/kms_swrast_dri.so -%{_libdir}/dri/swrast_dri.so -%{_libdir}/dri/virtio_gpu_dri.so - -%if %{with_hardware} -%if 0%{?with_omx} -%files omx-drivers -%{_libdir}/bellagio/libomx_mesa.so -%endif -%if 0%{?with_vdpau} -%files vdpau-drivers -%{_libdir}/vdpau/libvdpau_virtio_gpu.so.1* -%{_libdir}/vdpau/libvdpau_nouveau.so.1* -%{_libdir}/vdpau/libvdpau_r600.so.1* -%{_libdir}/vdpau/libvdpau_radeonsi.so.1* -%endif -%endif - -%files vulkan-drivers -%if 0%{?with_vulkan_hw} -%{_libdir}/libvulkan_intel.so -%{_libdir}/libvulkan_intel_hasvk.so -%{_libdir}/libvulkan_radeon.so -%{_datadir}/drirc.d/00-radv-defaults.conf -%ifarch x86_64 -%{_datadir}/vulkan/icd.d/intel_icd.x86_64.json -%{_datadir}/vulkan/icd.d/intel_hasvk_icd.x86_64.json -%{_datadir}/vulkan/icd.d/radeon_icd.x86_64.json -%else -%{_datadir}/vulkan/icd.d/intel_icd.i686.json -%{_datadir}/vulkan/icd.d/intel_hasvk_icd.i686.json -%{_datadir}/vulkan/icd.d/radeon_icd.i686.json -%endif -%endif -%{_libdir}/libvulkan_lvp.so -%{_datadir}/vulkan/icd.d/lvp_icd.*.json -%{_libdir}/libVkLayer_MESA_device_select.so -%{_datadir}/vulkan/implicit_layer.d/VkLayer_MESA_device_select.json - -%if 0%{?with_vulkan_hw} -%files vulkan-devel -%endif - -%changelog -* Mon Mar 17 2025 Dave Airlie - 23.1.4-4 -- Fix two nouveau bugs for customer (RHEL-54452) - -* Thu Jun 20 2024 José Expósito - 23.1.4-3 -- Fix off-by-one error for newblock allocation in dlist_alloc - Resolves: https://issues.redhat.com/browse/RHEL-40566 - -* Thu Nov 23 2023 José Expósito - 23.1.4-2 -- Rebuild against LLVM 17 - -* Thu Jul 27 2023 Dave Airlie - 23.1.4-1 -- Update to 23.1.4 - -* Mon May 22 2023 Dave Airlie - 23.1.0-1 -- Update to 23.1.0 - -* Fri Jan 27 2023 Dave Airlie - 22.3.0-2 -- disable glthread for radeonsi (breaks totem) - -* Wed Dec 07 2022 Dave Airlie - 22.3.0-1 -- Update to 22.3.0 final + fix mit-shm regression - -* Fri Nov 25 2022 Dave Airlie - 22.3.0-0.4 -- Disable glthread for gnome-shell - -* Thu Nov 24 2022 Dave Airlie - 22.3.0-0.3 -- Update to 22.3.0-rc4 + fix wayland dep version - -* Wed Nov 23 2022 Dave Airlie - 22.3.0-0.2 -- Update to 22.3.0-rc3 + fix glthread regression fix - -* Fri Nov 11 2022 Dave Airlie - 22.3.0-0.1 -- Update to 22.3.0-rc2 - -* Tue Aug 09 2022 Dave Airlie - 22.1.5-1 -- Update to 22.1.5 - add some crocus and llvmpipe fixes - -* Mon Jun 06 2022 Dave Airlie - 22.1.1-1 -- Update to 22.1.1 - switch to crocus, drop legacy unused i965 driver. - -* Tue Jan 25 2022 Dave Airlie - 21.3.4-1 -- Update to 23.1.4 for gbm and leak fixes, add iris regression fix - -* Thu Nov 18 2021 Dave Airlie - 21.3.0-1 -- rebase to 23.1.0 - -* Thu Jul 22 2021 Dave Airlie - 21.1.5-1 -- Fix vulkan sw with wayland, pull in .4 + .5 fixes - -* Sat Jun 19 2021 Dave Airlie - 21.1.3-1 -- rebase to 21.1.3 - -* Tue Jun 01 2021 Dave Airlie - 21.1.1-2 -- rebuild against llvm 12 - -* Thu May 20 2021 Dave Airlie - 21.1.1-1 -- Update to 21.1.1 - -* Tue Feb 16 2021 Dave Airlie - 20.3.3-1 -- Update to 20.3.3 + upstream fixes for qemu regression - -* Mon Jan 11 2021 Dave Airlie - 20.3.2-1 -- Update to 20.3.2 for upstream fixes - -* Mon Dec 21 2020 Dave Airlie - 20.3.1-1 -- Update to 20.3.1 for radeon fix - -* Mon Dec 07 2020 Dave Airlie - 20.3.0-2 -- Fix regression with radeon si/cik cards - -* Fri Dec 04 2020 Dave Airlie - 20.3.0-1 -- Update to 20.3.0 release - -* Thu Nov 19 2020 Dave Airlie - 20.3.0-0.1.rc2 -- Update 20.3.0-rc2 -- enable lavapipe behind env var so it can be used for testing - -* Wed Aug 05 2020 Dave Airlie - 20.1.4-1 -- Update to 20.1.4 -- Update nouveau tu1xx support patch (Karol) - -* Mon Jun 29 2020 Dave Airlie - 20.1.2-3 -- a fix on top of the big-endian fix (#1847064) - -* Mon Jun 29 2020 Dave Airlie - 20.1.2-2 -- add another fix for big-endian llvmpipe (#1847064) - -* Mon Jun 29 2020 Dave Airlie - 20.1.2-1 -- Update to 20.1.2 -- add fix for big-endian llvmpipe (#1847064) - -* Thu Jun 11 2020 Dave Airlie - 20.1.1-1 -- Update to 20.1.1 -- Add support for turing - -* Thu May 28 2020 Dave Airlie - 20.1.0-1 -- Update to 20.1.0 final - -* Mon May 25 2020 Dave Airlie - 20.1.0-0.1.rc4 -- Update to 20.1.0-rc4 - -* Thu Feb 20 2020 Dave Airlie - 19.3.4-2 -- Fix put image shm fallback path. - -* Sat Feb 15 2020 Dave Airlie - 19.3.4-1 -- Update to 19.3.4 release (s390x fix) - -* Thu Jan 30 2020 Dave Airlie - 19.3.3-1 -- Update to 19.3.3 release - -* Mon Nov 25 2019 Dave Airlie - 19.3.0-3 -- drop khr-devel subpackage from here - -* Fri Nov 22 2019 Dave Airlie - 19.3.0-2 -- sort out libglvnd requires - -* Thu Nov 21 2019 Dave Airlie - 19.3.0-1 -- mesa-19.3.0-rc4 - -* Fri Aug 09 2019 Dave Airlie - 19.1.4-2 -- Add CET support to asm files - -* Mon Aug 05 2019 Dave Airlie - 19.1.4-1 -- mesa-19.1.4 - -* Thu Jun 06 2019 Dave Airlie - 19.1.0-0.5 -- mesa-19.1.0-rc5 - -* Thu May 30 2019 Dave Airlie - 19.1.0-0.4 -- mesa-19.1.0-rc4 - -* Wed May 22 2019 Dave Airlie - 19.1.0-0.3 -- mesa-19.1.0-rc3 -- disable asserts explicitly - -* Thu May 16 2019 Dave Airlie - 19.1.0-0.2 -- mesa 19.1.0-rc2 -- bring back glesv2.pc - -* Fri May 10 2019 Dave Airlie - 19.1.0-0.1 -- mesa 19.1.0-rc1 - -* Thu Apr 04 2019 Dave Airlie - 18.3.1-5 -- Fix remote shm detection again - -* Tue Mar 26 2019 Dave Airlie - 18.3.1-4 -- Fix remove shm detection - -* Wed Mar 20 2019 Dave Airlie - 18.3.1-3 -- Add shm leak fix - -* Tue Jan 29 2019 Dave Airlie - 18.3.1-2 -- fix shm swrast - -* Thu Dec 13 2018 Dave Airlie - 18.3.1-1 -- Mesa 18.3.1 - move to release - -* Wed Dec 12 2018 Tom Stellard -- Rebuild for LLVM 7.0.1 - -* Tue Nov 20 2018 Adam Jackson - 18.3.0-0.2 -- Mesa 18.3.0 RC2 -- Drop python3 build system backport -- Drop no-longer-necessary big-endian build fix -- Re-enable 10bpc fbconfigs - -* Wed Oct 10 2018 Adam Jackson - 18.2.2-1 -- Mesa 18.2.2 - -* Fri Sep 28 2018 Adam Jackson - 18.2.1-1 -- Mesa 18.2.1 -- Fix "HW cursor for format" error message flood with swrast - -* Fri Sep 28 2018 Adam Jackson - 18.2.0-2 -- Drop unneeded BuildRequires: makedepend - -* Tue Sep 11 2018 Dave Airlie - 18.2.0-1 -- mesa 18.2.0 - -* Thu Aug 16 2018 Ray Strode - 18.1.3-4 -- Fix crash on screen resolution change - Resolves: #1616390 - -* Thu Aug 02 2018 Tom Stellard - 18.1.3-3 -- Rebuild for LLVM 6.0 - -* Tue Jul 24 2018 Dave Airlie - 18.1.3-2 -- rename fallback for glvnd - -* Fri Jul 06 2018 Adam Jackson - 18.1.3-1 -- Mesa 18.1.3 - -* Wed Jun 20 2018 Adam Jackson - 18.1.2-2 -- Disable arm-specific drivers -- Use alternate glvnd indirect library name - -* Wed Jun 20 2018 Adam Jackson - 18.1.2-1 -- Mesa 18.1.2 - -* Mon Jun 18 2018 Adam Jackson - 18.0.5-1 -- Mesa 18.0.5 - -* Tue May 29 2018 Adam Jackson - 18.0.3-1 -- Mesa 18.0.3 -- Disable old drivers: radeon, r200, r300, i915, vieux - -* Fri May 04 2018 Dave Airlie - 18.0.2-2 -- Disable omx/opencl/nine - -* Tue May 01 2018 Adam Jackson - 18.0.2-1 -- Mesa 18.0.2 - -* Thu Mar 08 2018 Tom Stellard - 17.3.6-2 -- Use llvm-toolset - -* Tue Feb 27 2018 Adam Jackson - 17.3.6-1 -- Update to 17.3.6 - -* Mon Feb 26 2018 Igor Gnatenko - 17.3.5-2 -- Backport patch to fix video corruption - -* Tue Feb 20 2018 Igor Gnatenko - 17.3.5-1 -- Update to 17.3.5 - -* Thu Feb 15 2018 Igor Gnatenko - 17.3.4-1 -- Update to 17.3.4 - -* Mon Jan 22 2018 Peter Robinson 17.3.3-1 -- Update to 17.3.3 - -* Mon Jan 01 2018 Igor Gnatenko - 17.3.1-1 -- Update to 17.3.1 - -* Fri Nov 10 2017 Igor Gnatenko - 17.3.0-0.4.rc3 -- Sanitize tarball - -* Wed Nov 8 2017 Peter Robinson 17.3.0-0.3.rc3 -- Update to 17.3.0-rc3 - -* Tue Oct 31 2017 Peter Robinson 17.3.0-0.1.rc2 -- Update to 17.3.0-rc2 - -* Tue Oct 31 2017 Peter Robinson 17.2.4-1 -- Update to 17.2.4 GA - -* Mon Oct 23 2017 Tom Stellard - 17.2.3-2 -- Rebuild for LLVM 5.0.0 - -* Thu Oct 19 2017 Gwyn Ciesla - 17.2.3-1 -- 17.2.3, bugfix release. - -* Wed Oct 11 2017 Peter Robinson - 17.2.2-4 -- Fix for vc4/Raspberry Pi - -* Mon Oct 09 2017 Dave Airlie - 17.2.2-3 -- enable vulkan on 32-bit x86 - -* Tue Oct 03 2017 Adam Jackson - 17.2.2-2 -- Backport S3TC support from master - -* Tue Oct 3 2017 Peter Robinson 17.2.2-1 -- Update to 17.2.2 GA - -* Wed Sep 20 2017 Peter Robinson 17.2.1-1 -- Update to 17.2.1 GA - -* Mon Sep 11 2017 Peter Robinson 17.2.0-2 -- Add upstream patch for glibc xlocale.h change (fdo bz 102454) - -* Tue Sep 5 2017 Peter Robinson 17.2.0-1 -- Update to 17.2.0 GA - -* Thu Aug 31 2017 Peter Robinson 17.2.0-0.3.rc6 -- Update to 17.2.0-rc6 - -* Tue Aug 22 2017 Peter Robinson 17.2.0-0.2.rc5 -- Update to 17.2.0-rc5 - -* Sun Aug 13 2017 Peter Robinson 17.2.0-0.1.rc4 -- Update to 17.2.0-rc4 - -* Thu Aug 03 2017 Fedora Release Engineering - 17.1.5-1.2 -- Rebuilt for https://fedoraproject.org/wiki/Fedora_27_Binutils_Mass_Rebuild - -* Wed Jul 26 2017 Fedora Release Engineering - 17.1.5-1.1 -- Rebuilt for https://fedoraproject.org/wiki/Fedora_27_Mass_Rebuild - -* Mon Jul 17 2017 Peter Robinson 7.1.5-1 -- Update to 17.1.5 - -* Thu Jul 13 2017 Adam Jackson -- Stop replacing eglext.h, we're up to date again - -* Sat Jul 1 2017 Peter Robinson 7.1.4-1 -- Update to 17.1.4 - -* Mon Jun 19 2017 Peter Robinson 7.1.3-2 -- Fixes and perf improvements for vc4 - -* Mon Jun 19 2017 Peter Robinson 7.1.3-1 -- Update to 17.1.3 - -* Wed Jun 14 2017 Peter Robinson 7.1.2-2 -- Some etnaviv fixes - -* Mon Jun 5 2017 Peter Robinson 7.1.2-1 -- Update to 17.1.2 - -* Mon Jun 05 2017 Adam Jackson - 17.1.1-2 -- Disable BGRA8 images on Fermi - -* Thu May 25 2017 Peter Robinson 17.1.1-1 -- Update to 17.1.1 - -* Thu May 11 2017 Dave Airlie - 17.1.0-1 -- Update to 17.1.0 - -* Tue May 9 2017 Peter Robinson 17.1.0-0.4.rc4 -- Update to 17.1.0-rc4 - -* Fri Apr 28 2017 Peter Robinson 17.1.0-0.3.rc2 -- Enable renderonly support for i.MX SoC (rhbz #1424714) - -* Mon Apr 24 2017 Peter Robinson 17.1.0-0.2.rc2 -- Update to 17.1.0-rc2 - -* Tue Apr 18 2017 Igor Gnatenko - 17.1.0-0.1.rc1 -- Update to 17.1.0-rc1 - -* Sun Apr 02 2017 Igor Gnatenko - 17.0.3-1 -- Update to 17.0.3 - -* Fri Mar 24 2017 Igor Gnatenko - 17.0.2-2 -- Rebuild for LLVM4 - -* Mon Mar 20 2017 Peter Robinson 17.0.2-1 -- Update to 17.0.2 - -* Mon Mar 20 2017 Hans de Goede - 17.0.1-3 -- Fix glXGetDriverConfig not working with glvnd (rhbz#1429894) -- Fix indirect rendering, add libGLX_indirect.so.0 symlink (rhbz#1427174) - -* Tue Mar 14 2017 Peter Robinson 17.0.1-2 -- Rebuild for aarch64 llvmpipe fix (rhbz 1429050) - -* Sun Mar 05 2017 Igor Gnatenko - 17.0.1-1 -- Update to 17.0.1 - -* Mon Feb 13 2017 Peter Robinson 17.0.0-1 -- 17.0.0 GA - -* Mon Feb 6 2017 Peter Robinson 17.0.0-0.6.rc3 -- Update to 17.0.0-rc3 - -* Mon Feb 6 2017 Hans de Goede - 17.0.0-0.5.rc2 -- Fix GLX_SGIX_fbconfig extension dispatching with glvnd, this fixes games such - as "The Binding of Isaac: Rebirth" and "Crypt of the NecroDancer" from Steam - -* Thu Feb 2 2017 Hans de Goede - 17.0.0-0.4.rc2 -- Update eglext.h to 20161230 version this brings in some new defines needed - by some apps / libraries - -* Sat Jan 28 2017 Peter Robinson 17.0.0-0.3.rc2 -- Update to 17.0.0-rc2 - -* Sat Jan 21 2017 Peter Robinson 17.0.0-0.2.rc1 -- Enable etnaviv gallium driver - -* Fri Jan 20 2017 Igor Gnatenko - 17.0.0-0.rc1 -- Update to 17.0.0-rc1 - -* Tue Jan 17 2017 Hans de Goede - 13.0.3-3 -- Enable libglvnd support (rhbz#1413579) - -* Thu Jan 12 2017 Igor Gnatenko - 13.0.3-2 -- Add valgrind BuildRequires to have valgrind support - -* Fri Jan 6 2017 Peter Robinson 13.0.3-1 -- 13.0.3 GA - -* Mon Dec 12 2016 Igor Gnatenko - 13.0.2-2 -- Use nettle for sha1 - -* Tue Nov 29 2016 Peter Robinson 13.0.2-1 -- 13.0.2 GA - -* Tue Nov 15 2016 Peter Robinson 13.0.1-1 -- 13.0.1 GA - -* Wed Nov 2 2016 Peter Robinson 13.0.0-3 -- Don't ship duplicate vulkan devel headers - -* Wed Nov 2 2016 Peter Robinson 13.0.0-2 -- Add options for enabling vulkan components -- Enable intel/radeon vulkan drivers - -* Wed Nov 2 2016 Peter Robinson 13.0.0-1 -- 13.0.0 GA - -* Tue Nov 01 2016 Dave Airlie - 13.0.0-0.3.rc2 -- rebuild for llvm 3.9 - -* Mon Oct 24 2016 Peter Robinson 13.0.0-0.2.rc2 -- 13.0.0-rc2 - -* Thu Oct 20 2016 Igor Gnatenko - 13.0.0-0.1.rc1 -- 13.0.0-rc1 - -* Tue Oct 11 2016 Hans de Goede - 12.0.3-2 -- Add 2 patches from upstream to fix DRI3 vaapi crashes (rhbz1309446, fdo71759) - -* Sun Sep 18 2016 Peter Robinson 12.0.3-1 -- 12.0.3 - -* Mon Sep 5 2016 Peter Robinson 12.0.2-1 -- 12.0.2 - -* Mon Sep 5 2016 Hans de Goede - 12.0.1-7 -- Fix PRIME fd leak - -* Tue Aug 23 2016 Adam Jackson - 12.0.1-6 -- Remove BuildRequires: xorg-x11-server-devel - -* Mon Aug 15 2016 Igor Gnatenko - 12.0.1-5 -- Fix broken deps with OpenCL - -* Sun Aug 14 2016 Igor Gnatenko - 12.0.1-4 -- Fix broken deps - -* Sun Aug 14 2016 Igor Gnatenko - 12.0.1-3 -- Slightly refactor spec -- Drop virtual provides for OCL - -* Tue Jul 19 2016 Orion Poplawski - 12.0.1-2 -- Add missing %%{?_isa} to requires in some devel sub-packages (bug #1138463) - -* Sun Jul 10 2016 Igor Gnatenko - 12.0.1-1 -- 12.0.1 - -* Fri Jul 08 2016 Igor Gnatenko - 12.0.0-1 -- 12.0.0 - -* Wed Jun 22 2016 Igor Gnatenko - 12.0.0-0.3.rc4 -- 12.0.0-rc4 - -* Mon Jun 20 2016 Adam Jackson - 12.0.0-0.3.rc3 -- Fix packaging error on s390* - -* Mon Jun 20 2016 Igor Gnatenko - 12.0.0-0.2.rc3 -- 12.0.0-rc3 - -* Tue Jun 14 2016 Dominik Mierzejewski - 12.0.0-0.2.rc2 -- add missing dependency for /etc/OpenCL/vendors ownership (RHBZ #1265948) - -* Tue Jun 14 2016 Igor Gnatenko - 12.0.0-0.1.rc2 -- 12.0.0-rc2 - -* Wed Jun 01 2016 Igor Gnatenko - 12.0.0-0.1.rc1 -- 12.0.0-rc1 - -* Sun May 01 2016 Igor Gnatenko - 11.3.0-0.4.gitcbcd7b6 -- cbcd7b6 - -* Thu Apr 14 2016 Igor Gnatenko - 11.3.0-0.3.git171a570 -- 171a570 - -* Fri Apr 08 2016 Björn Esser - 11.3.0-0.2.gitea2bff1 -- add virtual Provides for ocl-icd (RHBZ #1317602) - -* Sun Mar 20 2016 Igor Gnatenko - 11.3.0-0.1.gitea2bff1 -- 11.3.0 (gitea2bff1) -- Add SWR state-tracker (but disable because build is broken) -- Use gallium-osmesa instead of classic osmesa (RHBZ #1305588) -- Remove very old changelogs - -* Sun Mar 20 2016 Igor Gnatenko - 11.2.0-0.1.rc3.20160320 -- Update to 11.2.0-rc3 - -* Fri Feb 19 2016 Dave Airlie 11.2.0-0.devel.11 -- rebuild against llvm 3.8.0 - -* Fri Feb 12 2016 Dave Airlie 11.2.0-0.devel.10 -- rebuild against new llvm packages - -* Thu Feb 11 2016 Adam Jackson 11.2.0-0.devel.9 -- Fix OpenCL-enabled FTBFS by not forcing clang search path to /usr/lib - -* Thu Feb 04 2016 Fedora Release Engineering - 11.2.0-0.devel.8.24ea81a.1 -- Rebuilt for https://fedoraproject.org/wiki/Fedora_24_Mass_Rebuild - -* Wed Jan 27 2016 Adam Jackson 11.2.0-0.devel.8 -- Rebuild for llvm 3.7.1 library split - -* Sun Jan 24 2016 Igor Gnatenko - 11.2.0-0.devel.7.24ea81a -- 24ea81a - -* Thu Jan 21 2016 Peter Robinson 11.2.0-0.devel.6.5e3edd4 -- OpenCL now supported on aarch64 - -* Sun Jan 10 2016 Igor Gnatenko - 11.2.0-0.devel.5.5e3edd4 -- 5e3edd4 - -* Thu Jan 07 2016 Adam Jackson -- Mangle libtool even harder to get -static-libstdc++ to work - -* Tue Dec 29 2015 Igor Gnatenko - 11.2.0-0.devel.3.70d8dbc -- 70d8dbc - -* Wed Dec 02 2015 Igor Gnatenko - 11.2.0-0.devel.2.56aff6b -- 56aff6b - -* Sun Nov 22 2015 Igor Gnatenko - 11.2.0-0.devel.1.86fc97d -- 86fc97d - -* Thu Nov 05 2015 Igor Gnatenko - 11.1.0-0.devel.13.5ae37ae -- 5ae37ae - -* Thu Nov 05 2015 Adam Jackson 11.1.0-0.devel.12.3994ef5 -- Link with -static-libstdc++ to work around Steam bundling its own copy - -* Fri Oct 23 2015 Igor Gnatenko - 11.1.0-0.devel.11.3994ef5 -- 3994ef5 -- Enable VirGL driver - -* Thu Oct 22 2015 Igor Gnatenko - 11.1.0-0.devel.10.7182498 -- 7182498 -- Disable SWR rasterizer - -* Wed Oct 21 2015 Igor Gnatenko - 11.1.0-0.devel.9.4a168ad -- Enable experimental SWR rasterizer - -* Wed Oct 14 2015 Igor Gnatenko - 11.1.0-0.devel.8.4a168ad -- 4a168ad - -* Wed Oct 07 2015 Igor Gnatenko - 11.1.0-0.devel.7.47d1199 -- 47d1199 - -* Sat Sep 26 2015 Igor Gnatenko - 11.1.0-0.devel.6.9932142 -- 9932142 - -* Wed Sep 16 2015 Igor Gnatenko - 11.1.0-0.devel.5.47e18a5 -- 47e18a5 -- Rebuild against llvm 3.7 - -* Sun Sep 13 2015 Igor Gnatenko - 11.1.0-0.devel.4.d6fbcf6 -- d6fbcf6 - -* Thu Sep 10 2015 Rex Dieter - 11.1.0-0.devel.3.60aea30 -- Add brw_meta_fast_clear crash workaround patch (#1259443, fdo#86281) - -* Wed Sep 02 2015 Igor Gnatenko - 11.1.0-0.devel.2.60aea30 -- 60aea30 - -* Mon Aug 24 2015 Igor Gnatenko - 11.1.0-0.devel.1.4e5752e -- 4e5752e - -* Sun Aug 09 2015 Igor Gnatenko - 11.0.0-0.devel.2.21ccdbd -- 21ccdbd -- add surfaceless EGL platform (RHBZ #1251747) - -* Sat Aug 01 2015 Igor Gnatenko - 11.0.0-0.devel.1.6f2d889 -- Update to 11.0.0 - -* Tue Jul 14 2015 Peter Robinson 10.7.0-0.devel.4.ea633db -- Use %%license -- Minor spec cleanups - -* Tue Jul 14 2015 Igor Gnatenko - 10.7.0-0.devel.3.ea633db -- ea633db - -* Tue Jul 07 2015 Igor Gnatenko - 10.7.0-0.devel.2.8787141 -- Drop unecessary make for s390 - -* Mon Jun 22 2015 Igor Gnatenko - 10.7.0-0.devel.1.8787141 -- 8787141 - -* Wed Jun 17 2015 Fedora Release Engineering - 10.6.0-0.devel.7.5a55f68.1 -- Rebuilt for https://fedoraproject.org/wiki/Fedora_23_Mass_Rebuild - -* Mon May 18 2015 Igor Gnatenko - 10.6.0-0.devel.7.5a55f68 -- add git to BR everywhere - -* Sun May 17 2015 Igor Gnatenko - 10.6.0-0.devel.6.5a55f68 -- 5a55f68 - -* Thu May 07 2015 Igor Gnatenko - 10.6.0-0.devel.5.51e3453 -- 51e3453 - -* Mon Apr 20 2015 Igor Gnatenko - 10.6.0-0.devel.4.c1485f4 -- c1485f4 - -* Thu Apr 09 2015 Adam Jackson 10.6.0-0.devel.3 -- F23 rebuild against llvm 3.6.0 - -* Fri Feb 27 2015 Rob Clark - 10.6.0-0.devel.1.f80af89 -- f80af89 - -* Wed Feb 18 2015 Igor Gnatenko - 10.5.0-1.20150218 -- 10.5.0 - -* Fri Jan 02 2015 Igor Gnatenko - 10.5.0-0.devel.32.6171131 -- 6171131 - -* Fri Jan 02 2015 Igor Gnatenko - 10.5.0-0.devel.31.c3260f8 -- c3260f8 - -* Fri Jan 02 2015 Igor Gnatenko - 10.5.0-0.devel.30.290553b -- 290553b - -* Thu Jan 01 2015 Igor Gnatenko - 10.5.0-0.devel.28.b77eaaf -- b77eaaf - -* Thu Jan 01 2015 Igor Gnatenko - 10.5.0-0.devel.26.c633528 -- c633528 - -* Thu Jan 01 2015 Igor Gnatenko - 10.5.0-0.devel.25.a6f6d61 -- a6f6d61 - -* Wed Dec 31 2014 Igor Gnatenko - 10.5.0-0.devel.23.be0311c -- be0311c - -* Wed Dec 31 2014 Igor Gnatenko - 10.5.0-0.devel.21.609c3e5 -- 609c3e5 - -* Wed Dec 31 2014 Igor Gnatenko - 10.5.0-0.devel.19.3ba57ba -- 3ba57ba - -* Tue Dec 30 2014 Igor Gnatenko - 10.5.0-0.devel.17.64dcb2b -- 64dcb2b - -* Mon Dec 29 2014 Igor Gnatenko - 10.5.0-0.devel.15.6c18279 -- 6c18279 - -* Sat Dec 27 2014 Igor Gnatenko - 10.5.0-0.devel.13.0c7f895 -- 0c7f895 - -* Fri Dec 26 2014 Igor Gnatenko - 10.5.0-0.devel.11.cb5a372 -- cb5a372 - -* Sun Dec 21 2014 Igor Gnatenko - 10.5.0-0.devel.10.git0d7f4c8 -- enable ilo gallium driver - -* Fri Dec 19 2014 Dan Horák 10.5.0-0.devel.9 -- Sync with_{vaapi,vdpau,nine} settings with F21 - -* Thu Dec 18 2014 Adam Jackson 10.5.0-0.devel.8 -- Sync ppc build config with F21 - -* Wed Dec 17 2014 Igor Gnatenko - 10.5.0-0.devel.7.git0d7f4c8 -- fix requirements for d3d - -* Sun Dec 14 2014 Igor Gnatenko - 10.5.0-0.devel.6.git0d7f4c8 -- 0d7f4c8 - -* Sun Dec 14 2014 Igor Gnatenko - 10.5.0-0.devel.5.git29c7cf2 -- Enable VA state-tracker -- Enable Nine state-tracker (Direct3D9 API) - -* Thu Dec 11 2014 Adam Jackson 10.5.0-0.devel.4 -- Restore hardware drivers on ppc64{,le} - -* Tue Dec 02 2014 Igor Gnatenko - 10.5.0-0.devel.3.git29c7cf2 -- 29c7cf2 - -* Sat Nov 22 2014 Igor Gnatenko - 10.5.0-0.devel.2.git3d9c1a9 -- 3d9c1a9 - -* Wed Nov 19 2014 Igor Gnatenko - 10.5.0-0.devel.1.git9460cd3 -- 9460cd3 - -* Mon Nov 10 2014 Igor Gnatenko - 10.4-0.devel.8.gitf3b709c -- f3b709c - -* Tue Oct 28 2014 10.4-0.devel.7.git1a17098 -- rebuild for llvm - -* Mon Oct 27 2014 Igor Gnatenko - 10.4-0.devel.6.git1a17098 -- 1a17098 - -* Sat Sep 27 2014 Igor Gnatenko - 10.4-0.devel.5.gitc3f17bb -- c3f17bb18f597d7f606805ae94363dae7fd51582 - -* Sat Sep 06 2014 Igor Gnatenko - 10.4-0.devel.4.git1f184bc -- apply patch for bigendian from karsten -- fix ppc filelist from karsten - -* Sat Sep 06 2014 Igor Gnatenko - 10.4-0.devel.3.git1f184bc -- 1f184bc114143acbcea373184260da777b6c6be1 commit - -* Thu Aug 28 2014 Igor Gnatenko - 10.4-0.devel.2.1.80771e47b6c1e47ab55f17311e1d4e227a9eb3d8 -- add swrast to dri driver list - -* Wed Aug 27 2014 Igor Gnatenko - 10.4-0.devel.2.80771e47b6c1e47ab55f17311e1d4e227a9eb3d8 -- 80771e47b6c1e47ab55f17311e1d4e227a9eb3d8 commit - -* Sat Aug 23 2014 Igor Gnatenko - 10.4-0.devel.1.c2867f5b3626157379ef0d4d5bcaf5180ca0ec1f -- 10.4 c2867f5b3626157379ef0d4d5bcaf5180ca0ec1f - -* Fri Aug 22 2014 Igor Gnatenko - 10.3-0.rc1.1.e7f2f2dea5acdbd1a12ed88914e64a38a97432f0 -- e7f2f2dea5acdbd1a12ed88914e64a38a97432f0 commit - -* Sun Aug 17 2014 Fedora Release Engineering - 10.3-0.devel.2.c40d7d6d948912a4d51cbf8f0854cf2ebe916636.1 -- Rebuilt for https://fedoraproject.org/wiki/Fedora_21_22_Mass_Rebuild - -* Wed Aug 06 2014 Igor Gnatenko - 10.3-0.devel.2.c40d7d6d948912a4d51cbf8f0854cf2ebe916636 -- c40d7d6d948912a4d51cbf8f0854cf2ebe916636 commit - -* Fri Jul 11 2014 Igor Gnatenko - 10.3-0.devel.1.f381c27c548aa28b003c8e188f5d627ab4105f76 -- Rebase to 'master' branch (f381c27c548aa28b003c8e188f5d627ab4105f76 commit) - -* Fri Jul 11 2014 Igor Gnatenko - 10.2.3-1.20140711 -- 10.2.3 upstream release - -* Mon Jul 7 2014 Peter Robinson 10.2.2-4.20140625 -- Build aarch64 options the same as ARMv7 -- Fix PPC conditionals - -* Fri Jul 04 2014 Igor Gnatenko - 10.2.2-3.20140625 -- Fix up intelInitScreen2 for DRI3 (RHBZ #1115323) (patch from drago01) - -* Fri Jun 27 2014 Dave Airlie 10.2.2-2.20140625 -- add dri3 gnome-shell startup fix from Jasper. - -* Wed Jun 25 2014 Igor Gnatenko - 10.2.2-1.20140625 -- 10.2.2 upstream release - -* Wed Jun 11 2014 Igor Gnatenko - 10.2.1-2.20140608 -- drop radeonsi llvm hack - -* Sun Jun 08 2014 Igor Gnatenko - 10.2.1-1.20140608 -- 10.2.1 upstream release - -* Sat Jun 07 2014 Fedora Release Engineering - 10.2-0.11.rc5.20140531 -- Rebuilt for https://fedoraproject.org/wiki/Fedora_21_Mass_Rebuild - -* Wed Jun 04 2014 Dan Horák - 10.2-0.10.rc5.20140531 -- fix build without hardware drivers - -* Sat May 31 2014 Igor Gnatenko - 10.2-0.9.rc5.20140531 -- 10.2-rc5 upstream release - -* Wed May 28 2014 Brent Baude - 10.2-0.8.rc4.20140524 -- Removing ppc64le arch from with_llvm - -* Wed May 28 2014 Igor Gnatenko - 10.2-0.7.rc4.20140524 -- i915: add a missing NULL pointer check (RHBZ #1100967) - -* Sat May 24 2014 Igor Gnatenko - 10.2-0.6.rc4.20140524 -- 10.2-rc4 upstream release -- add back updated radeonsi hack for LLVM - -* Sat May 17 2014 Igor Gnatenko - 10.2-0.5.rc3.20140517 -- 10.2-rc3 upstream release - -* Sat May 10 2014 Igor Gnatenko - 10.2-0.4.rc2.20140510 -- 10.2-rc2 upstream release -- drop radeonsi hack for LLVM - -* Tue May 06 2014 Igor Gnatenko - 10.2-0.3.rc1.20140505 -- Move gallium-pipe to the correct sub-package (RHBZ #1094588) (kwizart) -- Move egl_gallium.so to the correct location (RHBZ #1094588) (kwizart) -- Switch from with to enable for llvm shared libs (kwizart) - -* Mon May 05 2014 Igor Gnatenko - 10.2-0.2.rc1.20140505 -- Enable gallium-egl (needed by freedreeno) (RHBZ #1094199) (kwizart) - -* Mon May 05 2014 Igor Gnatenko - 10.2-0.1.rc1.20140505 -- Enable omx on x86 and arm (RHBZ #1094199) (kwizart) -- Split _with_xa from _with_vmware (RHBZ #1094199) (kwizart) -- Add _with_xa when arch is arm and _with_freedreeno (RHBZ #1094199) (kwizart) - -* Mon May 05 2014 Igor Gnatenko - 10.2-0.rc1.20140505 -- 10.2-rc1 upstream release - -* Wed Apr 30 2014 Igor Gnatenko - 10.1.1-3.20140430 -- Update to today snapshot -- apply as downstream patches for reporting GPU max frequency on r600 (FD.o #73511) - -* Sat Apr 19 2014 Igor Gnatenko - 10.1.1-2.20140419 -- fix buildrequires llvm 3.4-5 to 3.4-6, because 3.4-5 is not available for F20 - -* Sat Apr 19 2014 Igor Gnatenko - 10.1.1-1.20140419 -- 10.1.1 upstream release - -* Tue Apr 15 2014 Adam Jackson 10.1-6.20140305 -- Disable DRI3 in F20, it requires libxcb bits we haven't backported. - -* Wed Mar 26 2014 Adam Jackson 10.1-5.20140305 -- Initial ppc64le enablement (no hardware drivers or vdpau yet) - -* Fri Mar 21 2014 Adam Jackson 10.1-4.20140305 -- mesa: Don't optimize out glClear if drawbuffer size is 0x0 (fdo #75797) - -* Wed Mar 19 2014 Dave Airlie 10.1-3.20140305 -- rebuild against backported llvm 3.4-5 for radeonsi GL 3.3 support. - -* Wed Mar 12 2014 Dave Airlie 10.1-2.20140305 -- disable r600 llvm compiler (upstream advice) - -* Wed Mar 05 2014 Igor Gnatenko - 10.1-1.20140305 -- mesa: Bump version to 10.1 (final) (Ian Romanick) -- glx/dri2: fix build failure on HURD (Julien Cristau) -- i965: Validate (and resolve) all the bound textures. (Chris Forbes) -- i965: Widen sampler key bitfields for 32 samplers (Chris Forbes) - -* Sat Mar 01 2014 Igor Gnatenko - 10.1-0.rc3.20140301 -- 10.1-rc3 - -* Tue Feb 25 2014 Igor Gnatenko - 10.1-0.rc2.20140225 -- really 10.1-rc2 - -* Sat Feb 22 2014 Igor Gnatenko - 10.1-0.rc2.20140222 -- 10.1-rc2 - -* Sat Feb 08 2014 Adel Gadllah - 10.1-0.rc1.20140208 -- 10.1rc1 -- Drop upstreamed patches - -* Thu Feb 06 2014 Igor Gnatenko - 10.0.3-1.20140206 -- 10.0.3 upstream release - -* Tue Feb 04 2014 Kyle McMartin - 10.0.2-6.20140118 -- Fix accidentally inverted logic that meant radeonsi_dri.so went missing - on all architectures instead of just ppc and s390. Sorry! - -* Sun Feb 02 2014 Kyle McMartin - 10.0.2-5.20140118 -- Fix a thinko in previous commit wrt libdrm_nouveau2. - -* Sun Feb 02 2014 Kyle McMartin - 10.0.2-4.20140118 -- Fix up building drivers on AArch64, enable LLVM there. -- Eliminate some F17 cruft from the spec, since we don't support it anymore. -- Conditionalize with_radeonsi on with_llvm instead of ppc,s390 && >F-17. -- Conditionalize libvdpau_radeonsi.so.1* on with_radeonsi instead of simply - with_llvm to fix a build failure on AArch64. - -* Sun Jan 19 2014 Igor Gnatenko - 10.0.2-3.20140118 -- Enable OpenCL (RHBZ #887628) -- Enable r600 llvm compiler (RHBZ #1055098) diff --git a/SOURCES/gnome-shell-glthread-disable.patch b/gnome-shell-glthread-disable.patch similarity index 100% rename from SOURCES/gnome-shell-glthread-disable.patch rename to gnome-shell-glthread-disable.patch diff --git a/mesa.spec b/mesa.spec new file mode 100644 index 0000000..a83827b --- /dev/null +++ b/mesa.spec @@ -0,0 +1,1967 @@ +## START: Set by rpmautospec +## (rpmautospec version 0.6.5) +## RPMAUTOSPEC: autorelease, autochangelog +%define autorelease(e:s:pb:n) %{?-p:0.}%{lua: + release_number = 2; + base_release_number = tonumber(rpm.expand("%{?-b*}%{!?-b:1}")); + print(release_number + base_release_number - 1); +}%{?-e:.%{-e*}}%{?-s:.%{-s*}}%{!?-n:%{?dist}} +## END: Set by rpmautospec + +%ifnarch s390x +%global with_hardware 1 +%global with_radeonsi 1 +%global with_vmware 1 +%global with_vulkan_hw 1 +%global with_vdpau 1 +%global with_va 1 +%if !0%{?rhel} +%global with_r300 1 +%global with_r600 1 +%global with_nine 1 +%if 0%{?with_vulkan_hw} +%global with_nvk %{with_vulkan_hw} +%endif +%global with_opencl 1 +%endif +%global base_vulkan %{?with_vulkan_hw:,amd}%{!?with_vulkan_hw:%{nil}} +%endif + +%ifnarch %{ix86} +%if !0%{?rhel} +%global with_teflon 1 +%endif +%endif + +%ifarch %{ix86} x86_64 +%global with_iris 1 +%global with_crocus 1 +%global with_xa 1 +%global with_intel_clc 1 +%global intel_platform_vulkan %{?with_vulkan_hw:,intel,intel_hasvk}%{!?with_vulkan_hw:%{nil}} +%endif +%ifarch x86_64 +%if !0%{?with_vulkan_hw} +%global with_intel_vk_rt 1 +%endif +%endif + +%ifarch aarch64 x86_64 %{ix86} +%if !0%{?rhel} +%global with_etnaviv 1 +%global with_lima 1 +%global with_tegra 1 +%global with_vc4 1 +%global with_v3d 1 +%endif +%global with_freedreno 1 +%global with_kmsro 1 +%global with_panfrost 1 +%global with_xa 1 +%global extra_platform_vulkan %{?with_vulkan_hw:,broadcom,freedreno,panfrost,imagination-experimental}%{!?with_vulkan_hw:%{nil}} +%endif + +%if !0%{?rhel} +%global with_libunwind 1 +%global with_lmsensors 1 +%endif + +%ifarch %{valgrind_arches} +%bcond_without valgrind +%else +%bcond_with valgrind +%endif + +%global vulkan_drivers swrast%{?base_vulkan}%{?intel_platform_vulkan}%{?extra_platform_vulkan}%{?with_nvk:,nouveau} + +Name: mesa +Summary: Mesa graphics libraries +%global ver 24.2.8 +Version: %{lua:ver = string.gsub(rpm.expand("%{ver}"), "-", "~"); print(ver)} +Release: %autorelease +License: MIT AND BSD-3-Clause AND SGI-B-2.0 +URL: http://www.mesa3d.org + +Source0: https://archive.mesa3d.org/mesa-%{ver}.tar.xz +# src/gallium/auxiliary/postprocess/pp_mlaa* have an ... interestingly worded license. +# Source1 contains email correspondence clarifying the license terms. +# Fedora opts to ignore the optional part of clause 2 and treat that code as 2 clause BSD. +Source1: Mesa-MLAA-License-Clarification-Email.txt + +# libclc is not available in RHEL but it is required for Intel drivers since +# mesa >= 24.1.0 +%global libclc_version 19.1.1 +Source3: https://github.com/llvm/llvm-project/releases/download/llvmorg-%{libclc_version}/libclc-%{libclc_version}.src.tar.xz +BuildRequires: libedit-devel +BuildRequires: clang-devel >= %{libclc_version} +# Build our own version +# BuildRequires: spirv-llvm-translator-tools + +# spirv-llvm-translator is a dependency of libclc +%global spirv_llvm_trans_ver 19.1.1 +%global spirv_llvm_trans_commit 90a976491d3847657396456e0e94d7dc48d35996 +%global spirv_llvm_trans_shortcommit %(c=%{spirv_llvm_trans_commit}; echo ${c:0:7}) +Source4: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/archive/%{spirv_llvm_trans_commit}/spirv-llvm-translator-%{spirv_llvm_trans_shortcommit}.tar.gz +BuildRequires: cmake +BuildRequires: ninja-build +BuildRequires: llvm-static +BuildRequires: spirv-headers-devel +BuildRequires: spirv-tools-devel +BuildRequires: zlib-devel + +Patch10: gnome-shell-glthread-disable.patch + +# AMD Navi4x support: +# Backport fixes for radeonsi and disable GFX12 on radv +# https://issues.redhat.com/browse/RHEL-53423 +Patch11: RHEL-53423.patch + +BuildRequires: meson +BuildRequires: gcc +BuildRequires: gcc-c++ +BuildRequires: gettext +%if 0%{?with_hardware} +BuildRequires: kernel-headers +%endif +# We only check for the minimum version of pkgconfig(libdrm) needed so that the +# SRPMs for each arch still have the same build dependencies. See: +# https://bugzilla.redhat.com/show_bug.cgi?id=1859515 +BuildRequires: pkgconfig(libdrm) >= 2.4.121 +%if 0%{?with_libunwind} +BuildRequires: pkgconfig(libunwind) +%endif +BuildRequires: pkgconfig(expat) +BuildRequires: pkgconfig(zlib) >= 1.2.3 +BuildRequires: pkgconfig(libzstd) +BuildRequires: pkgconfig(libselinux) +BuildRequires: pkgconfig(wayland-scanner) +BuildRequires: pkgconfig(wayland-protocols) >= 1.34 +BuildRequires: pkgconfig(wayland-client) >= 1.11 +BuildRequires: pkgconfig(wayland-server) >= 1.11 +BuildRequires: pkgconfig(wayland-egl-backend) >= 3 +BuildRequires: pkgconfig(x11) +BuildRequires: pkgconfig(xext) +BuildRequires: pkgconfig(xdamage) >= 1.1 +BuildRequires: pkgconfig(xfixes) +BuildRequires: pkgconfig(xcb-glx) >= 1.8.1 +BuildRequires: pkgconfig(xxf86vm) +BuildRequires: pkgconfig(xcb) +BuildRequires: pkgconfig(x11-xcb) +BuildRequires: pkgconfig(xcb-dri2) >= 1.8 +BuildRequires: pkgconfig(xcb-dri3) +BuildRequires: pkgconfig(xcb-present) +BuildRequires: pkgconfig(xcb-sync) +BuildRequires: pkgconfig(xshmfence) >= 1.1 +BuildRequires: pkgconfig(dri2proto) >= 2.8 +BuildRequires: pkgconfig(glproto) >= 1.4.14 +BuildRequires: pkgconfig(xcb-xfixes) +BuildRequires: pkgconfig(xcb-randr) +BuildRequires: pkgconfig(xrandr) >= 1.3 +BuildRequires: bison +BuildRequires: flex +%if 0%{?with_lmsensors} +BuildRequires: lm_sensors-devel +%endif +%if 0%{?with_vdpau} +BuildRequires: pkgconfig(vdpau) >= 1.1 +%endif +%if 0%{?with_va} +BuildRequires: pkgconfig(libva) >= 0.38.0 +%endif +BuildRequires: pkgconfig(libelf) +BuildRequires: pkgconfig(libglvnd) >= 1.3.2 +BuildRequires: llvm-devel >= %{libclc_version} +%if 0%{?with_teflon} +BuildRequires: flatbuffers-devel +BuildRequires: flatbuffers-compiler +BuildRequires: xtensor-devel +%endif +%if 0%{?with_opencl} || 0%{?with_nvk} || 0%{?with_intel_clc} +BuildRequires: clang-devel +# Build our own version +# BuildRequires: pkgconfig(libclc) +# BuildRequires: pkgconfig(LLVMSPIRVLib) +BuildRequires: pkgconfig(SPIRV-Tools) +%endif +%if 0%{?with_opencl} || 0%{?with_nvk} +BuildRequires: bindgen +BuildRequires: rust-packaging +%endif +%if 0%{?with_nvk} +BuildRequires: cbindgen +BuildRequires: (crate(paste) >= 1.0.14 with crate(paste) < 2) +BuildRequires: (crate(proc-macro2) >= 1.0.56 with crate(proc-macro2) < 2) +BuildRequires: (crate(quote) >= 1.0.25 with crate(quote) < 2) +BuildRequires: (crate(syn/clone-impls) >= 2.0.15 with crate(syn/clone-impls) < 3) +BuildRequires: (crate(unicode-ident) >= 1.0.6 with crate(unicode-ident) < 2) +%endif +%if %{with valgrind} +BuildRequires: pkgconfig(valgrind) +%endif +BuildRequires: python3-devel +BuildRequires: python3-mako +%if 0%{?with_intel_clc} +BuildRequires: python3-ply +%endif +BuildRequires: python3-pycparser +BuildRequires: python3-pyyaml +BuildRequires: vulkan-headers +BuildRequires: glslang +%if 0%{?with_vulkan_hw} +BuildRequires: pkgconfig(vulkan) +%endif + +%description +%{summary}. + +%package filesystem +Summary: Mesa driver filesystem +Provides: mesa-dri-filesystem = %{?epoch:%{epoch}:}%{version}-%{release} +Obsoletes: mesa-omx-drivers < %{?epoch:%{epoch}:}%{version}-%{release} + +%description filesystem +%{summary}. + +%package libGL +Summary: Mesa libGL runtime libraries +Requires: %{name}-libglapi%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +Requires: libglvnd-glx%{?_isa} >= 1:1.3.2 +Recommends: %{name}-dri-drivers%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} + +%description libGL +%{summary}. + +%package libGL-devel +Summary: Mesa libGL development package +Requires: %{name}-libGL%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +Requires: libglvnd-devel%{?_isa} >= 1:1.3.2 +Provides: libGL-devel +Provides: libGL-devel%{?_isa} +Recommends: gl-manpages + +%description libGL-devel +%{summary}. + +%package libEGL +Summary: Mesa libEGL runtime libraries +Requires: libglvnd-egl%{?_isa} >= 1:1.3.2 +Requires: %{name}-libgbm%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +Requires: %{name}-libglapi%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +Recommends: %{name}-dri-drivers%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} + +%description libEGL +%{summary}. + +%package libEGL-devel +Summary: Mesa libEGL development package +Requires: %{name}-libEGL%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +Requires: libglvnd-devel%{?_isa} >= 1:1.3.2 +Requires: %{name}-khr-devel%{?_isa} +Provides: libEGL-devel +Provides: libEGL-devel%{?_isa} + +%description libEGL-devel +%{summary}. + +%package dri-drivers +Summary: Mesa-based DRI drivers +Requires: %{name}-filesystem%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +Requires: %{name}-libglapi%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +%if 0%{?with_va} +Recommends: %{name}-va-drivers%{?_isa} +%endif + +%description dri-drivers +%{summary}. + +%if 0%{?with_va} +%package va-drivers +Summary: Mesa-based VA-API video acceleration drivers +Requires: %{name}-filesystem%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +Obsoletes: %{name}-vaapi-drivers < 22.2.0-5 + +%description va-drivers +%{summary}. +%endif + +%if 0%{?with_vdpau} +%package vdpau-drivers +Summary: Mesa-based VDPAU drivers +Requires: %{name}-filesystem%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} + +%description vdpau-drivers +%{summary}. +%endif + +%package libOSMesa +Summary: Mesa offscreen rendering libraries +Requires: %{name}-libglapi%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +Provides: libOSMesa +Provides: libOSMesa%{?_isa} + +%description libOSMesa +%{summary}. + +%package libOSMesa-devel +Summary: Mesa offscreen rendering development package +Requires: %{name}-libOSMesa%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} + +%description libOSMesa-devel +%{summary}. + +%package libgbm +Summary: Mesa gbm runtime library +Provides: libgbm +Provides: libgbm%{?_isa} +Recommends: %{name}-dri-drivers%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +# If mesa-dri-drivers are installed, they must match in version. This is here to prevent using +# older mesa-dri-drivers together with a newer mesa-libgbm and its dependants. +# See https://bugzilla.redhat.com/show_bug.cgi?id=2193135 . +Requires: (%{name}-dri-drivers%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} if %{name}-dri-drivers%{?_isa}) + +%description libgbm +%{summary}. + +%package libgbm-devel +Summary: Mesa libgbm development package +Requires: %{name}-libgbm%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +Provides: libgbm-devel +Provides: libgbm-devel%{?_isa} + +%description libgbm-devel +%{summary}. + +%if 0%{?with_xa} +%package libxatracker +Summary: Mesa XA state tracker +Provides: libxatracker +Provides: libxatracker%{?_isa} + +%description libxatracker +%{summary}. + +%package libxatracker-devel +Summary: Mesa XA state tracker development package +Requires: %{name}-libxatracker%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +Provides: libxatracker-devel +Provides: libxatracker-devel%{?_isa} + +%description libxatracker-devel +%{summary}. +%endif + +%package libglapi +Summary: Mesa shared glapi +Provides: libglapi +Provides: libglapi%{?_isa} +# If mesa-dri-drivers are installed, they must match in version. This is here to prevent using +# older mesa-dri-drivers together with a newer mesa-libglapi or its dependants. +# See https://bugzilla.redhat.com/show_bug.cgi?id=2193135 . +Requires: (%{name}-dri-drivers%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} if %{name}-dri-drivers%{?_isa}) + +%description libglapi +%{summary}. + +%if 0%{?with_opencl} +%package libOpenCL +Summary: Mesa OpenCL runtime library +Requires: ocl-icd%{?_isa} +Requires: libclc%{?_isa} +Requires: %{name}-libgbm%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +Requires: opencl-filesystem + +%description libOpenCL +%{summary}. + +%package libOpenCL-devel +Summary: Mesa OpenCL development package +Requires: %{name}-libOpenCL%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} + +%description libOpenCL-devel +%{summary}. +%endif + +%if 0%{?with_teflon} +%package libTeflon +Summary: Mesa TensorFlow Lite delegate + +%description libTeflon +%{summary}. +%endif + +%if 0%{?with_nine} +%package libd3d +Summary: Mesa Direct3D9 state tracker + +%description libd3d +%{summary}. + +%package libd3d-devel +Summary: Mesa Direct3D9 state tracker development package +Requires: %{name}-libd3d%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} + +%description libd3d-devel +%{summary}. +%endif + +%package vulkan-drivers +Summary: Mesa Vulkan drivers +Requires: vulkan%{_isa} +Requires: %{name}-filesystem%{?_isa} = %{?epoch:%{epoch}:}%{version}-%{release} +Obsoletes: mesa-vulkan-devel < %{?epoch:%{epoch}:}%{version}-%{release} + +%description vulkan-drivers +The drivers with support for the Vulkan API. + +%prep +%autosetup -n %{name}-%{ver} -p1 +cp %{SOURCE1} docs/ + +# Extract libclc +tar -xvf %{SOURCE3} + +# Extract spirv-llvm-translator +tar -xvf %{SOURCE4} + +%build +# Build spirv-llvm-translator +cd SPIRV-LLVM-Translator-%{spirv_llvm_trans_commit} +%cmake -GNinja \ + -DLLVM_BUILD_TOOLS=ON \ + -DCMAKE_BUILD_TYPE=RelWithDebInfo \ + -DCMAKE_INSTALL_RPATH:BOOL=";" \ + -DLLVM_DIR="/usr/lib64/cmake/llvm/" \ +%if 0%{?__isa_bits} == 64 + -DLLVM_LIBDIR_SUFFIX=64 \ +%else + -DLLVM_LIBDIR_SUFFIX= \ +%endif + -DLLVM_EXTERNAL_PROJECTS="SPIRV-Headers" \ + -DLLVM_EXTERNAL_SPIRV_HEADERS_SOURCE_DIR="/usr/include/spirv/" +%cmake_build +%cmake_install +cd - + +export LIBRARY_PATH=%{buildroot}%{_libdir}:$LIBRARY_PATH +export LD_LIBRARY_PATH=%{buildroot}%{_libdir}:$LD_LIBRARY_PATH +export XDG_DATA_DIRS=%{buildroot}%{_datadir}:$XDG_DATA_DIRS +export CPATH=%{buildroot}%{_includedir}:$CPATH +export PKG_CONFIG_PATH=%{buildroot}%{_libdir}/pkgconfig:%{buildroot}%{_datadir}/pkgconfig:$PKG_CONFIG_PATH +export PATH=%{buildroot}%{_bindir}:$PATH + +# Build libclc +cd libclc-%{libclc_version}.src +export CFLAGS="%{build_cflags} -D__extern_always_inline=inline" +%cmake -GNinja \ + -DCMAKE_INSTALL_DATADIR:PATH=%{_lib} \ + -DLIBCLC_TARGETS_TO_BUILD="spirv-mesa3d-;spirv64-mesa3d-" \ + -DLLVM_SPIRV=%{buildroot}%{_bindir}/llvm-spirv +%cmake_build +%cmake_install +cd - +sed -e "s!libexecdir=!libexecdir=\/%{buildroot}!" -i %{buildroot}%{_libdir}/pkgconfig/libclc.pc + +# ensure standard Rust compiler flags are set +export RUSTFLAGS="%build_rustflags" + +%if 0%{?with_nvk} +export MESON_PACKAGE_CACHE_DIR="%{cargo_registry}/" +# So... Meson can't actually find them without tweaks +%define inst_crate_nameversion() %(basename %{cargo_registry}/%{1}-*) +%define rewrite_wrap_file() sed -e "/source.*/d" -e "s/%{1}-.*/%{inst_crate_nameversion %{1}}/" -i subprojects/%{1}.wrap + +%rewrite_wrap_file proc-macro2 +%rewrite_wrap_file quote +%rewrite_wrap_file syn +%rewrite_wrap_file unicode-ident +%rewrite_wrap_file paste +%endif + +# We've gotten a report that enabling LTO for mesa breaks some games. See +# https://bugzilla.redhat.com/show_bug.cgi?id=1862771 for details. +# Disable LTO for now +%define _lto_cflags %{nil} + +%meson \ + -Dplatforms=x11,wayland \ + -Ddri3=enabled \ + -Dosmesa=true \ +%if 0%{?with_hardware} + -Dgallium-drivers=swrast,virgl,nouveau%{?with_r300:,r300}%{?with_crocus:,crocus}%{?with_iris:,iris}%{?with_vmware:,svga}%{?with_radeonsi:,radeonsi}%{?with_r600:,r600}%{?with_freedreno:,freedreno}%{?with_etnaviv:,etnaviv}%{?with_tegra:,tegra}%{?with_vc4:,vc4}%{?with_v3d:,v3d}%{?with_lima:,lima}%{?with_panfrost:,panfrost}%{?with_vulkan_hw:,zink} \ +%else + -Dgallium-drivers=swrast,virgl \ +%endif + -Dgallium-vdpau=%{?with_vdpau:enabled}%{!?with_vdpau:disabled} \ + -Dgallium-va=%{?with_va:enabled}%{!?with_va:disabled} \ + -Dgallium-xa=%{?with_xa:enabled}%{!?with_xa:disabled} \ + -Dgallium-nine=%{?with_nine:true}%{!?with_nine:false} \ + -Dteflon=%{?with_teflon:true}%{!?with_teflon:false} \ + -Dgallium-opencl=%{?with_opencl:icd}%{!?with_opencl:disabled} \ +%if 0%{?with_opencl} + -Dgallium-rusticl=true \ +%endif + -Dvulkan-drivers=%{?vulkan_drivers} \ + -Dvulkan-layers=device-select \ + -Dshared-glapi=enabled \ + -Dgles1=enabled \ + -Dgles2=enabled \ + -Dopengl=true \ + -Dgbm=enabled \ + -Dglx=dri \ + -Degl=enabled \ + -Dglvnd=enabled \ +%if 0%{?with_intel_clc} + -Dintel-clc=enabled \ +%endif + -Dintel-rt=%{?with_intel_vk_rt:enabled}%{!?with_intel_vk_rt:disabled} \ + -Dmicrosoft-clc=disabled \ + -Dllvm=enabled \ + -Dshared-llvm=enabled \ + -Dvalgrind=%{?with_valgrind:enabled}%{!?with_valgrind:disabled} \ + -Dbuild-tests=false \ + -Dselinux=true \ +%if !0%{?with_libunwind} + -Dlibunwind=disabled \ +%endif +%if !0%{?with_lmsensors} + -Dlmsensors=disabled \ +%endif + -Dandroid-libbacktrace=disabled \ +%ifarch %{ix86} + -Dglx-read-only-text=true \ +%endif + %{nil} +%meson_build + +%install +%meson_install + +# Delete files installed by libclc +rm -fr %{buildroot}%{_libdir}/clc +rm -f %{buildroot}%{_libdir}/pkgconfig/libclc.pc + +# Delete files installed by spirv-llvm-translator +rm -f %{buildroot}%{_bindir}/llvm-spirv +rm -fr %{buildroot}%{_includedir}/LLVMSPIRVLib +rm -f %{buildroot}%{_libdir}/libLLVMSPIRVLib.so +rm -f %{buildroot}%{_libdir}/libLLVMSPIRVLib.so.* +rm -f %{buildroot}%{_libdir}/pkgconfig/LLVMSPIRVLib.pc + +# libvdpau opens the versioned name, don't bother including the unversioned +rm -vf %{buildroot}%{_libdir}/vdpau/*.so +# likewise glvnd +rm -vf %{buildroot}%{_libdir}/libGLX_mesa.so +rm -vf %{buildroot}%{_libdir}/libEGL_mesa.so +# XXX can we just not build this +rm -vf %{buildroot}%{_libdir}/libGLES* + +# glvnd needs a default provider for indirect rendering where it cannot +# determine the vendor +ln -s %{_libdir}/libGLX_mesa.so.0 %{buildroot}%{_libdir}/libGLX_system.so.0 + +# this keeps breaking, check it early. note that the exit from eu-ftr is odd. +pushd %{buildroot}%{_libdir} +for i in libOSMesa*.so libGL.so ; do + eu-findtextrel $i && exit 1 +done +popd + +%files filesystem +%doc docs/Mesa-MLAA-License-Clarification-Email.txt +%dir %{_libdir}/dri +%dir %{_datadir}/drirc.d + +%files libGL +%{_libdir}/libGLX_mesa.so.0* +%{_libdir}/libGLX_system.so.0* +%files libGL-devel +%dir %{_includedir}/GL +%dir %{_includedir}/GL/internal +%{_includedir}/GL/internal/dri_interface.h +%{_libdir}/pkgconfig/dri.pc +%{_libdir}/libglapi.so + +%files libEGL +%{_datadir}/glvnd/egl_vendor.d/50_mesa.json +%{_libdir}/libEGL_mesa.so.0* +%files libEGL-devel +%dir %{_includedir}/EGL +%{_includedir}/EGL/eglext_angle.h +%{_includedir}/EGL/eglmesaext.h + +%files libglapi +%{_libdir}/libglapi.so.0 +%{_libdir}/libglapi.so.0.* + +%files libOSMesa +%{_libdir}/libOSMesa.so.8* +%files libOSMesa-devel +%dir %{_includedir}/GL +%{_includedir}/GL/osmesa.h +%{_libdir}/libOSMesa.so +%{_libdir}/pkgconfig/osmesa.pc + +%files libgbm +%{_libdir}/libgbm.so.1 +%{_libdir}/libgbm.so.1.* +%files libgbm-devel +%{_libdir}/libgbm.so +%{_includedir}/gbm.h +%{_libdir}/pkgconfig/gbm.pc + +%if 0%{?with_xa} +%files libxatracker +%if 0%{?with_hardware} +%{_libdir}/libxatracker.so.2 +%{_libdir}/libxatracker.so.2.* +%endif + +%files libxatracker-devel +%if 0%{?with_hardware} +%{_libdir}/libxatracker.so +%{_includedir}/xa_tracker.h +%{_includedir}/xa_composite.h +%{_includedir}/xa_context.h +%{_libdir}/pkgconfig/xatracker.pc +%endif +%endif + +%if 0%{?with_teflon} +%files libTeflon +%{_libdir}/libteflon.so +%endif + +%if 0%{?with_opencl} +%files libOpenCL +%{_libdir}/libMesaOpenCL.so.* +%{_libdir}/libRusticlOpenCL.so.* +%{_sysconfdir}/OpenCL/vendors/mesa.icd +%{_sysconfdir}/OpenCL/vendors/rusticl.icd + +%files libOpenCL-devel +%{_libdir}/libMesaOpenCL.so +%{_libdir}/libRusticlOpenCL.so +%endif + +%if 0%{?with_nine} +%files libd3d +%dir %{_libdir}/d3d/ +%{_libdir}/d3d/*.so.* + +%files libd3d-devel +%{_libdir}/pkgconfig/d3d.pc +%{_includedir}/d3dadapter/ +%{_libdir}/d3d/*.so +%endif + +%files dri-drivers +%{_datadir}/drirc.d/00-mesa-defaults.conf +%{_libdir}/libgallium-*.so +%{_libdir}/dri/kms_swrast_dri.so +%{_libdir}/dri/libdril_dri.so +%{_libdir}/dri/swrast_dri.so +%{_libdir}/dri/virtio_gpu_dri.so + +%if 0%{?with_hardware} +%if 0%{?with_r300} +%{_libdir}/dri/r300_dri.so +%endif +%if 0%{?with_radeonsi} +%if 0%{?with_r600} +%{_libdir}/dri/r600_dri.so +%endif +%{_libdir}/dri/radeonsi_dri.so +%endif +%ifarch %{ix86} x86_64 +%{_libdir}/dri/crocus_dri.so +%{_libdir}/dri/iris_dri.so +%endif +%ifarch aarch64 x86_64 %{ix86} +%{_libdir}/dri/ingenic-drm_dri.so +%{_libdir}/dri/imx-drm_dri.so +%{_libdir}/dri/imx-lcdif_dri.so +%{_libdir}/dri/kirin_dri.so +%{_libdir}/dri/komeda_dri.so +%{_libdir}/dri/mali-dp_dri.so +%{_libdir}/dri/mcde_dri.so +%{_libdir}/dri/mxsfb-drm_dri.so +%{_libdir}/dri/rcar-du_dri.so +%{_libdir}/dri/stm_dri.so +%endif +%if 0%{?with_vc4} +%{_libdir}/dri/vc4_dri.so +%endif +%if 0%{?with_v3d} +%{_libdir}/dri/v3d_dri.so +%endif +%if 0%{?with_freedreno} +%{_libdir}/dri/kgsl_dri.so +%{_libdir}/dri/msm_dri.so +%endif +%if 0%{?with_etnaviv} +%{_libdir}/dri/etnaviv_dri.so +%endif +%if 0%{?with_tegra} +%{_libdir}/dri/tegra_dri.so +%endif +%if 0%{?with_lima} +%{_libdir}/dri/lima_dri.so +%endif +%if 0%{?with_panfrost} +%{_libdir}/dri/panfrost_dri.so +%{_libdir}/dri/panthor_dri.so +%endif +%{_libdir}/dri/nouveau_dri.so +%if 0%{?with_vmware} +%{_libdir}/dri/vmwgfx_dri.so +%endif +%endif +%if 0%{?with_opencl} +%dir %{_libdir}/gallium-pipe +%{_libdir}/gallium-pipe/*.so +%endif +%if 0%{?with_kmsro} +%{_libdir}/dri/armada-drm_dri.so +%{_libdir}/dri/exynos_dri.so +%{_libdir}/dri/gm12u320_dri.so +%{_libdir}/dri/hdlcd_dri.so +%{_libdir}/dri/hx8357d_dri.so +%{_libdir}/dri/ili9163_dri.so +%{_libdir}/dri/ili9225_dri.so +%{_libdir}/dri/ili9341_dri.so +%{_libdir}/dri/ili9486_dri.so +%{_libdir}/dri/imx-dcss_dri.so +%{_libdir}/dri/mediatek_dri.so +%{_libdir}/dri/meson_dri.so +%{_libdir}/dri/mi0283qt_dri.so +%{_libdir}/dri/panel-mipi-dbi_dri.so +%{_libdir}/dri/pl111_dri.so +%{_libdir}/dri/repaper_dri.so +%{_libdir}/dri/rockchip_dri.so +%{_libdir}/dri/rzg2l-du_dri.so +%{_libdir}/dri/ssd130x_dri.so +%{_libdir}/dri/st7586_dri.so +%{_libdir}/dri/st7735r_dri.so +%{_libdir}/dri/sti_dri.so +%{_libdir}/dri/sun4i-drm_dri.so +%{_libdir}/dri/udl_dri.so +%{_libdir}/dri/vkms_dri.so +%{_libdir}/dri/zynqmp-dpsub_dri.so +%endif +%if 0%{?with_vulkan_hw} +%{_libdir}/dri/zink_dri.so +%endif + +%if 0%{?with_va} +%files va-drivers +%{_libdir}/dri/nouveau_drv_video.so +%if 0%{?with_r600} +%{_libdir}/dri/r600_drv_video.so +%endif +%if 0%{?with_radeonsi} +%{_libdir}/dri/radeonsi_drv_video.so +%endif +%{_libdir}/dri/virtio_gpu_drv_video.so +%endif + +%if 0%{?with_vdpau} +%files vdpau-drivers +%dir %{_libdir}/vdpau +%{_libdir}/vdpau/libvdpau_nouveau.so.1* +%if 0%{?with_r600} +%{_libdir}/vdpau/libvdpau_r600.so.1* +%endif +%if 0%{?with_radeonsi} +%{_libdir}/vdpau/libvdpau_radeonsi.so.1* +%endif +%{_libdir}/vdpau/libvdpau_virtio_gpu.so.1* +%endif + +%files vulkan-drivers +%{_libdir}/libvulkan_lvp.so +%{_datadir}/vulkan/icd.d/lvp_icd.*.json +%{_libdir}/libVkLayer_MESA_device_select.so +%{_datadir}/vulkan/implicit_layer.d/VkLayer_MESA_device_select.json +%if 0%{?with_vulkan_hw} +%{_libdir}/libvulkan_radeon.so +%{_datadir}/drirc.d/00-radv-defaults.conf +%{_datadir}/vulkan/icd.d/radeon_icd.*.json +%if 0%{?with_nvk} +%{_libdir}/libvulkan_nouveau.so +%{_datadir}/vulkan/icd.d/nouveau_icd.*.json +%endif +%ifarch %{ix86} x86_64 +%{_libdir}/libvulkan_intel.so +%{_datadir}/vulkan/icd.d/intel_icd.*.json +%{_libdir}/libvulkan_intel_hasvk.so +%{_datadir}/vulkan/icd.d/intel_hasvk_icd.*.json +%endif +%ifarch aarch64 x86_64 %{ix86} +%{_libdir}/libvulkan_broadcom.so +%{_datadir}/vulkan/icd.d/broadcom_icd.*.json +%{_libdir}/libvulkan_freedreno.so +%{_datadir}/vulkan/icd.d/freedreno_icd.*.json +%{_libdir}/libvulkan_panfrost.so +%{_datadir}/vulkan/icd.d/panfrost_icd.*.json +%{_libdir}/libpowervr_rogue.so +%{_libdir}/libvulkan_powervr_mesa.so +%{_datadir}/vulkan/icd.d/powervr_mesa_icd.*.json +%endif +%endif + +%changelog +## START: Generated by rpmautospec +* Wed Feb 26 2025 José Expósito - 24.2.8-2 +- AMD Navi4x support + +* Thu Nov 28 2024 José Expósito - 24.2.8-1 +- Update to 24.2.8 + +* Wed Nov 13 2024 José Expósito - 24.2.6-2 +- Don't build python3-pyyaml + +* Tue Nov 12 2024 José Expósito - 24.2.6-1 +- Update to 24.2.6 + +* Tue Oct 29 2024 Troy Dawson - 24.1.2-2 +- Bump release for October 2024 mass rebuild: + +* Fri Jun 28 2024 José Expósito - 24.1.2-1 +- Update to 24.1.2 + +* Mon Jun 24 2024 Troy Dawson - 24.1.0-3 +- Bump release for June 2024 mass rebuild + +* Fri Jun 21 2024 Ray Strode - 24.1.0-2 +- Fix egl on s390x + +* Wed Jun 05 2024 José Expósito - 24.1.0-1 +- Update to 24.1.0 + +* Mon May 27 2024 Tomas Pelka - 24.0.0-3 +- Add gating.yaml via API + +* Fri Feb 09 2024 Neal Gompa - 24.0.0-2 +- Add a modprobe config file to enable GSP on Turing and Ampere with NVK + +* Thu Feb 01 2024 José Expósito - 24.0.0-1 +- Update to 24.0.0 + +* Wed Jan 31 2024 Yaakov Selkowitz - 24.0.0~rc2-7 +- Disable NVK for now in ELN builds + +* Wed Jan 31 2024 José Expósito - 24.0.0~rc2-6 +- Revert "Enable LTO" + +* Fri Jan 26 2024 José Expósito - 24.0.0~rc2-5 +- Enable LTO + +* Thu Jan 25 2024 Neal Gompa - 24.0.0~rc2-4 +- Enable NVK to support the new Nouveau driver in Linux 6.7+ + +* Thu Jan 25 2024 Fedora Release Engineering - 24.0.0~rc2-3 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_40_Mass_Rebuild + +* Fri Jan 19 2024 Javier Martinez Canillas - 24.0.0~rc2-2 +- Fix build due a clang bug on nested macros + +* Fri Jan 19 2024 Javier Martinez Canillas - 24.0.0~rc2-1 +- Update to 24.0.0-rc2 + +* Tue Jan 16 2024 Javier Martinez Canillas - 24.0.0~rc1-1 +- Update to 24.0.0-rc1 + +* Thu Jan 11 2024 José Expósito - 23.3.3-1 +- Update to 23.3.0 + +* Wed Jan 10 2024 Alessandro Astone - 23.3.2-9 +- Fix zink crash and re-enable the automatic fallback + +* Mon Jan 08 2024 Florian Weimer - 23.3.2-8 +- Fix C compatibility issue in Meson probe + +* Mon Jan 08 2024 José Expósito - 23.3.2-7 +- fix compiler backport + +* Mon Jan 08 2024 José Expósito - 23.3.2-6 +- Update patch "intel/compiler: reemit boolean resolve for inverted if on + gen5" + +* Wed Jan 03 2024 Alessandro Astone - 23.3.2-5 +- Disable zink fallback in EGL + +* Wed Jan 03 2024 Dave Airlie - 23.3.2-4 +- fix compiler backport more + +* Wed Jan 03 2024 Dave Airlie - 23.3.2-3 +- fix intel compiler change for 23.3 + +* Wed Jan 03 2024 Dave Airlie - 23.3.2-2 +- add fix for intel compiler unused variable in release builds + +* Wed Jan 03 2024 Dave Airlie - 23.3.2-1 +- Update to 23.3.2 and better fix for gen5 intel. + +* Thu Dec 21 2023 Dave Airlie - 23.3.1-4 +- Fix gtk4-demo regression on older Intel + +* Mon Dec 18 2023 Dave Airlie - 23.3.1-3 +- fix a crocus regression in intel compiler for gtk4/gnome-shell + +* Mon Dec 18 2023 Dave Airlie - 23.3.1-2 +- drop zink patch + +* Mon Dec 18 2023 Dave Airlie - 23.3.1-1 +- Update to 23.3.1 + +* Thu Nov 30 2023 José Expósito - 23.3.0-1 +- Update to 23.3.0 + +* Wed Nov 29 2023 José Expósito - 23.3.0~rc5-1 +- Update to 23.3.0-rc5 + +* Thu Nov 23 2023 José Expósito - 23.3.0~rc2-6 +- Set glx-read-only-text on i386 + +* Thu Nov 23 2023 José Expósito - 23.3.0~rc2-5 +- Disable rwx segment linker error + +* Wed Nov 22 2023 José Expósito - 23.3.0~rc2-4 +- Backport MR #26332 to fix X11 session on VMs + +* Fri Nov 17 2023 José Expósito - 23.3.0~rc2-3 +- Backport MR #26220 to fix GNOME apps crash + +* Fri Nov 03 2023 José Expósito - 23.3.0~rc2-2 +- Backport MR #26029 to fix installer crash + +* Thu Nov 02 2023 José Expósito - 23.3.0~rc2-1 +- Update to 23.3.0-rc2 + +* Thu Oct 26 2023 José Expósito - 23.3.0~rc1-1 +- Update to 23.3.0-rc1 + +* Thu Oct 05 2023 Adam Williamson - 23.2.1-2 +- Backport MR #24045 to fix Iris crashes (#2238711) + +* Fri Sep 29 2023 Pete Walter - 23.2.1-1 +- Update to 23.2.1 + +* Fri Sep 15 2023 Dave Airlie - 23.2.0~rc3-3 +- update SPDX license + +* Thu Sep 07 2023 Adam Jackson - 23.2.0~rc3-2 +- Build a few more drivers for RHEL + +* Wed Sep 06 2023 Pete Walter - 23.2.0~rc3-1 +- Update to 23.2.0-rc3 + +* Tue Aug 22 2023 Neal Gompa - 23.2.0~rc2-4 +- Enable GLESv1 support + +* Mon Aug 14 2023 Neal Gompa - 23.2.0~rc2-3 +- Enable all aarch64 drivers for x86 for x86 emulation on aarch64 + +* Sat Aug 12 2023 Neal Gompa - 23.2.0~rc2-2 +- Bump Meson minimum build dependency to 1.2.0 + +* Thu Aug 10 2023 Pete Walter - 23.2.0~rc2-1 +- Update to 23.2.0-rc2 + +* Thu Aug 03 2023 Pete Walter - 23.1.5-1 +- Update to 23.1.5 + +* Sat Jul 22 2023 Pete Walter - 23.1.4-1 +- Update to 23.1.4 + +* Thu Jul 20 2023 Fedora Release Engineering - 23.1.3-4 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_39_Mass_Rebuild + +* Sun Jul 16 2023 Yaakov Selkowitz - 23.1.3-3 +- Disable libunwind, lm_sensors in RHEL builds + +* Thu Jul 13 2023 Kamil Páral - 23.1.3-2 +- Prevent partial updates (rhbz#2193135) + +* Fri Jun 30 2023 Nicolas Chauvet - 23.1.3-1 +- Update to 23.1.3 + +* Sun Jun 11 2023 Pete Walter - 23.1.2-1 +- Update to 23.1.2 + +* Wed Jun 07 2023 Neal Gompa - 23.1.1-2 +- Enable stack trace and HUD sensor support + +* Thu May 25 2023 Dave Airlie - 23.1.1-1 +- update to 23.1.1 + +* Tue May 23 2023 Dave Airlie - 23.1.0-3 +- removed unused BR + +* Tue May 23 2023 Dave Airlie - 23.1.0-2 +- Update to mesa 23.1.0 + +* Tue May 23 2023 Dave Airlie - 23.1.0-1 +- Update to mesa 23.1.0 + +* Wed May 03 2023 Michel Dänzer - 23.0.3-4 +- Do not enable intel-clc for ELN/RHEL + +* Mon May 01 2023 Michel Dänzer - 23.0.3-3 +- Enable intel-clc for ANV ray tracing support + +* Fri Apr 28 2023 Michel Dänzer - 23.0.3-2 +- Remove superfluous meson parameters for rusticl +- Dllvm=enabled is already there unconditionally further down. + +* Tue Apr 25 2023 Pete Walter - 23.0.3-1 +- Update to 23.0.3 + +* Tue Apr 25 2023 Pete Walter - 23.0.2-3 +- Add missing inter-subpackage requires (rhbz#2187726) + +* Tue Apr 18 2023 Nicolas Chauvet - 23.0.2-2 +- Revert "Tighten mesa-va-drivers recommends again (rhbz#2161338)" + +* Thu Apr 13 2023 Pete Walter - 23.0.2-1 +- Update to 23.0.2 + +* Thu Apr 13 2023 Pete Walter - 23.0.1-3 +- Tighten mesa-va-drivers recommends again (rhbz#2161338) + +* Mon Apr 03 2023 František Zatloukal - 23.0.1-2 +- Rebuild for LLVM 16 + +* Sat Mar 25 2023 Pete Walter - 23.0.1-1 +- Update to 23.0.1 + +* Thu Feb 23 2023 Pete Walter - 23.0.0-1 +- Update to 23.0.0 + +* Wed Feb 15 2023 Adam Williamson - 23.0.0~rc4-3 +- Backport MR #21333 to fix KDE on llvmpipe (#2164667) + +* Sun Feb 05 2023 Fabio Valentini - 23.0.0~rc4-2 +- Ensure standard Rust compiler flags are set + +* Wed Feb 01 2023 Pete Walter - 23.0.0~rc4-1 +- Update to 23.0.0-rc4 + +* Thu Jan 26 2023 Adam Williamson - 23.0.0~rc3-3 +- Backport MR #20933 to fix double-free crash (rhbz#2164667) + +* Wed Jan 25 2023 Pete Walter - 23.0.0~rc3-2 +- Fix the build (rhbz#2161370) + +* Wed Jan 25 2023 Pete Walter - 23.0.0~rc3-1 +- Update to 23.0.0-rc3 + +* Wed Jan 25 2023 Pete Walter - 22.3.3-3 +- Use unversioned recommends for mesa-va-drivers (rhbz#2161338) + +* Thu Jan 19 2023 Fedora Release Engineering - 22.3.3-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_38_Mass_Rebuild + +* Wed Jan 11 2023 Pete Walter - 22.3.3-1 +- Update to 22.3.3 + +* Sat Dec 31 2022 Pete Walter - 22.3.2-1 +- Update to 22.3.2 + +* Sun Dec 18 2022 Pete Walter - 22.3.1-1 +- Update to 22.3.1 + +* Tue Dec 06 2022 Dave Airlie - 22.3.0-2 +- fix regression around mit-shm detection + +* Wed Nov 30 2022 Pete Walter - 22.3.0-1 +- Update to 22.3.0 + +* Fri Nov 25 2022 Dave Airlie - 22.3.0~rc4-2 +- disable glthread for gnome-shell + +* Thu Nov 24 2022 Pete Walter - 22.3.0~rc4-1 +- Update to 22.3.0-rc4 + +* Tue Nov 22 2022 Dave Airlie - 22.3.0~rc3-4 +- add hasvk files + +* Tue Nov 22 2022 Dave Airlie - 22.3.0~rc3-3 +- enable hasvk + regression fix + +* Mon Nov 21 2022 Pete Walter - 22.3.0~rc3-2 +- Sort new files + +* Mon Nov 21 2022 Dave Airlie - 22.3.0~rc3-1 +- rebase to 22.3.0-rc3 + +* Thu Nov 17 2022 Peter Robinson - 22.3.0~rc2-3 +- Enable rusticl as an optional OpenCL engine + +* Thu Nov 10 2022 Dave Airlie - 22.3.0~rc2-2 +- Add patch files + +* Thu Nov 10 2022 Dave Airlie - 22.3.0~rc2-1 +- Update to 22.3.0-rc2 + +* Mon Nov 07 2022 Pete Walter - 22.2.3-1 +- Update to 22.2.3 + +* Wed Oct 19 2022 Pete Walter - 22.2.2-1 +- Update to 22.2.2 + +* Wed Oct 12 2022 Pete Walter - 22.2.1-1 +- Update to 22.2.1 + +* Mon Oct 10 2022 Ray Strode - 22.2.0-7 +- Recommend mesa-va-drivers from mesa-dri-drivers + +* Sun Oct 02 2022 Pete Walter - 22.2.0-6 +- Remove old obsoletes + +* Sun Oct 02 2022 Pete Walter - 22.2.0-5 +- Rename mesa-vaapi-drivers to mesa-va-drivers + +* Wed Sep 28 2022 Dave Airlie - 22.2.0-4 +- mesa: split out vaapi drivers into separate package + +* Sun Sep 25 2022 Pete Walter - 22.2.0-3 +- Recommend mesa-dri-drivers from libGL, libEGL, and libgbm subpackages + (rhbz#1900633) + +* Thu Sep 22 2022 Karol Herbst - 22.2.0-2 +- Add Nouveau multithreading fix backport (rhbz#2123274) + +* Wed Sep 21 2022 Pete Walter - 22.2.0-1 +- Update to 22.2.0 + +* Tue Sep 20 2022 Dave Airlie - 22.2.0~rc3-4 +- Drop codecs. + +* Sat Sep 17 2022 Pete Walter - 22.2.0~rc3-3 +- Rebuild for llvm 15 + +* Mon Sep 12 2022 Pete Walter - 22.2.0~rc3-2 +- Re-enable video codecs (rhbz#2123998) + +* Thu Aug 18 2022 Pete Walter - 22.2.0~rc3-1 +- Update to 22.2.0-rc3 + +* Fri Aug 12 2022 Pete Walter - 22.2.0~rc2-1 +- Update to 22.2.0-rc2 + +* Fri Aug 12 2022 Pete Walter - 22.1.6-2 +- Drop obsolete arm ifarch conditionals + +* Thu Aug 11 2022 Pete Walter - 22.1.6-1 +- Update to 22.1.6 + +* Thu Aug 04 2022 Dave Airlie - 22.1.5-2 +- add two llvmpipe fixes for multi-context + +* Thu Aug 04 2022 Pete Walter - 22.1.5-1 +- Update to 22.1.5 + +* Thu Jul 21 2022 Pete Walter - 22.1.4-2 +- Enable vmware svga driver on aarch64 (#2108405) + +* Wed Jul 20 2022 Pete Walter - 22.1.4-1 +- Update to 22.1.4 + +* Thu Jul 14 2022 Pete Walter - 22.1.3-3 +- Build i915 gallium driver (#2100212) + +* Thu Jul 14 2022 Dave Airlie - 22.1.3-2 +- attempt to fix race in kms_swrast_dri.so affecting kwin. + +* Sat Jul 02 2022 Pete Walter - 22.1.3-1 +- Update to 22.1.3 + +* Thu Jun 16 2022 Pete Walter - 22.1.2-1 +- Update to 22.1.2 + +* Thu Jun 02 2022 Pete Walter - 22.1.1-1 +- Update to 22.1.1 + +* Thu Jun 02 2022 Pete Walter - 22.1.0-5 +- Update Source0 + +* Thu May 26 2022 Dave Airlie - 22.1.0-4 +- fix spec file chunk + +* Thu May 26 2022 Dave Airlie - 22.1.0-3 +- backport correct llvmpipe artifact fix + +* Wed May 25 2022 Dave Airlie - 22.1.0-2 +- revert llvmpipe overlap patch to see if it fixes rawhide + +* Thu May 19 2022 Pete Walter - 22.1.0-1 +- Update to 22.1.0 + +* Thu May 05 2022 Pete Walter - 22.0.3-1 +- Update to 22.0.3 + +* Mon Apr 25 2022 Pete Walter - 22.0.2-2 +- Add new 00-radv-defaults.conf to files list + +* Sun Apr 24 2022 Pete Walter - 22.0.2-1 +- Update to 22.0.2 + +* Wed Mar 30 2022 Pete Walter - 22.0.1-1 +- Update to 22.0.1 + +* Mon Mar 21 2022 Pete Walter - 22.0.0-4 +- Obsolete empty mesa-vulkan-devel subpackage + +* Mon Mar 21 2022 Pete Walter - 22.0.0-3 +- Fix the build + +* Thu Mar 10 2022 Dave Airlie - 22.0.0-2 +- fixup unknown args + +* Thu Mar 10 2022 Dave Airlie - 22.0.0-1 +- update to 22.0.0 + +* Wed Feb 23 2022 Pete Walter - 21.3.7-1 +- Update to 21.3.7 + +* Thu Feb 10 2022 Pete Walter - 21.3.6-1 +- Update to 21.3.6 + +* Mon Jan 31 2022 Lyude Paul - 21.3.5-2 +- Add missing attributions for 21.3.4-3 + +* Sat Jan 29 2022 Pete Walter - 21.3.5-1 +- Update to 21.3.5 + +* Fri Jan 21 2022 Lyude Paul - 21.3.4-3 +- Add patch from upstream to fix blinking with Intel Iris (#2040771) + (#2036600) + +* Thu Jan 20 2022 Fedora Release Engineering - 21.3.4-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_36_Mass_Rebuild + +* Fri Jan 14 2022 Pete Walter - 21.3.4-1 +- Update to 21.3.4 + +* Thu Dec 30 2021 Pete Walter - 21.3.3-1 +- Update to 21.3.3 + +* Sat Dec 18 2021 Pete Walter - 21.3.2-1 +- Update to 21.3.2 + +* Mon Dec 06 2021 Pete Walter - 21.3.1-2 +- Patch from upstream to make GBM work again with NVIDIA 495 (#2028524) + +* Wed Dec 01 2021 Pete Walter - 21.3.1-1 +- Update to 21.3.1 + +* Thu Nov 18 2021 Pete Walter - 21.3.0-2 +- Fix files list + +* Wed Nov 17 2021 Pete Walter - 21.3.0-1 +- Update to 21.3.0 + +* Tue Nov 09 2021 Tom Stellard - 21.2.5-2 +- Rebuild for llvm-13.0.0 + +* Thu Oct 28 2021 Pete Walter - 21.2.5-1 +- Update to 21.2.5 + +* Thu Oct 28 2021 Stephen Gallagher - 21.2.4-3 +- Rebuild for llvm 13 soname change + +* Thu Oct 14 2021 Tom Stellard - 21.2.4-2 +- Rebuild for llvm-13.0.0 + +* Thu Oct 14 2021 Pete Walter - 21.2.4-1 +- Update to 21.2.4 + +* Wed Oct 13 2021 Tom Stellard - 21.2.3-7 +- Rebuild for llvm-13.0.0 + +* Tue Oct 12 2021 Adam Williamson - 21.2.3-6 +- Add patches from previous commit to git + +* Tue Oct 12 2021 Adam Williamson - 21.2.3-5 +- Backport MR#13231 and revert MR#3724 to fix Tegra (kherbst) + +* Tue Oct 12 2021 Tom Stellard - 21.2.3-4 +- Rebuild for llvm-13.0.0 + +* Mon Oct 11 2021 Dave Airlie - 21.2.3-3 +- mesa: backport another crocus fix + +* Mon Oct 11 2021 Dave Airlie - 21.2.3-2 +- mesa: backport some crocus fixes + +* Wed Sep 29 2021 Pete Walter - 21.2.3-1 +- Update to 21.2.3 + +* Tue Sep 21 2021 Pete Walter - 21.2.2-1 +- Update to 21.2.2 + +* Mon Sep 13 2021 Dave Airlie - 21.2.1-4 +- mesa: add fixes from 21.2 staging branch and enable crocus by default + +* Sat Aug 21 2021 Pete Walter - 21.2.1-3 +- Fix the build + +* Fri Aug 20 2021 Peter Robinson - 21.2.1-2 +- Enable panfrost vulcan driver on arm + +* Thu Aug 19 2021 Pete Walter - 21.2.1-1 +- Update to 21.2.1 + +* Thu Aug 19 2021 Pete Walter - 21.2.0-4 +- Opt in to rpmautospec + +* Thu Aug 19 2021 Stephen Gallagher - 21.2.0-3 +- Fixes for building against LLVM 13 + +* Thu Aug 05 2021 ValdikSS - 21.2.0-2 +- Enable Crocus driver + +* Thu Aug 05 2021 Pete Walter - 21.2.0-1 +- Update to 21.2.0 + +* Sat Jul 31 2021 Pete Walter - 21.1.6-1 +- Update to 21.1.6 + +* Thu Jul 22 2021 Fedora Release Engineering - 21.1.5-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_35_Mass_Rebuild + +* Sat Jul 17 2021 Pete Walter - 21.1.5-1 +- Update to 21.1.5 + +* Sat Jul 03 2021 Pete Walter - 21.1.4-1 +- Update to 21.1.4 + +* Fri Jun 18 2021 Pete Walter - 21.1.3-1 +- Update to 21.1.3 + +* Sat Jun 12 2021 Pete Walter - 21.1.2-1 +- Update to 21.1.2 + +* Thu May 27 2021 Pete Walter - 21.1.1-3 +- Clean up %%ldconfig_scriptlets macros + +* Wed May 26 2021 Tom Stellard - 21.1.1-2 +- Rebuild for LLVM 12.0.0-final + +* Wed May 19 2021 Pete Walter - 21.1.1-1 +- Update to 21.1.1 + +* Wed May 05 2021 Adam Jackson - 21.1.0-1 +- Update to 21.1.0 + +* Thu Apr 29 2021 Kalev Lember - 21.0.3-2 +- Backport a fix for amdgpu graphics corruption regression + +* Thu Apr 22 2021 Pete Walter - 21.0.3-1 +- Update to 21.0.3 + +* Mon Apr 19 2021 Dave Airlie - 21.0.2-2 +- mesa: move imx-drm to correct place in file. + +* Wed Apr 07 2021 Pete Walter - 21.0.2-1 +- Update to 21.0.2 + +* Thu Apr 01 2021 Dave Airlie - 21.0.1-6 +- Backport CPU caps fixes + +* Fri Mar 26 2021 Adam Jackson - 21.0.1-4 +- Split out with_r300 and with_r600 Disable r300, r600, etnaviv, lima, vc4 + and v3d in RHEL + +* Thu Mar 25 2021 Dave Airlie - 21.0.1-3 +- add missing patch + +* Thu Mar 25 2021 Dave Airlie - 21.0.1-2 +- fix zink loading in places it shouldn't. + +* Wed Mar 24 2021 Pete Walter - 21.0.1-1 +- Update to 21.0.1 + +* Tue Mar 23 2021 Pete Walter - 21.0.0-2 +- Rebuild for llvm 12 + +* Fri Mar 12 2021 Pete Walter - 21.0.0-1 +- Update to 21.0.0 + +* Mon Mar 08 2021 Adam Williamson - 21.0.0~rc5-3 +- Backport MR #9425 to fix GNOME Shell crash on Jetson Nano (#1930977) + +* Mon Feb 22 2021 Dave Airlie - 21.0.0~rc5-2 +- fix sddm/vmware regression + +* Fri Feb 19 2021 Pete Walter - 21.0.0~rc5-1 +- Update to 21.0.0-rc5 + +* Fri Feb 19 2021 Adam Jackson - 21.0.0~rc4-2 +- Disable OpenMAX, OpenCL, and nine in RHEL + +* Wed Feb 17 2021 Pete Walter - 21.0.0~rc4-1 +- Update to 21.0.0-rc4 + +* Wed Feb 03 2021 Dave Airlie - 21.0.0~rc3-2 +- Fix zink/swrast/lavapipe/gnome-shell interaction (#1924360) + +* Fri Jan 29 2021 Pete Walter - 21.0.0~rc3-1 +- Update to 21.0.0-rc3 + +* Fri Jan 29 2021 Dave Airlie - 20.3.3-7 +- Backport upstream fix for EGL issues with qemu + +* Tue Jan 26 2021 Fedora Release Engineering - 20.3.3-6 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_34_Mass_Rebuild + +* Fri Jan 22 2021 Tom Stellard - 20.3.3-5 +- Rebuild for clang-11.1.0 + +* Wed Jan 20 2021 Adam Jackson - 20.3.3-4 +- Disable classic drivers in RHEL + +* Fri Jan 15 2021 Dave Airlie - 20.3.3-3 +- Fix lavapipe missing ext that breaks gstreamer/pidgin + +* Thu Jan 14 2021 Dave Airlie - 20.3.3-2 +- Fix device selection layer for vulkan 1.2 + +* Wed Jan 13 2021 Pete Walter - 20.3.3-1 +- Update to 20.3.3 + +* Thu Dec 31 2020 Pete Walter - 20.3.2-1 +- Update to 20.3.2 + +* Wed Dec 16 2020 Pete Walter - 20.3.1-2 +- Fix pre-release versions in old %%changelog entries + +* Wed Dec 16 2020 Pete Walter - 20.3.1-1 +- Update to 20.3.1 + +* Mon Dec 07 2020 Dave Airlie - 20.3.0-2 +- Fix regression with radeon si/cik cards + +* Fri Dec 04 2020 Dave Airlie - 20.3.0-1 +- Update to 20.3.0 release + +* Tue Dec 01 2020 Peter Robinson - 20.3.0~rc3-2 +- Enable Zink opengl over vulkan driver, Broadcom v3dv and freedreno vulkan + drivers on arm + +* Mon Nov 30 2020 Dave Airlie - 20.3.0~rc3-1 +- Update to 20.3.0-rc3 + +* Mon Nov 30 2020 Dave Airlie - 20.3.0~rc2-1 +- Update to 20.3.0-rc2 + +* Sat Nov 28 2020 Peter Robinson - 20.2.3-3 +- Update meson options and nomenclature + +* Sat Nov 28 2020 Peter Robinson - 20.2.3-2 +- Cleanup vulkan conditionals, make it more inline with dri_drivers so it's + more straightforward as arches diverge supported drivers + +* Tue Nov 24 2020 Pete Walter - 20.2.3-1 +- Update to 20.2.3 + +* Sat Nov 07 2020 Pete Walter - 20.2.2-1 +- Update to 20.2.2 + +* Wed Oct 14 2020 Pete Walter - 20.2.1-1 +- Update to 20.2.1 + +* Tue Sep 29 2020 Pete Walter - 20.2.0-3 +- Update glvnd required version + +* Tue Sep 29 2020 Pete Walter - 20.2.0-2 +- Drop no longer needed big endian fix + +* Tue Sep 29 2020 Pete Walter - 20.2.0-1 +- Update to 20.2.0 + +* Fri Sep 25 2020 Adam Jackson - 20.2.0~rc4-3 +- mesa-libGL-devel Recommends: gl-manpages + +* Fri Sep 04 2020 Pete Walter - 20.2.0~rc4-2 +- Remove more no longer needed build hacks + +* Fri Sep 04 2020 Pete Walter - 20.2.0~rc4-1 +- Update to 20.2.0~rc4 + +* Thu Sep 03 2020 Pete Walter - 20.2.0~rc3-2 +- Remove -fcommon build workaround + +* Sat Aug 29 2020 Pete Walter - 20.2.0~rc3-1 +- Update to 20.2.0~rc3 + +* Sun Aug 23 2020 Pete Walter - 20.2.0~rc2-1 +- Update to 20.2.0~rc2 + +* Sat Aug 22 2020 Kalev Lember - 20.1.6-2 +- Disable LTO as it appears to break some games (#1862771) + +* Thu Aug 20 2020 Pete Walter - 20.1.6-1 +- Update to 20.1.6 + +* Thu Aug 06 2020 Pete Walter - 20.1.5-1 +- Update to 20.1.5 + +* Tue Jul 28 2020 Fedora Release Engineering - 20.1.4-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_33_Mass_Rebuild + +* Thu Jul 23 2020 Pete Walter - 20.1.4-1 +- Update to 20.1.4 + +* Wed Jul 22 2020 Lyude Paul - 20.1.3-2 +- Fix build dependencies on certain arches + +* Sat Jul 11 2020 Pete Walter - 20.1.3-1 +- Update to 20.1.3 + +* Thu Jun 25 2020 Pete Walter - 20.1.2-1 +- Update to 20.1.2 + +* Wed Jun 10 2020 Pete Walter - 20.1.1-2 +- Fix the build with Python 3.9 + +* Wed Jun 10 2020 Pete Walter - 20.1.1-1 +- Update to 20.1.1 + +* Thu May 28 2020 Dave Airlie - 20.1.0-1 +- Update to 20.1.0 + +* Thu May 21 2020 Dave Airlie - 20.1.0~rc4-1 +- Update to 20.1.0-rc4 + +* Thu May 14 2020 Pete Walter - 20.0.7-1 +- Update to 20.0.7 + +* Thu Apr 30 2020 Pete Walter - 20.0.6-1 +- Update to 20.0.6 + +* Thu Apr 23 2020 Pete Walter - 20.0.5-2 +- Drop upstreamed patch + +* Thu Apr 23 2020 Pete Walter - 20.0.5-1 +- Update to 20.0.5 + +* Fri Apr 03 2020 Dave Airlie - 20.0.4-1 +- Update to 20.0.4 (fix spirv regression) + +* Wed Apr 01 2020 Pete Walter - 20.0.3-1 +- Update to 20.0.3 + +* Thu Mar 19 2020 Pete Walter - 20.0.2-1 +- Update to 20.0.2 + +* Fri Mar 06 2020 Pete Walter - 20.0.1-1 +- Update to 20.0.1 + +* Wed Feb 26 2020 Kalev Lember - 20.0.0-2 +- Fix the build with llvm 10 + +* Thu Feb 20 2020 Pete Walter - 20.0.0-1 +- Update to 20.0.0 + +* Fri Feb 14 2020 Pete Walter - 20.0.0~rc3-1 +- Update to 20.0.0~rc3 + +* Sat Feb 08 2020 Pete Walter - 20.0.0~rc2-1 +- Update to 20.0.0~rc2 + +* Sun Feb 02 2020 Pete Walter - 20.0.0~rc1-2 +- Update files list for arm drivers + +* Sat Feb 01 2020 Pete Walter - 20.0.0~rc1-1 +- Update to 20.0.0~rc1 + +* Wed Jan 29 2020 Pete Walter - 19.3.3-1 +- Update to 19.3.3 + +* Thu Jan 23 2020 Tom Stellard - 19.3.2-3 +- Link against libclang-cpp.so https://fedoraproject.org/wiki/Changes/Stop- + Shipping-Individual-Component-Libraries-In-clang-lib-Package + +* Thu Jan 23 2020 Tom Stellard - 19.3.2-2 +- Build with -fcommon until upstream fixes omx build with gcc10 + +* Fri Jan 10 2020 Pete Walter - 19.3.2-1 +- Update to 19.3.2 + +* Wed Dec 18 2019 Pete Walter - 19.3.1-1 +- Update to 19.3.1 + +* Mon Dec 16 2019 Pete Walter - 19.3.0-1 +- Update to 19.3.0 + +* Thu Dec 05 2019 Pete Walter - 19.3.0~rc6-1 +- Update to 19.3.0~rc6 + +* Thu Nov 28 2019 Pete Walter - 19.3.0~rc5-1 +- Update to 19.3.0~rc5 + +* Sun Nov 24 2019 Pete Walter - 19.3.0~rc4-1 +- Update to 19.3.0~rc4 + +* Thu Nov 14 2019 Pete Walter - 19.3.0~rc3-1 +- Update to 19.3.0~rc3 + +* Tue Nov 12 2019 Pete Walter - 19.3.0~rc2-2 +- Fix the build on arm + +* Fri Nov 08 2019 Pete Walter - 19.3.0~rc2-1 +- Update to 19.3.0~rc2 + +* Thu Nov 07 2019 Pete Walter - 19.2.3-1 +- Update to 19.2.3 + +* Fri Oct 25 2019 Peter Robinson - 19.2.2-5 +- adjust mesa-khr-devel requires now provided by libglvnd + +* Fri Oct 25 2019 Peter Robinson - 19.2.2-4 +- Fix up and remove bits now in libglvnd + +* Fri Oct 25 2019 Peter Robinson - 19.2.2-3 +- rebuild against libglvnd 1.2 + +* Fri Oct 25 2019 Pete Walter - 19.2.2-2 +- Update files lists + +* Fri Oct 25 2019 Pete Walter - 19.2.2-1 +- Update to 19.2.2 + +* Thu Oct 10 2019 Peter Robinson - 19.2.1-1 +- 19.2.1 + +* Fri Oct 04 2019 Gwyn Ciesla - 19.2.0-2 +- Rebuild for new freeglut. + +* Wed Sep 25 2019 Pete Walter - 19.2.0-1 +- Update to 19.2.0 + +* Wed Sep 18 2019 Pete Walter - 19.2.0~rc4-1 +- Update to 19.2.0~rc4 + +* Tue Sep 17 2019 Adam Jackson - 19.2.0~rc3-2 +- Build iris too + +* Thu Sep 12 2019 Pete Walter - 19.2.0~rc3-1 +- Update to 19.2.0~rc3 + +* Thu Sep 05 2019 Pete Walter - 19.2.0~rc2-1 +- Update to 19.2.0~rc2 + +* Tue Aug 27 2019 Adam Jackson - 19.2.0~rc1-5 +- BuildRequire vulkan-headers not vulkan-devel to ease llvm updates + +* Thu Aug 22 2019 Peter Robinson - 19.2.0~rc1-4 +- Bring back egl.pc for now + +* Wed Aug 21 2019 Peter Robinson - 19.2.0~rc1-3 +- add mxsfb-drm_dri and stm_dri drivers for arm platforms + +* Wed Aug 21 2019 Peter Robinson - 19.2.0~rc1-2 +- pkgconfig/egl.pc no longer shipped + +* Wed Aug 21 2019 Peter Robinson - 19.2.0~rc1-1 +- 19.2.0~rc1 + +* Thu Aug 08 2019 Pete Walter - 19.1.4-1 +- Update to 19.1.4 + +* Wed Jul 24 2019 Pete Walter - 19.1.3-1 +- Update to 19.1.3 + +* Tue Jul 09 2019 Pete Walter - 19.1.2-1 +- Update to 19.1.2 + +* Wed Jun 26 2019 Pete Walter - 19.1.1-1 +- Update to 19.1.1 + +* Mon Jun 24 2019 Peter Robinson - 19.1.0-2 +- Enable v3d driver + +* Wed Jun 12 2019 Igor Gnatenko - 19.1.0-1 +- Update to 19.1.0 + +* Fri Jun 07 2019 Pete Walter - 19.1.0~rc5-1 +- Update to 19.1.0~rc5 + +* Thu May 30 2019 Pete Walter - 19.1.0~rc4-1 +- Update to 19.1.0~rc4 + +* Wed May 22 2019 Dave Airlie - 19.1.0~rc3-1 +- Update to 19.1.0-rc3 + +* Tue May 21 2019 Adam Jackson - 19.1.0~rc2-2 +- Delete unused patch + +* Tue May 14 2019 Dave Airlie - 19.1.0~rc2-1 +- Update to 19.1.0-rc2 + +* Tue May 14 2019 Dave Airlie - 19.1.0~rc1-8 +- Bring back glesv2.pc for now + +* Sat May 11 2019 Peter Robinson - 19.1.0~rc1-7 +- Enable panfrost + +* Thu May 09 2019 Adam Jackson - 19.1.0~rc1-6 +- Enable lima + +* Thu May 09 2019 Adam Jackson - 19.1.0~rc1-5 +- Add some more stuff to .gitignore + +* Wed May 08 2019 Dave Airlie - 19.1.0~rc1-4 +- add missing exynos driver + +* Wed May 08 2019 Dave Airlie - 19.1.0~rc1-3 +- fix missing kmsro + +* Wed May 08 2019 Dave Airlie - 19.1.0~rc1-2 +- add missing kmsro drivers + +* Wed May 08 2019 Dave Airlie - 19.1.0~rc1-1 +- Update to 19.1.0-rc1 + +* Thu Apr 25 2019 Pete Walter - 19.0.3-1 +- Update to 19.0.3 + +* Tue Apr 16 2019 Adam Williamson - 19.0.2-5 +- Rebuild with Meson fix for #1699099 + +* Mon Apr 15 2019 Pete Walter - 19.0.2-4 +- Remove unneeded chrpath build dep + +* Sun Apr 14 2019 Igor Gnatenko - 19.0.2-3 +- Remove unneeded sources + +* Thu Apr 11 2019 Adam Jackson - 19.0.2-2 +- Drop the mpeg1/2 sanitize hack Switch to upstream tarball since we no + longer need to do the above + +* Thu Apr 11 2019 Igor Gnatenko - 19.0.2-1 +- Update to 19.0.2 + +* Thu Apr 04 2019 Adam Jackson - 19.0.1-2 +- Nuke rpath from installed DRI drivers + +* Wed Mar 27 2019 Igor Gnatenko - 19.0.1-1 +- Update to 19.0.1 + +* Mon Mar 25 2019 Igor Gnatenko - 19.0.0-2 +- Rebuild with -Db_ndebug=true + +* Wed Mar 13 2019 Peter Robinson - 19.0.0-1 +- 19.0.0 + +* Thu Mar 07 2019 Pete Walter - 19.0.0~rc7-1 +- Update to 19.0.0~rc7 + +* Wed Feb 27 2019 Pete Walter - 19.0.0~rc6-1 +- Update to 19.0.0~rc6 + +* Wed Feb 20 2019 Peter Robinson - 19.0.0~rc5-1 +- 19.0.0~rc5 + +* Thu Feb 14 2019 Igor Gnatenko - 19.0.0~rc4-3 +- Update EGL patch + +* Thu Feb 14 2019 Igor Gnatenko - 19.0.0~rc4-2 +- relax dependency of xcb-randr + +* Thu Feb 14 2019 Igor Gnatenko - 19.0.0~rc4-1 +- Update to 19.0.0~rc4 + +* Tue Feb 12 2019 Igor Gnatenko - 19.0.0~rc2-4 +- Fix radv vulkan + +* Fri Feb 08 2019 Pete Walter - 19.0.0~rc2-3 +- Add back accidentally lost patch to disable rgb10 configs by default + (#1650929) + +* Wed Feb 06 2019 Peter Robinson - 19.0.0~rc2-2 +- update 19.0.0~rc2 + +* Wed Feb 06 2019 Peter Robinson - 19.0.0~rc2-1 +- 19.0.0~rc2 + +* Thu Jan 31 2019 Peter Robinson - 19.0.0~rc1-3 +- add kmsro build option, add work around for missing files in 'make dist' + (fixed upstream) + +* Thu Jan 31 2019 Igor Gnatenko - 19.0.0~rc1-2 +- Switch imx to kmsro + +* Thu Jan 31 2019 Igor Gnatenko - 19.0.0~rc1-1 +- Update to 19.0.0~rc1 + +* Thu Jan 17 2019 Adam Jackson - 18.3.2-1 +- Update to 18.3.2 + +* Wed Dec 19 2018 Igor Gnatenko - 18.3.1-3 +- Enable annotated build + +* Wed Dec 19 2018 Igor Gnatenko - 18.3.1-2 +- Switch to meson buildsystem + +* Tue Dec 18 2018 Igor Gnatenko - 18.3.1-1 +- commit spec changes + +* Tue Dec 18 2018 Igor Gnatenko - 18.3.0-2 +- Update to 18.3.1 + +* Fri Dec 07 2018 Igor Gnatenko - 18.3.0-1 +- Update to 18.3.0 + +* Fri Dec 07 2018 Igor Gnatenko - 18.3.0~rc5-3 +- Remove unused patches + +* Tue Dec 04 2018 Igor Gnatenko - 18.3.0~rc5-2 +- Backport patch to fix totem + +* Tue Dec 04 2018 Peter Robinson - 18.3.0~rc5-1 +- 18.3.0 rc5 + +* Tue Nov 27 2018 Igor Gnatenko - 18.3.0~rc4-1 +- Update to 18.3.0~rc4 + +* Thu Nov 15 2018 Adam Jackson - 18.3.0~rc2-2 +- Add mesa-khr-devel subpackage to hold , and make mesa- + lib{GL,GLES,EGL}-devel Require it. + +* Wed Nov 14 2018 Adam Jackson - 18.3.0~rc2-1 +- Update to 18.3.0 RC2 Re-enable 10bpc fbconfigs, clutter apps seem to work + now Drop now-unnecessary big-endian compilation fix + +* Tue Nov 06 2018 Igor Gnatenko - 18.2.4-3 +- Rebuild without workaround + +* Mon Nov 05 2018 Dave Airlie - 18.2.4-2 +- workaround bug with gcc 8.2.1-4 + +* Thu Nov 01 2018 Adam Jackson - 18.2.4-1 +- Update to 18.2.4 + +* Wed Oct 31 2018 Igor Gnatenko - 18.2.3-1 +- Update to 18.2.3 + +* Fri Oct 05 2018 Peter Robinson - 18.2.2-1 +- 18.2.2 + +* Fri Sep 21 2018 Peter Robinson - 18.2.1-1 +- 18.2.1 + +* Wed Sep 19 2018 Adam Williamson - 18.2.0-2 +- Fix "HW cursor for format" error message flood with swrast + +* Sat Sep 08 2018 Peter Robinson - 18.2.0-1 +- 18.2.0 + +* Sun Sep 02 2018 Hans de Goede - 18.2.0~rc5-1 +- Update to 18.2.0~rc5 + +* Wed Aug 22 2018 Igor Gnatenko - 18.2.0~rc3-2 +- Re-enable RadeonSI on ARM + +* Tue Aug 21 2018 Peter Robinson - 18.2.0~rc3-1 +- 18.2.0~rc3 + +* Sun Aug 19 2018 Igor Gnatenko - 18.2.0~rc2-4 +- correct files + +* Sun Aug 19 2018 Igor Gnatenko - 18.2.0~rc2-3 +- no radeon vulkan driver on arm + +* Sat Aug 11 2018 Igor Gnatenko - 18.2.0~rc2-2 +- BR: xrandr + +* Sat Aug 11 2018 Igor Gnatenko - 18.2.0~rc2-1 +- Update to 18.2.0~rc2 + +* Mon Jul 30 2018 Peter Robinson - 18.1.5-1 +- 18.1.5 + +* Mon Jul 23 2018 Dave Airlie - 18.1.4-3 +- bump glvnd requires + +* Mon Jul 23 2018 Dave Airlie - 18.1.4-2 +- fix fallback path for glvnd + +* Tue Jul 17 2018 Peter Robinson - 18.1.4-1 +- 18.1.4 + +* Fri Jul 13 2018 Fedora Release Engineering - 18.1.3-4 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_29_Mass_Rebuild + +* Fri Jul 06 2018 Adam Jackson - 18.1.3-3 +- Drop texture float patch + +* Sun Jul 01 2018 Igor Gnatenko - 18.1.3-2 +- Use simpler %%ldconfig macro + +* Sun Jul 01 2018 Peter Robinson - 18.1.3-1 +- 18.1.3 + +* Fri Jun 29 2018 Adam Jackson - 18.1.2-5 +- Use ldconfig scriptlet macros + +* Mon Jun 18 2018 Adam Jackson - 18.1.2-4 +- Create %%{_includedir}/vulkan unconditionally + +* Mon Jun 18 2018 Adam Jackson - 18.1.2-3 +- Careful, only configure vulkan drivers if hardware + +* Mon Jun 18 2018 Adam Jackson - 18.1.2-2 +- Build mesa-vulkan-drivers everywhere Build actual vulkan drivers on all + but s390x + +* Sat Jun 16 2018 Peter Robinson - 18.1.2-1 +- 18.1.2 + +* Fri Jun 15 2018 Adam Jackson - 18.1.1-9 +- Build tegra too + +* Thu Jun 14 2018 Adam Jackson - 18.1.1-8 +- libglvnd is epoched + +* Thu Jun 14 2018 Adam Jackson - 18.1.1-7 +- Change the name of the fallback GLX library + +* Wed Jun 06 2018 Adam Jackson - 18.1.1-6 +- this would all be easier if we just built amdgpu on arm32 + +* Wed Jun 06 2018 Adam Jackson - 18.1.1-5 +- ,,, + +* Tue Jun 05 2018 Adam Jackson - 18.1.1-4 +- hrgnarhgnhrn + +* Tue Jun 05 2018 Adam Jackson - 18.1.1-3 +- Stop mentioning ppc and s390, we don't build for them anymore Remove + with_llvm, now always true Switch with_radeonsi to be an exclude pattern, + apparently not available for armv7hl. + +* Tue Jun 05 2018 Adam Jackson - 18.1.1-2 +- Stop mentioning ppc and s390, we don't build for them anymore remove + with_llvm and with_radeonsi as they're now always true + +* Sun Jun 03 2018 Peter Robinson - 18.1.1-1 +- 18.1.1 + +* Thu May 24 2018 Peter Robinson - 18.1.0-4 +- 18.1.0 + +* Sat May 12 2018 Peter Robinson - 18.1.0-3 +- 18.1.0~rc4 + +* Sat May 05 2018 Peter Robinson - 18.1.0-2 +- 18.1 rc3 + +* Fri May 04 2018 Igor Gnatenko - 18.1.0-1 +- Update ot 18.1.0~rc2 + +* Tue May 01 2018 Peter Robinson - 18.0.2-2 +- RPMAUTOSPEC: unresolvable merge +## END: Generated by rpmautospec diff --git a/sources b/sources new file mode 100644 index 0000000..e9ebfb6 --- /dev/null +++ b/sources @@ -0,0 +1,3 @@ +SHA512 (libclc-19.1.1.src.tar.xz) = 41ba80e2ed8f874d79c40cfbb1de89ad9e1ecc3709519e697617c14bc2583b2f8cdb8ca20bd2095b436afcc69144a6d88d4334de1e152d78ef3a19ec14c0733d +SHA512 (mesa-24.2.8.tar.xz) = 3aa1051a72e1428e42f9537d8f6a26f2ebddc78894e0f71d2cdcc9ed555ea4d6489ad8e74d4c59b8cdf7ea1c629fa725ac2fe1e385db5d3a582d8fe8186392d6 +SHA512 (spirv-llvm-translator-90a9764.tar.gz) = c0be7326fa76927f9900a9d91ced0035aeee66cdab35baa9c708b27c5d5e423f4819f148d17c3b7b812d1e8991e1057d71d52c22df2de37efdd72f1c20dcf05e