99 lines
4.0 KiB
Diff
99 lines
4.0 KiB
Diff
From dbc6b9344bde269a2499d47e7f08c172a88f289a Mon Sep 17 00:00:00 2001
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From: pvanhout <pierre.vanhoutryve@amd.com>
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Date: Thu, 3 Aug 2023 10:53:08 +0200
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Subject: [PATCH] [DAG] Fix crash in replaceStoreOfInsertLoad
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Idx's type can be different from Ptr's, causing a "Binary operator types must match" assertion failure when emitting the MUL.
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Reviewed By: arsenm
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Differential Revision: https://reviews.llvm.org/D156972
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(cherry picked from commit 98ccc70b93a39a7ea3e26f7f5b5fe40d39b5a7e5)
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---
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llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +-
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.../AMDGPU/replace-store-of-insert-load.ll | 58 +++++++++++++++++++
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2 files changed, 59 insertions(+), 1 deletion(-)
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create mode 100644 llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll
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diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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index 235f0da86b90..dbc8be3c52b8 100644
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--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@@ -20517,7 +20517,7 @@ SDValue DAGCombiner::replaceStoreOfInsertLoad(StoreSDNode *ST) {
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EVT PtrVT = Ptr.getValueType();
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SDValue Offset =
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- DAG.getNode(ISD::MUL, DL, PtrVT, Idx,
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+ DAG.getNode(ISD::MUL, DL, PtrVT, DAG.getZExtOrTrunc(Idx, DL, PtrVT),
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DAG.getConstant(EltVT.getSizeInBits() / 8, DL, PtrVT));
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SDValue NewPtr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, Offset);
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MachinePointerInfo PointerInfo(ST->getAddressSpace());
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diff --git a/llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll b/llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll
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new file mode 100644
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index 000000000000..35a602af68c0
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--- /dev/null
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+++ b/llvm/test/CodeGen/AMDGPU/replace-store-of-insert-load.ll
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@@ -0,0 +1,58 @@
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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck %s
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+
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+; Regression test for a bug in `DAGCombiner::replaceStoreOfInsertLoad` where
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+; Idx could be smaller than PtrVT, causing a MUL to be emitted with inconsistent
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+; LHS/RHS types.
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+
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+define void @testcase_0(ptr addrspace(1) %in, float %arg) {
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+; CHECK-LABEL: testcase_0:
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+; CHECK: ; %bb.0:
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+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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+; CHECK-NEXT: global_store_dword v[0:1], v2, off offset:12
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+; CHECK-NEXT: s_waitcnt vmcnt(0)
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+; CHECK-NEXT: s_setpc_b64 s[30:31]
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+ %loaded = load <4 x float>, ptr addrspace(1) %in
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+ %modified = insertelement <4 x float> %loaded, float %arg, i64 3
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+ store <4 x float> %modified, ptr addrspace(1) %in
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+ ret void
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+}
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+
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+define void @testcase_1(ptr addrspace(1) %in, float %arg) {
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+; CHECK-LABEL: testcase_1:
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+; CHECK: ; %bb.0:
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+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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+; CHECK-NEXT: global_store_dword v[0:1], v2, off offset:16
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+; CHECK-NEXT: s_waitcnt vmcnt(0)
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+; CHECK-NEXT: s_setpc_b64 s[30:31]
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+ %loaded = load <6 x float>, ptr addrspace(1) %in
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+ %modified = insertelement <6 x float> %loaded, float %arg, i64 4
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+ store <6 x float> %modified, ptr addrspace(1) %in
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+ ret void
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+}
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+
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+define void @testcase_2(ptr addrspace(1) %in, double %arg) {
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+; CHECK-LABEL: testcase_2:
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+; CHECK: ; %bb.0:
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+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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+; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:8
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+; CHECK-NEXT: s_waitcnt vmcnt(0)
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+; CHECK-NEXT: s_setpc_b64 s[30:31]
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+ %loaded = load <4 x double>, ptr addrspace(1) %in
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+ %modified = insertelement <4 x double> %loaded, double %arg, i64 1
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+ store <4 x double> %modified, ptr addrspace(1) %in
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+ ret void
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+}
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+
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+define void @testcase_3(ptr addrspace(1) %in, double %arg) {
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+; CHECK-LABEL: testcase_3:
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+; CHECK: ; %bb.0:
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+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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+; CHECK-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:56
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+; CHECK-NEXT: s_waitcnt vmcnt(0)
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+; CHECK-NEXT: s_setpc_b64 s[30:31]
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+ %loaded = load <8 x double>, ptr addrspace(1) %in
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+ %modified = insertelement <8 x double> %loaded, double %arg, i64 7
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+ store <8 x double> %modified, ptr addrspace(1) %in
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+ ret void
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+}
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--
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2.44.0
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