95 lines
5.1 KiB
Diff
95 lines
5.1 KiB
Diff
From eba58195932f37fb461ae17c69fc517181b99c9a Mon Sep 17 00:00:00 2001
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From: Paul Murphy <paumurph@redhat.com>
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Date: Mon, 30 Jun 2025 10:13:37 -0500
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Subject: [PATCH] [PowerPC] fix lowering of SPILL_CRBIT on pwr9 and pwr10
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If a copy exists between creation of a crbit and a spill, machine-cp
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may delete the copy since it seems unaware of the relation between a cr
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and crbit. A fix was previously made for the generic ppc64 lowering. It
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should be applied to the pwr9 and pwr10 variants too.
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Likewise, relax and extend the pwr8 test to verify pwr9 and pwr10
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codegen too.
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This fixes #143989.
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---
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llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 17 +++++++++++------
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.../PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir | 8 +++++++-
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2 files changed, 18 insertions(+), 7 deletions(-)
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diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
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index 76dca4794e05..78d254a55fd9 100644
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--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
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+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
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@@ -1102,13 +1102,20 @@ void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
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SpillsKnownBit = true;
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break;
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default:
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+ // When spilling a CR bit, The super register may not be explicitly defined
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+ // (i.e. it can be defined by a CR-logical that only defines the subreg) so
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+ // we state that the CR field is undef. Also, in order to preserve the kill
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+ // flag on the CR bit, we add it as an implicit use.
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+
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// On Power10, we can use SETNBC to spill all CR bits. SETNBC will set all
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// bits (specifically, it produces a -1 if the CR bit is set). Ultimately,
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// the bit that is of importance to us is bit 32 (bit 0 of a 32-bit
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// register), and SETNBC will set this.
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if (Subtarget.isISA3_1()) {
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETNBC8 : PPC::SETNBC), Reg)
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- .addReg(SrcReg, RegState::Undef);
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+ .addReg(SrcReg, RegState::Undef)
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+ .addReg(SrcReg, RegState::Implicit |
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+ getKillRegState(MI.getOperand(0).isKill()));
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break;
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}
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@@ -1122,16 +1129,14 @@ void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
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SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT ||
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SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) {
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::SETB8 : PPC::SETB), Reg)
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- .addReg(getCRFromCRBit(SrcReg), RegState::Undef);
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+ .addReg(getCRFromCRBit(SrcReg), RegState::Undef)
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+ .addReg(SrcReg, RegState::Implicit |
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+ getKillRegState(MI.getOperand(0).isKill()));
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break;
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}
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}
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// We need to move the CR field that contains the CR bit we are spilling.
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- // The super register may not be explicitly defined (i.e. it can be defined
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- // by a CR-logical that only defines the subreg) so we state that the CR
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- // field is undef. Also, in order to preserve the kill flag on the CR bit,
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- // we add it as an implicit use.
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BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
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.addReg(getCRFromCRBit(SrcReg), RegState::Undef)
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.addReg(SrcReg,
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diff --git a/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir b/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir
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index 41e21248a3f0..2796cdb3ae87 100644
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--- a/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir
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+++ b/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir
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@@ -1,6 +1,12 @@
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# RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -start-after \
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# RUN: virtregrewriter -ppc-asm-full-reg-names -verify-machineinstrs %s \
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# RUN: -o - | FileCheck %s
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+# RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -start-after \
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+# RUN: virtregrewriter -ppc-asm-full-reg-names -verify-machineinstrs %s \
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+# RUN: -o - | FileCheck %s
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+# RUN: llc -mcpu=pwr10 -mtriple=powerpc64le-unknown-linux-gnu -start-after \
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+# RUN: virtregrewriter -ppc-asm-full-reg-names -verify-machineinstrs %s \
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+# RUN: -o - | FileCheck %s
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--- |
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; ModuleID = 'a.ll'
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@@ -30,7 +36,7 @@
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(ptr, ptr) #1
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- attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" }
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+ attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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!llvm.ident = !{!0}
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--
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2.49.0
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