diff --git a/0001-SystemZ-Avoid-unaligned-VL-VST-s-with-memcpy-memmove.patch b/0001-SystemZ-Avoid-unaligned-VL-VST-s-with-memcpy-memmove.patch new file mode 100644 index 0000000..95a7dfb --- /dev/null +++ b/0001-SystemZ-Avoid-unaligned-VL-VST-s-with-memcpy-memmove.patch @@ -0,0 +1,4156 @@ +From deb79107cdc640de8ccf4512a01512e7a8dcb72e Mon Sep 17 00:00:00 2001 +From: Jonas Paulsson +Date: Tue, 28 Apr 2026 19:09:09 +0200 +Subject: [PATCH] [SystemZ] Avoid unaligned VL/VST:s with + memcpy/memmove/memset. (#187100) + +This is a squash of the proposed backport PR #196359 and its dependencies +to llvm 22: + +[SystemZ] Improved testing for memcpy/memmove/memset. (#194682) +[SystemZ] Avoid unaligned VL/VST:s with memcpy/memmove/memset. (#187100) +[SystemZ] Remove superfluous args in tests. (#196022) +Fix memmove-01.ll test (to use libcalls in some cases). +--- + .../Target/SystemZ/SystemZISelLowering.cpp | 26 +- + llvm/test/CodeGen/SystemZ/memcpy-03.ll | 648 +++++- + llvm/test/CodeGen/SystemZ/memmove-01.ll | 1090 +++++++++ + llvm/test/CodeGen/SystemZ/memset-08.ll | 2018 +++++++++++++++-- + 4 files changed, 3453 insertions(+), 329 deletions(-) + create mode 100644 llvm/test/CodeGen/SystemZ/memmove-01.ll + +diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +index c3ded986fd68..78862759c880 100644 +--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp ++++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +@@ -830,6 +830,10 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM, + MaxStoresPerMemcpy = Subtarget.hasVector() ? 2 : 0; + MaxStoresPerMemcpyOptSize = 0; + ++ // Same with memmove. ++ MaxStoresPerMemmove = Subtarget.hasVector() ? 2 : 0; ++ MaxStoresPerMemmoveOptSize = 0; ++ + // The main memset sequence is a byte store followed by an MVC. + // Two STC or MV..I stores win over that, but the kind of fused stores + // generated by target-independent code don't when the byte value is +@@ -1473,17 +1477,21 @@ bool SystemZTargetLowering::findOptimalMemOpLowering( + LLVMContext &Context, std::vector &MemOps, unsigned Limit, + const MemOp &Op, unsigned DstAS, unsigned SrcAS, + const AttributeList &FuncAttributes) const { ++ ++ assert(Limit != ~0U && ++ "Expected EmitTargetCodeForMemXXX() to handle AlwaysInline cases."); ++ ++ if (Op.isZeroMemset()) ++ return false; // Memset zero: Use XC. ++ + const int MVCFastLen = 16; ++ // Use MVC up to 16 bytes. Small memset uses STC/MVI for first byte. ++ if ((Op.isMemset() ? Op.size() - 1 : Op.size()) <= MVCFastLen) ++ return false; + +- if (Limit != ~unsigned(0)) { +- // Don't expand Op into scalar loads/stores in these cases: +- if (Op.isMemcpy() && Op.allowOverlap() && Op.size() <= MVCFastLen) +- return false; // Small memcpy: Use MVC +- if (Op.isMemset() && Op.size() - 1 <= MVCFastLen) +- return false; // Small memset (first byte with STC/MVI): Use MVC +- if (Op.isZeroMemset()) +- return false; // Memset zero: Use XC +- } ++ // Avoid unaligned VL/VST:s. ++ if (!Op.isAligned(Align(8)) || (Op.size() >= 25 && Op.size() <= 31)) ++ return false; + + return TargetLowering::findOptimalMemOpLowering(Context, MemOps, Limit, Op, + DstAS, SrcAS, FuncAttributes); +diff --git a/llvm/test/CodeGen/SystemZ/memcpy-03.ll b/llvm/test/CodeGen/SystemZ/memcpy-03.ll +index c703aef27532..213764e79ffb 100644 +--- a/llvm/test/CodeGen/SystemZ/memcpy-03.ll ++++ b/llvm/test/CodeGen/SystemZ/memcpy-03.ll +@@ -1,217 +1,661 @@ + ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +-; RUN: llc -mcpu=z15 < %s -mtriple=s390x-linux-gnu | FileCheck %s ++; RUN: llc -mcpu=z17 < %s -mtriple=s390x-linux-gnu | FileCheck %s + ; +-; Test memcpys of small constant lengths that should not be done with MVC. ++; Test non-volatile memcpys of small constant lengths in both aligned and ++; unaligned cases. + + declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind + +-define void @fun16(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun1(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun1: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(1,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 1, i1 false) ++ ret void ++} ++ ++define void @fun1_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun1_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(1,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 1, i1 false) ++ ret void ++} ++ ++define void @fun2(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun2: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(2,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 2, i1 false) ++ ret void ++} ++ ++define void @fun2_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun2_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(2,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 2, i1 false) ++ ret void ++} ++ ++define void @fun3(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun3: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(3,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 3, i1 false) ++ ret void ++} ++ ++define void @fun3_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun3_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(3,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 3, i1 false) ++ ret void ++} ++ ++define void @fun4(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun4: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(4,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 4, i1 false) ++ ret void ++} ++ ++define void @fun4_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun4_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(4,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 4, i1 false) ++ ret void ++} ++ ++define void @fun5(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun5: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(5,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 5, i1 false) ++ ret void ++} ++ ++define void @fun5_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun5_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(5,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 5, i1 false) ++ ret void ++} ++ ++define void @fun6(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun6: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(6,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 6, i1 false) ++ ret void ++} ++ ++define void @fun6_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun6_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(6,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 6, i1 false) ++ ret void ++} ++ ++define void @fun7(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun7: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(7,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 7, i1 false) ++ ret void ++} ++ ++define void @fun7_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun7_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(7,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 7, i1 false) ++ ret void ++} ++ ++define void @fun8(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun8: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(8,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 8, i1 false) ++ ret void ++} ++ ++define void @fun8_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun8_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(8,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 8, i1 false) ++ ret void ++} ++ ++define void @fun9(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun9: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(9,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 9, i1 false) ++ ret void ++} ++ ++define void @fun9_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun9_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(9,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 9, i1 false) ++ ret void ++} ++ ++define void @fun10(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun10: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(10,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 10, i1 false) ++ ret void ++} ++ ++define void @fun10_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun10_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(10,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 10, i1 false) ++ ret void ++} ++ ++define void @fun11(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun11: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(11,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 11, i1 false) ++ ret void ++} ++ ++define void @fun11_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun11_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(11,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 11, i1 false) ++ ret void ++} ++ ++define void @fun12(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun12: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(12,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 12, i1 false) ++ ret void ++} ++ ++define void @fun12_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun12_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(12,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 12, i1 false) ++ ret void ++} ++ ++define void @fun13(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun13: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(13,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 13, i1 false) ++ ret void ++} ++ ++define void @fun13_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun13_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(13,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 13, i1 false) ++ ret void ++} ++ ++define void @fun14(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun14: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(14,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 14, i1 false) ++ ret void ++} ++ ++define void @fun14_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun14_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(14,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 14, i1 false) ++ ret void ++} ++ ++define void @fun15(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun15: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(15,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 15, i1 false) ++ ret void ++} ++ ++define void @fun15_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun15_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(15,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 15, i1 false) ++ ret void ++} ++ ++define void @fun16(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun16: + ; CHECK: # %bb.0: +-; CHECK-NEXT: mvc 0(16,%r3), 0(%r2) ++; CHECK-NEXT: mvc 0(16,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 16, i1 false) ++ ret void ++} ++ ++define void @fun16_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun16_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(16,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 16, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 16, i1 false) + ret void + } + +-define void @fun17(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun17(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun17: + ; CHECK: # %bb.0: +-; CHECK-NEXT: lb %r0, 16(%r2) +-; CHECK-NEXT: stc %r0, 16(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: lb %r0, 16(%r3) ++; CHECK-NEXT: stc %r0, 16(%r2) ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 17, i1 false) ++ ret void ++} ++ ++define void @fun17_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun17_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(17,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 17, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 17, i1 false) + ret void + } + +-define void @fun18(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun17_unalignedSrc(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun17_unalignedSrc: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(17,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 4 %Src, i64 17, i1 false) ++ ret void ++} ++ ++define void @fun18(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun18: + ; CHECK: # %bb.0: +-; CHECK-NEXT: lh %r0, 16(%r2) +-; CHECK-NEXT: sth %r0, 16(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: lh %r0, 16(%r3) ++; CHECK-NEXT: sth %r0, 16(%r2) ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 18, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 18, i1 false) + ret void + } + +-define void @fun19(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun18_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun18_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(18,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 18, i1 false) ++ ret void ++} ++ ++define void @fun18_unalignedDst(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun18_unalignedDst: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(18,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 2 %Dst, ptr align 16 %Src, i64 18, i1 false) ++ ret void ++} ++ ++define void @fun19(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun19: + ; CHECK: # %bb.0: +-; CHECK-NEXT: l %r0, 15(%r2) +-; CHECK-NEXT: st %r0, 15(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: l %r0, 15(%r3) ++; CHECK-NEXT: st %r0, 15(%r2) ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 19, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 19, i1 false) + ret void + } + +-define void @fun20(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun19_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun19_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(19,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 19, i1 false) ++ ret void ++} ++ ++define void @fun20(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun20: + ; CHECK: # %bb.0: +-; CHECK-NEXT: l %r0, 16(%r2) +-; CHECK-NEXT: st %r0, 16(%r3) ++; CHECK-NEXT: l %r0, 16(%r3) ++; CHECK-NEXT: st %r0, 16(%r2) ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 20, i1 false) ++ ret void ++} ++ ++define void @fun20_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun20_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(20,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 20, i1 false) ++ ret void ++} ++ ++define void @fun20_localDst(ptr %Src) { ++; CHECK-LABEL: fun20_localDst: ++; CHECK: # %bb.0: ++; CHECK-NEXT: aghi %r15, -184 ++; CHECK-NEXT: .cfi_def_cfa_offset 344 + ; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: vst %v0, 164(%r15), 4 ++; CHECK-NEXT: mvc 180(4,%r15), 16(%r2) ++; CHECK-NEXT: aghi %r15, 184 + ; CHECK-NEXT: br %r14 ++ %Dst = alloca [20 x i8] + call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 20, i1 false) + ret void + } + +-define void @fun21(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun21(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun21: + ; CHECK: # %bb.0: +-; CHECK-NEXT: lg %r0, 13(%r2) +-; CHECK-NEXT: stg %r0, 13(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: lg %r0, 13(%r3) ++; CHECK-NEXT: stg %r0, 13(%r2) ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 21, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 21, i1 false) + ret void + } + +-define void @fun22(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun21_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun21_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(21,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 21, i1 false) ++ ret void ++} ++ ++define void @fun22(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun22: + ; CHECK: # %bb.0: +-; CHECK-NEXT: lg %r0, 14(%r2) +-; CHECK-NEXT: stg %r0, 14(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: lg %r0, 14(%r3) ++; CHECK-NEXT: stg %r0, 14(%r2) ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 22, i1 false) ++ ret void ++} ++ ++define void @fun22_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun22_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(22,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 22, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 22, i1 false) + ret void + } + +-define void @fun23(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun23(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun23: + ; CHECK: # %bb.0: +-; CHECK-NEXT: lg %r0, 15(%r2) +-; CHECK-NEXT: stg %r0, 15(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: lg %r0, 15(%r3) ++; CHECK-NEXT: stg %r0, 15(%r2) ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 23, i1 false) ++ ret void ++} ++ ++define void @fun23_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun23_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(23,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 23, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 23, i1 false) + ret void + } + +-define void @fun24(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun24(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun24: + ; CHECK: # %bb.0: +-; CHECK-NEXT: lg %r0, 16(%r2) +-; CHECK-NEXT: stg %r0, 16(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: lg %r0, 16(%r3) ++; CHECK-NEXT: stg %r0, 16(%r2) ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 24, i1 false) ++ ret void ++} ++ ++define void @fun24_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun24_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(24,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 24, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 24, i1 false) + ret void + } + +-define void @fun25(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun25(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun25: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vl %v0, 9(%r2) +-; CHECK-NEXT: vst %v0, 9(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: mvc 0(25,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 25, i1 false) ++ ret void ++} ++ ++define void @fun25_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun25_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(25,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 25, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 25, i1 false) + ret void + } + +-define void @fun26(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun26(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun26: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vl %v0, 10(%r2) +-; CHECK-NEXT: vst %v0, 10(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: mvc 0(26,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 26, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 26, i1 false) + ret void + } + +-define void @fun27(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun26_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun26_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(26,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 26, i1 false) ++ ret void ++} ++ ++define void @fun27(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun27: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vl %v0, 11(%r2) +-; CHECK-NEXT: vst %v0, 11(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: mvc 0(27,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 27, i1 false) ++ ret void ++} ++ ++define void @fun27_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun27_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(27,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 27, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 27, i1 false) + ret void + } + +-define void @fun28(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun28(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun28: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vl %v0, 12(%r2) +-; CHECK-NEXT: vst %v0, 12(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: mvc 0(28,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 28, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 28, i1 false) + ret void + } + +-define void @fun29(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun28_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun28_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(28,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 28, i1 false) ++ ret void ++} ++ ++define void @fun29(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun29: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vl %v0, 13(%r2) +-; CHECK-NEXT: vst %v0, 13(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: mvc 0(29,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 29, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 29, i1 false) + ret void + } + +-define void @fun30(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun29_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun29_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(29,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 29, i1 false) ++ ret void ++} ++ ++define void @fun30(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun30: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vl %v0, 14(%r2) +-; CHECK-NEXT: vst %v0, 14(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: mvc 0(30,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 30, i1 false) ++ ret void ++} ++ ++define void @fun30_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun30_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(30,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 30, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 30, i1 false) + ret void + } + +-define void @fun31(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun31(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun31: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vl %v0, 15(%r2) +-; CHECK-NEXT: vst %v0, 15(%r3) +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: mvc 0(31,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 31, i1 false) ++ ret void ++} ++ ++define void @fun31_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun31_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(31,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 31, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 31, i1 false) + ret void + } + +-define void @fun32(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun32(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun32: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vl %v0, 16(%r2), 4 +-; CHECK-NEXT: vst %v0, 16(%r3), 4 +-; CHECK-NEXT: vl %v0, 0(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r3), 4 ++; CHECK-NEXT: vl %v0, 16(%r3), 3 ++; CHECK-NEXT: vst %v0, 16(%r2), 3 ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 32, i1 false) ++ ret void ++} ++ ++define void @fun32_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun32_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(32,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 32, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 32, i1 false) + ret void + } + +-define void @fun33(ptr %Src, ptr %Dst, i8 %val) { ++define void @fun33(ptr %Dst, ptr %Src) { + ; CHECK-LABEL: fun33: + ; CHECK: # %bb.0: +-; CHECK-NEXT: mvc 0(33,%r3), 0(%r2) ++; CHECK-NEXT: mvc 0(33,%r2), 0(%r3) + ; CHECK-NEXT: br %r14 +- call void @llvm.memcpy.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 33, i1 false) ++ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 33, i1 false) + ret void + } + ++define void @fun33_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun33_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvc 0(33,%r2), 0(%r3) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memcpy.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 33, i1 false) ++ ret void ++} +diff --git a/llvm/test/CodeGen/SystemZ/memmove-01.ll b/llvm/test/CodeGen/SystemZ/memmove-01.ll +new file mode 100644 +index 000000000000..b9c60fbe59a7 +--- /dev/null ++++ b/llvm/test/CodeGen/SystemZ/memmove-01.ll +@@ -0,0 +1,1090 @@ ++; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ++; RUN: llc -mcpu=z17 < %s -mtriple=s390x-linux-gnu | FileCheck %s ++; ++; Test non-volatile memmoves of small constant lengths in both aligned and ++; unaligned cases. ++ ++declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind ++ ++define void @fun1(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun1: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 1 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 1, i1 false) ++ ret void ++} ++ ++define void @fun1_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun1_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 1 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 1, i1 false) ++ ret void ++} ++ ++define void @fun2(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun2: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 2 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 2, i1 false) ++ ret void ++} ++ ++define void @fun2_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun2_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 2 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 2, i1 false) ++ ret void ++} ++ ++define void @fun3(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun3: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 3 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 3, i1 false) ++ ret void ++} ++ ++define void @fun3_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun3_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 3 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 3, i1 false) ++ ret void ++} ++ ++define void @fun4(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun4: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 4 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 4, i1 false) ++ ret void ++} ++ ++define void @fun4_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun4_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 4 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 4, i1 false) ++ ret void ++} ++ ++define void @fun5(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun5: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 5 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 5, i1 false) ++ ret void ++} ++ ++define void @fun5_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun5_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 5 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 5, i1 false) ++ ret void ++} ++ ++define void @fun6(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun6: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 6 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 6, i1 false) ++ ret void ++} ++ ++define void @fun6_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun6_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 6 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 6, i1 false) ++ ret void ++} ++ ++define void @fun7(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun7: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 7 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 7, i1 false) ++ ret void ++} ++ ++define void @fun7_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun7_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 7 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 7, i1 false) ++ ret void ++} ++ ++define void @fun8(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun8: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 8 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 8, i1 false) ++ ret void ++} ++ ++define void @fun8_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun8_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 8 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 8, i1 false) ++ ret void ++} ++ ++define void @fun9(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun9: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 9 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 9, i1 false) ++ ret void ++} ++ ++define void @fun9_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun9_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 9 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 9, i1 false) ++ ret void ++} ++ ++define void @fun10(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun10: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 10 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 10, i1 false) ++ ret void ++} ++ ++define void @fun10_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun10_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 10 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 10, i1 false) ++ ret void ++} ++ ++define void @fun11(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun11: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 11 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 11, i1 false) ++ ret void ++} ++ ++define void @fun11_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun11_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 11 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 11, i1 false) ++ ret void ++} ++ ++define void @fun12(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun12: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 12 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 12, i1 false) ++ ret void ++} ++ ++define void @fun12_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun12_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 12 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 12, i1 false) ++ ret void ++} ++ ++define void @fun13(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun13: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 13 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 13, i1 false) ++ ret void ++} ++ ++define void @fun13_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun13_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 13 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 13, i1 false) ++ ret void ++} ++ ++define void @fun14(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun14: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 14 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 14, i1 false) ++ ret void ++} ++ ++define void @fun14_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun14_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 14 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 14, i1 false) ++ ret void ++} ++ ++define void @fun15(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun15: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 15 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 15, i1 false) ++ ret void ++} ++ ++define void @fun15_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun15_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 15 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 15, i1 false) ++ ret void ++} ++ ++define void @fun16(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun16: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 16 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 16, i1 false) ++ ret void ++} ++ ++define void @fun16_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun16_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 16 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 16, i1 false) ++ ret void ++} ++ ++define void @fun17(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun17: ++; CHECK: # %bb.0: ++; CHECK-NEXT: lb %r0, 16(%r3) ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: stc %r0, 16(%r2) ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 17, i1 false) ++ ret void ++} ++ ++define void @fun17_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun17_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 17 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 17, i1 false) ++ ret void ++} ++ ++define void @fun17_unalignedSrc(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun17_unalignedSrc: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 17 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 16 %Dst, ptr align 4 %Src, i64 17, i1 false) ++ ret void ++} ++ ++define void @fun18(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun18: ++; CHECK: # %bb.0: ++; CHECK-NEXT: lh %r0, 16(%r3) ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: sth %r0, 16(%r2) ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 18, i1 false) ++ ret void ++} ++ ++define void @fun18_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun18_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 18 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 18, i1 false) ++ ret void ++} ++ ++define void @fun18_unalignedDst(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun18_unalignedDst: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 18 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 2 %Dst, ptr align 16 %Src, i64 18, i1 false) ++ ret void ++} ++ ++define void @fun19(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun19: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 19 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 19, i1 false) ++ ret void ++} ++ ++define void @fun19_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun19_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 19 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 19, i1 false) ++ ret void ++} ++ ++define void @fun20(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun20: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: l %r0, 16(%r3) ++; CHECK-NEXT: st %r0, 16(%r2) ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 20, i1 false) ++ ret void ++} ++ ++define void @fun20_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun20_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 20 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 20, i1 false) ++ ret void ++} ++ ++define void @fun20_localDst(ptr %Src) { ++; CHECK-LABEL: fun20_localDst: ++; CHECK: # %bb.0: ++; CHECK-NEXT: aghi %r15, -184 ++; CHECK-NEXT: .cfi_def_cfa_offset 344 ++; CHECK-NEXT: vl %v0, 0(%r2), 4 ++; CHECK-NEXT: vst %v0, 164(%r15), 4 ++; CHECK-NEXT: mvc 180(4,%r15), 16(%r2) ++; CHECK-NEXT: aghi %r15, 184 ++; CHECK-NEXT: br %r14 ++ %Dst = alloca [20 x i8] ++ call void @llvm.memmove.p0.p0.i64(ptr align 16 %Dst, ptr align 16 %Src, i64 20, i1 false) ++ ret void ++} ++ ++define void @fun21(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun21: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 21 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 21, i1 false) ++ ret void ++} ++ ++define void @fun21_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun21_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 21 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 21, i1 false) ++ ret void ++} ++ ++define void @fun22(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun22: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 22 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 22, i1 false) ++ ret void ++} ++ ++define void @fun22_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun22_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 22 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 22, i1 false) ++ ret void ++} ++ ++define void @fun23(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun23: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 23 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 23, i1 false) ++ ret void ++} ++ ++define void @fun23_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun23_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 23 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 23, i1 false) ++ ret void ++} ++ ++define void @fun24(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun24: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: lg %r0, 16(%r3) ++; CHECK-NEXT: stg %r0, 16(%r2) ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 24, i1 false) ++ ret void ++} ++ ++define void @fun24_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun24_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 24 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 24, i1 false) ++ ret void ++} ++ ++define void @fun25(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun25: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 25 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 25, i1 false) ++ ret void ++} ++ ++define void @fun25_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun25_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 25 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 25, i1 false) ++ ret void ++} ++ ++define void @fun26(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun26: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 26 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 26, i1 false) ++ ret void ++} ++ ++define void @fun26_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun26_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 26 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 26, i1 false) ++ ret void ++} ++ ++define void @fun27(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun27: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 27 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 27, i1 false) ++ ret void ++} ++ ++define void @fun27_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun27_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 27 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 27, i1 false) ++ ret void ++} ++ ++define void @fun28(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun28: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 28 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 28, i1 false) ++ ret void ++} ++ ++define void @fun28_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun28_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 28 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 28, i1 false) ++ ret void ++} ++ ++define void @fun29(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun29: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 29 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 29, i1 false) ++ ret void ++} ++ ++define void @fun29_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun29_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 29 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 29, i1 false) ++ ret void ++} ++ ++define void @fun30(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun30: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 30 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 30, i1 false) ++ ret void ++} ++ ++define void @fun30_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun30_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 30 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 30, i1 false) ++ ret void ++} ++ ++define void @fun31(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun31: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 31 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 31, i1 false) ++ ret void ++} ++ ++define void @fun31_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun31_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 31 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 31, i1 false) ++ ret void ++} ++ ++define void @fun32(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun32: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vl %v0, 0(%r3), 3 ++; CHECK-NEXT: vl %v1, 16(%r3), 3 ++; CHECK-NEXT: vst %v1, 16(%r2), 3 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 32, i1 false) ++ ret void ++} ++ ++define void @fun32_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun32_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 32 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 32, i1 false) ++ ret void ++} ++ ++define void @fun33(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun33: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 33 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 8 %Dst, ptr align 8 %Src, i64 33, i1 false) ++ ret void ++} ++ ++define void @fun33_unaligned(ptr %Dst, ptr %Src) { ++; CHECK-LABEL: fun33_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stmg %r14, %r15, 112(%r15) ++; CHECK-NEXT: .cfi_offset %r14, -48 ++; CHECK-NEXT: .cfi_offset %r15, -40 ++; CHECK-NEXT: aghi %r15, -160 ++; CHECK-NEXT: .cfi_def_cfa_offset 320 ++; CHECK-NEXT: lghi %r4, 33 ++; CHECK-NEXT: brasl %r14, memmove@PLT ++; CHECK-NEXT: lmg %r14, %r15, 272(%r15) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memmove.p0.p0.i64(ptr align 1 %Dst, ptr align 1 %Src, i64 33, i1 false) ++ ret void ++} +diff --git a/llvm/test/CodeGen/SystemZ/memset-08.ll b/llvm/test/CodeGen/SystemZ/memset-08.ll +index 931230983368..43c50320e011 100644 +--- a/llvm/test/CodeGen/SystemZ/memset-08.ll ++++ b/llvm/test/CodeGen/SystemZ/memset-08.ll +@@ -1,230 +1,1702 @@ + ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py + ; RUN: llc -mcpu=z15 %s -mtriple=s390x-linux-gnu -o - | FileCheck %s + ; +-; Test memsets of small constant lengths, that should not be done with MVC. ++; Test non-volatile memsets of small constant lengths in both aligned and ++; unaligned cases. + + declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) + ++define void @reg1(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg1: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 1, i1 false) ++ ret void ++} ++ ++define void @reg1_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg1_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 1, i1 false) ++ ret void ++} ++ ++define void @reg2(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg2: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 1(%r2) ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 2, i1 false) ++ ret void ++} ++ ++define void @reg2_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg2_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 1(%r2) ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 2, i1 false) ++ ret void ++} ++ ++define void @reg3(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg3: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(2,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 3, i1 false) ++ ret void ++} ++ ++define void @reg3_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg3_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(2,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 3, i1 false) ++ ret void ++} ++ ++define void @reg4(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg4: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(3,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 4, i1 false) ++ ret void ++} ++ ++define void @reg4_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg4_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(3,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 4, i1 false) ++ ret void ++} ++ ++define void @reg5(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg5: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(4,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 5, i1 false) ++ ret void ++} ++ ++define void @reg5_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg5_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(4,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 5, i1 false) ++ ret void ++} ++ ++define void @reg6(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg6: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(5,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 6, i1 false) ++ ret void ++} ++ ++define void @reg6_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg6_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(5,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 6, i1 false) ++ ret void ++} ++ ++define void @reg7(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg7: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(6,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 7, i1 false) ++ ret void ++} ++ ++define void @reg7_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg7_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(6,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 7, i1 false) ++ ret void ++} ++ ++define void @reg8(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg8: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(7,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 8, i1 false) ++ ret void ++} ++ ++define void @reg8_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg8_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(7,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 8, i1 false) ++ ret void ++} ++ ++define void @reg9(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg9: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(8,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 9, i1 false) ++ ret void ++} ++ ++define void @reg9_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg9_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(8,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 9, i1 false) ++ ret void ++} ++ ++define void @reg10(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg10: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(9,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 10, i1 false) ++ ret void ++} ++ ++define void @reg10_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg10_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(9,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 10, i1 false) ++ ret void ++} ++ ++define void @reg11(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg11: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(10,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 11, i1 false) ++ ret void ++} ++ ++define void @reg11_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg11_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(10,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 11, i1 false) ++ ret void ++} ++ ++define void @reg12(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg12: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(11,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 12, i1 false) ++ ret void ++} ++ ++define void @reg12_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg12_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(11,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 12, i1 false) ++ ret void ++} ++ ++define void @reg13(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg13: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(12,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 13, i1 false) ++ ret void ++} ++ ++define void @reg13_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg13_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(12,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 13, i1 false) ++ ret void ++} ++ ++define void @reg14(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg14: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(13,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 14, i1 false) ++ ret void ++} ++ ++define void @reg14_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg14_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(13,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 14, i1 false) ++ ret void ++} ++ ++define void @reg15(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg15: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(14,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 15, i1 false) ++ ret void ++} ++ ++define void @reg15_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg15_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(14,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 15, i1 false) ++ ret void ++} ++ ++define void @reg16(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg16: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(15,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 16, i1 false) ++ ret void ++} ++ ++define void @reg16_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg16_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(15,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 16, i1 false) ++ ret void ++} ++ + define void @reg17(ptr %Dst, i8 %val) { + ; CHECK-LABEL: reg17: + ; CHECK: # %bb.0: +-; CHECK-NEXT: stc %r3, 0(%r2) +-; CHECK-NEXT: mvc 1(16,%r2), 0(%r2) ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(16,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 17, i1 false) ++ ret void ++} ++ ++define void @reg17_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg17_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(16,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 17, i1 false) ++ ret void ++} ++ ++define void @reg18(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg18: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vlvgp %v0, %r3, %r3 ++; CHECK-NEXT: vrepb %v0, %v0, 7 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: vsteh %v0, 16(%r2), 0 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 18, i1 false) ++ ret void ++} ++ ++define void @reg18_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg18_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(17,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 18, i1 false) ++ ret void ++} ++ ++define void @reg19(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg19: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vlvgp %v0, %r3, %r3 ++; CHECK-NEXT: vrepb %v0, %v0, 7 ++; CHECK-NEXT: vstef %v0, 15(%r2), 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 19, i1 false) ++ ret void ++} ++ ++define void @reg19_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg19_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(18,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 19, i1 false) ++ ret void ++} ++ ++define void @reg20(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg20: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vlvgp %v0, %r3, %r3 ++; CHECK-NEXT: vrepb %v0, %v0, 7 ++; CHECK-NEXT: vstef %v0, 16(%r2), 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 20, i1 false) ++ ret void ++} ++ ++define void @reg20_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg20_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(19,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 20, i1 false) ++ ret void ++} ++ ++define void @reg20_localDst(i8 %val) { ++; CHECK-LABEL: reg20_localDst: ++; CHECK: # %bb.0: ++; CHECK-NEXT: aghi %r15, -184 ++; CHECK-NEXT: .cfi_def_cfa_offset 344 ++; CHECK-NEXT: vlvgp %v0, %r2, %r2 ++; CHECK-NEXT: vrepb %v0, %v0, 7 ++; CHECK-NEXT: vstef %v0, 180(%r15), 0 ++; CHECK-NEXT: vst %v0, 164(%r15), 4 ++; CHECK-NEXT: aghi %r15, 184 ++; CHECK-NEXT: br %r14 ++ %Dst = alloca [20 x i8] ++ call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 20, i1 false) ++ ret void ++} ++ ++define void @reg21(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg21: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vlvgp %v0, %r3, %r3 ++; CHECK-NEXT: vrepb %v0, %v0, 7 ++; CHECK-NEXT: vsteg %v0, 13(%r2), 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 21, i1 false) ++ ret void ++} ++ ++define void @reg21_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg21_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(20,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 21, i1 false) ++ ret void ++} ++ ++define void @reg22(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg22: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vlvgp %v0, %r3, %r3 ++; CHECK-NEXT: vrepb %v0, %v0, 7 ++; CHECK-NEXT: vsteg %v0, 14(%r2), 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 22, i1 false) ++ ret void ++} ++ ++define void @reg22_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg22_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(21,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 22, i1 false) ++ ret void ++} ++ ++define void @reg23(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg23: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vlvgp %v0, %r3, %r3 ++; CHECK-NEXT: vrepb %v0, %v0, 7 ++; CHECK-NEXT: vsteg %v0, 15(%r2), 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 23, i1 false) ++ ret void ++} ++ ++define void @reg23_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg23_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(22,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 23, i1 false) ++ ret void ++} ++ ++define void @reg24(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg24: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vlvgp %v0, %r3, %r3 ++; CHECK-NEXT: vrepb %v0, %v0, 7 ++; CHECK-NEXT: vsteg %v0, 16(%r2), 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 24, i1 false) ++ ret void ++} ++ ++define void @reg24_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg24_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(23,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 24, i1 false) ++ ret void ++} ++ ++define void @reg25(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg25: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(24,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 25, i1 false) ++ ret void ++} ++ ++define void @reg25_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg25_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(24,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 25, i1 false) ++ ret void ++} ++ ++define void @reg26(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg26: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(25,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 26, i1 false) ++ ret void ++} ++ ++define void @reg26_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg26_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(25,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 26, i1 false) ++ ret void ++} ++ ++define void @reg27(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg27: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(26,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 27, i1 false) ++ ret void ++} ++ ++define void @reg27_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg27_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(26,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 27, i1 false) ++ ret void ++} ++ ++define void @reg28(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg28: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(27,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 28, i1 false) ++ ret void ++} ++ ++define void @reg28_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg28_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(27,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 28, i1 false) ++ ret void ++} ++ ++define void @reg29(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg29: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(28,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 29, i1 false) ++ ret void ++} ++ ++define void @reg29_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg29_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(28,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 29, i1 false) ++ ret void ++} ++ ++define void @reg30(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg30: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(29,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 30, i1 false) ++ ret void ++} ++ ++define void @reg30_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg30_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(29,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 30, i1 false) ++ ret void ++} ++ ++define void @reg31(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg31: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(30,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 31, i1 false) ++ ret void ++} ++ ++define void @reg31_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg31_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(30,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 31, i1 false) ++ ret void ++} ++ ++define void @reg32(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg32: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vlvgp %v0, %r3, %r3 ++; CHECK-NEXT: vrepb %v0, %v0, 7 ++; CHECK-NEXT: vst %v0, 16(%r2), 3 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 32, i1 false) ++ ret void ++} ++ ++define void @reg32_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg32_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(31,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 32, i1 false) ++ ret void ++} ++ ++define void @reg33(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg33: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(32,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 %val, i64 33, i1 false) ++ ret void ++} ++ ++define void @reg33_unaligned(ptr %Dst, i8 %val) { ++; CHECK-LABEL: reg33_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: stc %r3, 0(%r2) ++; CHECK-NEXT: mvc 1(32,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 %val, i64 33, i1 false) ++ ret void ++} ++ ++;; Immediate value ++ ++define void @imm1(ptr %Dst) { ++; CHECK-LABEL: imm1: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 1 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 1, i64 1, i1 false) ++ ret void ++} ++ ++define void @imm1_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm1_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 255 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 -1, i64 1, i1 false) ++ ret void ++} ++ ++define void @imm2(ptr %Dst) { ++; CHECK-LABEL: imm2: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvhhi 0(%r2), 514 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 2, i64 2, i1 false) ++ ret void ++} ++ ++define void @imm2_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm2_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvhhi 0(%r2), 514 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 2, i64 2, i1 false) ++ ret void ++} ++ ++define void @imm3(ptr %Dst) { ++; CHECK-LABEL: imm3: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 2(%r2), 3 ++; CHECK-NEXT: mvhhi 0(%r2), 771 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 3, i64 3, i1 false) ++ ret void ++} ++ ++define void @imm3_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm3_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 2(%r2), 3 ++; CHECK-NEXT: mvhhi 0(%r2), 771 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 3, i64 3, i1 false) ++ ret void ++} ++ ++define void @imm4(ptr %Dst) { ++; CHECK-LABEL: imm4: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vrepib %v0, 4 ++; CHECK-NEXT: vstef %v0, 0(%r2), 0 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 4, i64 4, i1 false) ++ ret void ++} ++ ++define void @imm4_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm4_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vrepib %v0, 4 ++; CHECK-NEXT: vstef %v0, 0(%r2), 0 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 4, i64 4, i1 false) ++ ret void ++} ++ ++define void @imm5(ptr %Dst) { ++; CHECK-LABEL: imm5: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 5 ++; CHECK-NEXT: mvc 1(4,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 5, i64 5, i1 false) ++ ret void ++} ++ ++define void @imm5_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm5_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 5 ++; CHECK-NEXT: mvc 1(4,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 5, i64 5, i1 false) ++ ret void ++} ++ ++define void @imm6(ptr %Dst) { ++; CHECK-LABEL: imm6: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 6 ++; CHECK-NEXT: mvc 1(5,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 6, i64 6, i1 false) ++ ret void ++} ++ ++define void @imm6_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm6_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 6 ++; CHECK-NEXT: mvc 1(5,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 6, i64 6, i1 false) ++ ret void ++} ++ ++define void @imm7(ptr %Dst) { ++; CHECK-LABEL: imm7: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 7 ++; CHECK-NEXT: mvc 1(6,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 7, i64 7, i1 false) ++ ret void ++} ++ ++define void @imm7_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm7_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 7 ++; CHECK-NEXT: mvc 1(6,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 7, i64 7, i1 false) ++ ret void ++} ++ ++define void @imm8(ptr %Dst) { ++; CHECK-LABEL: imm8: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 8 ++; CHECK-NEXT: mvc 1(7,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 8, i64 8, i1 false) ++ ret void ++} ++ ++define void @imm8_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm8_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 8 ++; CHECK-NEXT: mvc 1(7,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 8, i64 8, i1 false) ++ ret void ++} ++ ++define void @imm9(ptr %Dst) { ++; CHECK-LABEL: imm9: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 9 ++; CHECK-NEXT: mvc 1(8,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 9, i64 9, i1 false) ++ ret void ++} ++ ++define void @imm9_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm9_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 9 ++; CHECK-NEXT: mvc 1(8,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 9, i64 9, i1 false) ++ ret void ++} ++ ++define void @imm10(ptr %Dst) { ++; CHECK-LABEL: imm10: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 10 ++; CHECK-NEXT: mvc 1(9,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 10, i64 10, i1 false) ++ ret void ++} ++ ++define void @imm10_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm10_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 10 ++; CHECK-NEXT: mvc 1(9,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 10, i64 10, i1 false) ++ ret void ++} ++ ++define void @imm11(ptr %Dst) { ++; CHECK-LABEL: imm11: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 11 ++; CHECK-NEXT: mvc 1(10,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 11, i64 11, i1 false) ++ ret void ++} ++ ++define void @imm11_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm11_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 11 ++; CHECK-NEXT: mvc 1(10,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 11, i64 11, i1 false) ++ ret void ++} ++ ++define void @imm12(ptr %Dst) { ++; CHECK-LABEL: imm12: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 12 ++; CHECK-NEXT: mvc 1(11,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 12, i64 12, i1 false) ++ ret void ++} ++ ++define void @imm12_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm12_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 12 ++; CHECK-NEXT: mvc 1(11,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 12, i64 12, i1 false) ++ ret void ++} ++ ++define void @imm13(ptr %Dst) { ++; CHECK-LABEL: imm13: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 13 ++; CHECK-NEXT: mvc 1(12,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 13, i64 13, i1 false) ++ ret void ++} ++ ++define void @imm13_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm13_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 13 ++; CHECK-NEXT: mvc 1(12,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 13, i64 13, i1 false) ++ ret void ++} ++ ++define void @imm14(ptr %Dst) { ++; CHECK-LABEL: imm14: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 14 ++; CHECK-NEXT: mvc 1(13,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 14, i64 14, i1 false) ++ ret void ++} ++ ++define void @imm14_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm14_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 14 ++; CHECK-NEXT: mvc 1(13,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 14, i64 14, i1 false) ++ ret void ++} ++ ++define void @imm15(ptr %Dst) { ++; CHECK-LABEL: imm15: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 15 ++; CHECK-NEXT: mvc 1(14,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 15, i64 15, i1 false) ++ ret void ++} ++ ++define void @imm15_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm15_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 15 ++; CHECK-NEXT: mvc 1(14,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 15, i64 15, i1 false) ++ ret void ++} ++ ++define void @imm16(ptr %Dst) { ++; CHECK-LABEL: imm16: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 16 ++; CHECK-NEXT: mvc 1(15,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 16, i64 16, i1 false) ++ ret void ++} ++ ++define void @imm16_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm16_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 16 ++; CHECK-NEXT: mvc 1(15,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 16, i64 16, i1 false) ++ ret void ++} ++ ++define void @imm17(ptr %Dst) { ++; CHECK-LABEL: imm17: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 17 ++; CHECK-NEXT: mvc 1(16,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 17, i64 17, i1 false) ++ ret void ++} ++ ++define void @imm17_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm17_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 17 ++; CHECK-NEXT: mvc 1(16,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 17, i64 17, i1 false) ++ ret void ++} ++ ++define void @imm18(ptr %Dst) { ++; CHECK-LABEL: imm18: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vrepib %v0, 18 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: mvhhi 16(%r2), 4626 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 18, i64 18, i1 false) ++ ret void ++} ++ ++define void @imm18_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm18_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 18 ++; CHECK-NEXT: mvc 1(17,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 18, i64 18, i1 false) ++ ret void ++} ++ ++define void @imm19(ptr %Dst) { ++; CHECK-LABEL: imm19: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vrepib %v0, 19 ++; CHECK-NEXT: vstef %v0, 15(%r2), 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 19, i64 19, i1 false) ++ ret void ++} ++ ++define void @imm19_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm19_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 19 ++; CHECK-NEXT: mvc 1(18,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 19, i64 19, i1 false) ++ ret void ++} ++ ++define void @imm20(ptr %Dst) { ++; CHECK-LABEL: imm20: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vrepib %v0, 20 ++; CHECK-NEXT: vstef %v0, 16(%r2), 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 20, i64 20, i1 false) ++ ret void ++} ++ ++define void @imm20_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm20_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 20 ++; CHECK-NEXT: mvc 1(19,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 20, i64 20, i1 false) ++ ret void ++} ++ ++define void @imm20_localDst() { ++; CHECK-LABEL: imm20_localDst: ++; CHECK: # %bb.0: ++; CHECK-NEXT: aghi %r15, -184 ++; CHECK-NEXT: .cfi_def_cfa_offset 344 ++; CHECK-NEXT: vrepib %v0, 20 ++; CHECK-NEXT: vstef %v0, 180(%r15), 0 ++; CHECK-NEXT: vst %v0, 164(%r15), 4 ++; CHECK-NEXT: aghi %r15, 184 ++; CHECK-NEXT: br %r14 ++ %Dst = alloca [20 x i8] ++ call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 20, i64 20, i1 false) ++ ret void ++} ++ ++define void @imm21(ptr %Dst) { ++; CHECK-LABEL: imm21: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vrepib %v0, 21 ++; CHECK-NEXT: vsteg %v0, 13(%r2), 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 21, i64 21, i1 false) ++ ret void ++} ++ ++define void @imm21_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm21_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 21 ++; CHECK-NEXT: mvc 1(20,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 21, i64 21, i1 false) ++ ret void ++} ++ ++define void @imm22(ptr %Dst) { ++; CHECK-LABEL: imm22: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vrepib %v0, 22 ++; CHECK-NEXT: vsteg %v0, 14(%r2), 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 22, i64 22, i1 false) ++ ret void ++} ++ ++define void @imm22_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm22_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 22 ++; CHECK-NEXT: mvc 1(21,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 22, i64 22, i1 false) ++ ret void ++} ++ ++define void @imm23(ptr %Dst) { ++; CHECK-LABEL: imm23: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vrepib %v0, 23 ++; CHECK-NEXT: vsteg %v0, 15(%r2), 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 23, i64 23, i1 false) ++ ret void ++} ++ ++define void @imm23_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm23_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 23 ++; CHECK-NEXT: mvc 1(22,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 23, i64 23, i1 false) ++ ret void ++} ++ ++define void @imm24(ptr %Dst) { ++; CHECK-LABEL: imm24: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vrepib %v0, 24 ++; CHECK-NEXT: vsteg %v0, 16(%r2), 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 24, i64 24, i1 false) ++ ret void ++} ++ ++define void @imm24_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm24_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 24 ++; CHECK-NEXT: mvc 1(23,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 24, i64 24, i1 false) ++ ret void ++} ++ ++define void @imm25(ptr %Dst) { ++; CHECK-LABEL: imm25: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 25 ++; CHECK-NEXT: mvc 1(24,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 25, i64 25, i1 false) ++ ret void ++} ++ ++define void @imm25_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm25_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 25 ++; CHECK-NEXT: mvc 1(24,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 25, i64 25, i1 false) ++ ret void ++} ++ ++define void @imm26(ptr %Dst) { ++; CHECK-LABEL: imm26: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 26 ++; CHECK-NEXT: mvc 1(25,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 26, i64 26, i1 false) ++ ret void ++} ++ ++define void @imm26_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm26_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 26 ++; CHECK-NEXT: mvc 1(25,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 26, i64 26, i1 false) ++ ret void ++} ++ ++define void @imm27(ptr %Dst) { ++; CHECK-LABEL: imm27: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 27 ++; CHECK-NEXT: mvc 1(26,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 27, i64 27, i1 false) ++ ret void ++} ++ ++define void @imm27_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm27_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 27 ++; CHECK-NEXT: mvc 1(26,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 27, i64 27, i1 false) ++ ret void ++} ++ ++define void @imm28(ptr %Dst) { ++; CHECK-LABEL: imm28: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 28 ++; CHECK-NEXT: mvc 1(27,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 28, i64 28, i1 false) ++ ret void ++} ++ ++define void @imm28_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm28_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 28 ++; CHECK-NEXT: mvc 1(27,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 28, i64 28, i1 false) ++ ret void ++} ++ ++define void @imm29(ptr %Dst) { ++; CHECK-LABEL: imm29: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 29 ++; CHECK-NEXT: mvc 1(28,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 29, i64 29, i1 false) ++ ret void ++} ++ ++define void @imm29_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm29_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 29 ++; CHECK-NEXT: mvc 1(28,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 29, i64 29, i1 false) ++ ret void ++} ++ ++define void @imm30(ptr %Dst) { ++; CHECK-LABEL: imm30: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 30 ++; CHECK-NEXT: mvc 1(29,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 30, i64 30, i1 false) ++ ret void ++} ++ ++define void @imm30_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm30_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 30 ++; CHECK-NEXT: mvc 1(29,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 30, i64 30, i1 false) ++ ret void ++} ++ ++define void @imm31(ptr %Dst) { ++; CHECK-LABEL: imm31: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 31 ++; CHECK-NEXT: mvc 1(30,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 31, i64 31, i1 false) ++ ret void ++} ++ ++define void @imm31_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm31_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 31 ++; CHECK-NEXT: mvc 1(30,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 31, i64 31, i1 false) ++ ret void ++} ++ ++define void @imm32(ptr %Dst) { ++; CHECK-LABEL: imm32: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vrepib %v0, 32 ++; CHECK-NEXT: vst %v0, 16(%r2), 3 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 32, i64 32, i1 false) ++ ret void ++} ++ ++define void @imm32_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm32_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 32 ++; CHECK-NEXT: mvc 1(31,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 32, i64 32, i1 false) ++ ret void ++} ++ ++define void @imm33(ptr %Dst) { ++; CHECK-LABEL: imm33: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 33 ++; CHECK-NEXT: mvc 1(32,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 33, i64 33, i1 false) ++ ret void ++} ++ ++define void @imm33_unaligned(ptr %Dst) { ++; CHECK-LABEL: imm33_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 33 ++; CHECK-NEXT: mvc 1(32,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 33, i64 33, i1 false) ++ ret void ++} ++ ++;; zero ++ ++define void @zero1(ptr %Dst) { ++; CHECK-LABEL: zero1: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 0 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 1, i1 false) ++ ret void ++} ++ ++define void @zero1_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero1_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvi 0(%r2), 0 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 1, i1 false) ++ ret void ++} ++ ++define void @zero2(ptr %Dst) { ++; CHECK-LABEL: zero2: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvhhi 0(%r2), 0 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 2, i1 false) ++ ret void ++} ++ ++define void @zero2_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero2_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvhhi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 17, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 2, i1 false) + ret void + } + +-define void @reg18(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg18: ++define void @zero3(ptr %Dst) { ++; CHECK-LABEL: zero3: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 +-; CHECK-NEXT: vsteh %v0, 16(%r2), 0 ++; CHECK-NEXT: mvi 2(%r2), 0 ++; CHECK-NEXT: mvhhi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 18, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 3, i1 false) + ret void + } + +-define void @reg19(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg19: ++define void @zero3_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero3_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vstef %v0, 15(%r2), 0 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: mvi 2(%r2), 0 ++; CHECK-NEXT: mvhhi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 19, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 3, i1 false) + ret void + } + +-define void @reg20(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg20: ++define void @zero4(ptr %Dst) { ++; CHECK-LABEL: zero4: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vstef %v0, 16(%r2), 0 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: mvhi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 20, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 4, i1 false) + ret void + } + +-define void @reg21(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg21: ++define void @zero4_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero4_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vsteg %v0, 13(%r2), 0 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: mvhi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 21, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 4, i1 false) + ret void + } + +-define void @reg22(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg22: ++define void @zero5(ptr %Dst) { ++; CHECK-LABEL: zero5: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vsteg %v0, 14(%r2), 0 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: mvi 4(%r2), 0 ++; CHECK-NEXT: mvhi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 22, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 5, i1 false) + ret void + } + +-define void @reg23(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg23: ++define void @zero5_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero5_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vsteg %v0, 15(%r2), 0 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: mvi 4(%r2), 0 ++; CHECK-NEXT: mvhi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 23, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 5, i1 false) + ret void + } + +-define void @reg24(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg24: ++define void @zero6(ptr %Dst) { ++; CHECK-LABEL: zero6: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vsteg %v0, 16(%r2), 0 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: mvhhi 4(%r2), 0 ++; CHECK-NEXT: mvhi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 24, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 6, i1 false) + ret void + } + +-define void @reg25(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg25: ++define void @zero6_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero6_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vst %v0, 9(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: mvhhi 4(%r2), 0 ++; CHECK-NEXT: mvhi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 25, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 6, i1 false) + ret void + } + +-define void @reg26(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg26: ++define void @zero7(ptr %Dst) { ++; CHECK-LABEL: zero7: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vst %v0, 10(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(7,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 26, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 7, i1 false) + ret void + } + +-define void @reg27(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg27: ++define void @zero7_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero7_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vst %v0, 11(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(7,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 27, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 7, i1 false) + ret void + } + +-define void @reg28(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg28: ++define void @zero8(ptr %Dst) { ++; CHECK-LABEL: zero8: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vst %v0, 12(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: mvghi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 28, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 8, i1 false) + ret void + } + +-define void @reg29(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg29: ++define void @zero8_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero8_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vst %v0, 13(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: mvi 0(%r2), 8 ++; CHECK-NEXT: mvc 1(7,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 29, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 8, i64 8, i1 false) + ret void + } + +-define void @reg30(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg30: ++define void @zero9(ptr %Dst) { ++; CHECK-LABEL: zero9: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vst %v0, 14(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: mvi 8(%r2), 0 ++; CHECK-NEXT: mvghi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 30, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 9, i1 false) + ret void + } + +-define void @reg31(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg31: ++define void @zero9_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero9_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vst %v0, 15(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: mvi 8(%r2), 0 ++; CHECK-NEXT: mvghi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 31, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 9, i1 false) + ret void + } + +-define void @reg32(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg32: ++define void @zero10(ptr %Dst) { ++; CHECK-LABEL: zero10: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vlvgp %v0, %r3, %r3 +-; CHECK-NEXT: vrepb %v0, %v0, 7 +-; CHECK-NEXT: vst %v0, 16(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: mvhhi 8(%r2), 0 ++; CHECK-NEXT: mvghi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 32, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 10, i1 false) + ret void + } + +-define void @reg33(ptr %Dst, i8 %val) { +-; CHECK-LABEL: reg33: ++define void @zero10_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero10_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: stc %r3, 0(%r2) +-; CHECK-NEXT: mvc 1(32,%r2), 0(%r2) ++; CHECK-NEXT: mvhhi 8(%r2), 0 ++; CHECK-NEXT: mvghi 0(%r2), 0 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 %val, i64 33, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 10, i1 false) + ret void + } + +-;; Immediate value ++define void @zero11(ptr %Dst) { ++; CHECK-LABEL: zero11: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(11,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 11, i1 false) ++ ret void ++} + +-define void @imm17(ptr %Dst) { +-; CHECK-LABEL: imm17: ++define void @zero11_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero11_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: mvi 0(%r2), 1 +-; CHECK-NEXT: mvc 1(16,%r2), 0(%r2) ++; CHECK-NEXT: xc 0(11,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 1, i64 17, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 11, i1 false) + ret void + } + +-define void @imm18(ptr %Dst) { +-; CHECK-LABEL: imm18: ++define void @zero12(ptr %Dst) { ++; CHECK-LABEL: zero12: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvhi 8(%r2), 0 ++; CHECK-NEXT: mvghi 0(%r2), 0 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 12, i1 false) ++ ret void ++} ++ ++define void @zero12_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero12_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: mvhi 8(%r2), 0 ++; CHECK-NEXT: mvghi 0(%r2), 0 ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 12, i1 false) ++ ret void ++} ++ ++define void @zero13(ptr %Dst) { ++; CHECK-LABEL: zero13: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(13,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 13, i1 false) ++ ret void ++} ++ ++define void @zero13_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero13_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(13,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 13, i1 false) ++ ret void ++} ++ ++define void @zero14(ptr %Dst) { ++; CHECK-LABEL: zero14: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(14,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 14, i1 false) ++ ret void ++} ++ ++define void @zero14_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero14_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(14,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 14, i1 false) ++ ret void ++} ++ ++define void @zero15(ptr %Dst) { ++; CHECK-LABEL: zero15: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(15,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 15, i1 false) ++ ret void ++} ++ ++define void @zero15_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero15_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(15,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 15, i1 false) ++ ret void ++} ++ ++define void @zero16(ptr %Dst) { ++; CHECK-LABEL: zero16: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vgbm %v0, 65535 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 +-; CHECK-NEXT: mvhhi 16(%r2), -1 ++; CHECK-NEXT: vgbm %v0, 0 ++; CHECK-NEXT: vst %v0, 0(%r2), 3 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 -1, i64 18, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 16, i1 false) ++ ret void ++} ++ ++define void @zero16_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero16_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: vgbm %v0, 0 ++; CHECK-NEXT: vst %v0, 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 16, i1 false) ++ ret void ++} ++ ++define void @zero17(ptr %Dst) { ++; CHECK-LABEL: zero17: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(17,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 17, i1 false) ++ ret void ++} ++ ++define void @zero17_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero17_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(17,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 17, i1 false) + ret void + } + +@@ -233,95 +1705,155 @@ define void @zero18(ptr %Dst) { + ; CHECK: # %bb.0: + ; CHECK-NEXT: xc 0(18,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 0, i64 18, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 18, i1 false) + ret void + } + +-define void @imm19(ptr %Dst) { +-; CHECK-LABEL: imm19: ++define void @zero18_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero18_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vrepib %v0, 1 +-; CHECK-NEXT: vstef %v0, 15(%r2), 0 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(18,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 1, i64 19, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 18, i1 false) + ret void + } + +-define void @imm20(ptr %Dst) { +-; CHECK-LABEL: imm20: ++define void @zero19(ptr %Dst) { ++; CHECK-LABEL: zero19: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vgbm %v0, 65535 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 +-; CHECK-NEXT: mvhi 16(%r2), -1 ++; CHECK-NEXT: xc 0(19,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 -1, i64 20, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 19, i1 false) + ret void + } + +-define void @imm21(ptr %Dst) { +-; CHECK-LABEL: imm21: ++define void @zero19_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero19_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vrepib %v0, 1 +-; CHECK-NEXT: vsteg %v0, 13(%r2), 0 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(19,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 1, i64 21, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 19, i1 false) + ret void + } + +-define void @imm22(ptr %Dst) { +-; CHECK-LABEL: imm22: ++define void @zero20(ptr %Dst) { ++; CHECK-LABEL: zero20: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vgbm %v0, 65535 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 +-; CHECK-NEXT: mvghi 14(%r2), -1 ++; CHECK-NEXT: xc 0(20,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 -1, i64 22, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 20, i1 false) + ret void + } + +-define void @imm23(ptr %Dst) { +-; CHECK-LABEL: imm23: ++define void @zero20_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero20_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vrepib %v0, 1 +-; CHECK-NEXT: vsteg %v0, 15(%r2), 0 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(20,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 1, i64 23, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 20, i1 false) + ret void + } + +-define void @imm24(ptr %Dst) { +-; CHECK-LABEL: imm24: ++define void @zero20_localDst() { ++; CHECK-LABEL: zero20_localDst: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vgbm %v0, 65535 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 +-; CHECK-NEXT: mvghi 16(%r2), -1 ++; CHECK-NEXT: aghi %r15, -184 ++; CHECK-NEXT: .cfi_def_cfa_offset 344 ++; CHECK-NEXT: xc 164(20,%r15), 164(%r15) ++; CHECK-NEXT: aghi %r15, 184 + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 -1, i64 24, i1 false) ++ %Dst = alloca [20 x i8] ++ call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 0, i64 20, i1 false) + ret void + } + +-define void @imm25(ptr %Dst) { +-; CHECK-LABEL: imm25: ++define void @zero21(ptr %Dst) { ++; CHECK-LABEL: zero21: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vrepib %v0, 1 +-; CHECK-NEXT: vst %v0, 9(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(21,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 1, i64 25, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 21, i1 false) + ret void + } + +-define void @imm26(ptr %Dst) { +-; CHECK-LABEL: imm26: ++define void @zero21_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero21_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(21,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 21, i1 false) ++ ret void ++} ++ ++define void @zero22(ptr %Dst) { ++; CHECK-LABEL: zero22: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(22,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 22, i1 false) ++ ret void ++} ++ ++define void @zero22_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero22_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(22,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 22, i1 false) ++ ret void ++} ++ ++define void @zero23(ptr %Dst) { ++; CHECK-LABEL: zero23: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(23,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 23, i1 false) ++ ret void ++} ++ ++define void @zero23_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero23_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(23,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 23, i1 false) ++ ret void ++} ++ ++define void @zero24(ptr %Dst) { ++; CHECK-LABEL: zero24: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(24,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 24, i1 false) ++ ret void ++} ++ ++define void @zero24_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero24_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(24,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 24, i1 false) ++ ret void ++} ++ ++define void @zero25(ptr %Dst) { ++; CHECK-LABEL: zero25: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(25,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 25, i1 false) ++ ret void ++} ++ ++define void @zero25_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero25_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vgbm %v0, 65535 +-; CHECK-NEXT: vst %v0, 10(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(25,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 -1, i64 26, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 25, i1 false) + ret void + } + +@@ -330,73 +1862,106 @@ define void @zero26(ptr %Dst) { + ; CHECK: # %bb.0: + ; CHECK-NEXT: xc 0(26,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 0, i64 26, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 26, i1 false) + ret void + } + +-define void @imm27(ptr %Dst) { +-; CHECK-LABEL: imm27: ++define void @zero26_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero26_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vrepib %v0, 1 +-; CHECK-NEXT: vst %v0, 11(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(26,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 1, i64 27, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 26, i1 false) + ret void + } + +-define void @imm28(ptr %Dst) { +-; CHECK-LABEL: imm28: ++define void @zero27(ptr %Dst) { ++; CHECK-LABEL: zero27: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vgbm %v0, 65535 +-; CHECK-NEXT: vst %v0, 12(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(27,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 -1, i64 28, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 27, i1 false) + ret void + } + +-define void @imm29(ptr %Dst) { +-; CHECK-LABEL: imm29: ++define void @zero27_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero27_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vrepib %v0, 1 +-; CHECK-NEXT: vst %v0, 13(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(27,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 1, i64 29, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 27, i1 false) + ret void + } + +-define void @imm30(ptr %Dst) { +-; CHECK-LABEL: imm30: ++define void @zero28(ptr %Dst) { ++; CHECK-LABEL: zero28: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vgbm %v0, 65535 +-; CHECK-NEXT: vst %v0, 14(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(28,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 -1, i64 30, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 28, i1 false) + ret void + } + +-define void @imm31(ptr %Dst) { +-; CHECK-LABEL: imm31: ++define void @zero28_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero28_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vrepib %v0, 1 +-; CHECK-NEXT: vst %v0, 15(%r2) +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(28,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 1, i64 31, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 28, i1 false) + ret void + } + +-define void @imm32(ptr %Dst) { +-; CHECK-LABEL: imm32: ++define void @zero29(ptr %Dst) { ++; CHECK-LABEL: zero29: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(29,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 29, i1 false) ++ ret void ++} ++ ++define void @zero29_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero29_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(29,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 29, i1 false) ++ ret void ++} ++ ++define void @zero30(ptr %Dst) { ++; CHECK-LABEL: zero30: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(30,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 30, i1 false) ++ ret void ++} ++ ++define void @zero30_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero30_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(30,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 30, i1 false) ++ ret void ++} ++ ++define void @zero31(ptr %Dst) { ++; CHECK-LABEL: zero31: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(31,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 31, i1 false) ++ ret void ++} ++ ++define void @zero31_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero31_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: vgbm %v0, 65535 +-; CHECK-NEXT: vst %v0, 16(%r2), 4 +-; CHECK-NEXT: vst %v0, 0(%r2), 4 ++; CHECK-NEXT: xc 0(31,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 -1, i64 32, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 31, i1 false) + ret void + } + +@@ -405,16 +1970,33 @@ define void @zero32(ptr %Dst) { + ; CHECK: # %bb.0: + ; CHECK-NEXT: xc 0(32,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 0, i64 32, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 32, i1 false) + ret void + } + +-define void @imm33(ptr %Dst) { +-; CHECK-LABEL: imm33: ++define void @zero32_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero32_unaligned: + ; CHECK: # %bb.0: +-; CHECK-NEXT: mvi 0(%r2), 1 +-; CHECK-NEXT: mvc 1(32,%r2), 0(%r2) ++; CHECK-NEXT: xc 0(32,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 32, i1 false) ++ ret void ++} ++ ++define void @zero33(ptr %Dst) { ++; CHECK-LABEL: zero33: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(33,%r2), 0(%r2) ++; CHECK-NEXT: br %r14 ++ call void @llvm.memset.p0.i64(ptr align 8 %Dst, i8 0, i64 33, i1 false) ++ ret void ++} ++ ++define void @zero33_unaligned(ptr %Dst) { ++; CHECK-LABEL: zero33_unaligned: ++; CHECK: # %bb.0: ++; CHECK-NEXT: xc 0(33,%r2), 0(%r2) + ; CHECK-NEXT: br %r14 +- call void @llvm.memset.p0.i64(ptr align 16 %Dst, i8 1, i64 33, i1 false) ++ call void @llvm.memset.p0.i64(ptr align 1 %Dst, i8 0, i64 33, i1 false) + ret void + } +-- +2.54.0 + diff --git a/0b6a1ef429.patch b/0b6a1ef429.patch new file mode 100644 index 0000000..8f6e2db --- /dev/null +++ b/0b6a1ef429.patch @@ -0,0 +1,70 @@ +From 0b6a1ef4297bb839fe26041602d32411358e0032 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Miro=20Hron=C4=8Dok?= +Date: Tue, 26 May 2026 01:41:01 +0200 +Subject: [PATCH] [lit] Normalize RLIM_INFINITY to "infinity" in + print_limits.py for Python 3.15+ (#190953) + +Python 3.15 changed resource.getrlimit() to return the platform's +maximum value (e.g., 18446744073709551615 on 64-bit systems) instead of +-1 for RLIM_INFINITY. This breaks lit tests that expect -1 for unlimited +resource limits. + +This patch normalizes the return value to "infinity" when it equals +RLIM_INFINITY to maintain compatibility with existing tests across all +Python versions. + +Fixes test failure: shtest-ulimit-nondarwin.py +Expected: RLIMIT_FSIZE=-1 +Got: RLIMIT_FSIZE=18446744073709551615 + +Reference: +https://github.com/python/cpython/commit/0324c726dea702282a0300225e989b19ae23b759 +Reference: https://bugzilla.redhat.com/show_bug.cgi?id=2448969 + +Analysis and testing assisted by AI. + +Assisted-by: Claude Sonnet 4.5 + +--------- + +Co-authored-by: Alexander Richardson +Co-authored-by: Tulio Magno Quites Machado Filho +--- + .../tests/Inputs/shtest-ulimit/print_limits.py | 17 +++++++++++++---- + llvm/utils/lit/tests/shtest-ulimit-nondarwin.py | 2 +- + 2 files changed, 14 insertions(+), 5 deletions(-) + +diff --git a/llvm/utils/lit/tests/Inputs/shtest-ulimit/print_limits.py b/llvm/utils/lit/tests/Inputs/shtest-ulimit/print_limits.py +index c732c0429e661..6c03721baf36d 100644 +--- a/llvm/utils/lit/tests/Inputs/shtest-ulimit/print_limits.py ++++ b/llvm/utils/lit/tests/Inputs/shtest-ulimit/print_limits.py +@@ -1,6 +1,15 @@ + import resource + +-print("RLIMIT_AS=" + str(resource.getrlimit(resource.RLIMIT_AS)[0])) +-print("RLIMIT_NOFILE=" + str(resource.getrlimit(resource.RLIMIT_NOFILE)[0])) +-print("RLIMIT_STACK=" + str(resource.getrlimit(resource.RLIMIT_STACK)[0])) +-print("RLIMIT_FSIZE=" + str(resource.getrlimit(resource.RLIMIT_FSIZE)[0])) ++ ++def normalize_limit(limit_value): ++ """Normalize RLIM_INFINITY to "infinity" for consistency across Python versions. ++ ++ Python 3.15+ returns the platform's max value (e.g., 2^64-1) instead of -1. ++ """ ++ return "infinity" if limit_value == resource.RLIM_INFINITY else str(limit_value) ++ ++ ++print("RLIMIT_AS=" + normalize_limit(resource.getrlimit(resource.RLIMIT_AS)[0])) ++print("RLIMIT_NOFILE=" + normalize_limit(resource.getrlimit(resource.RLIMIT_NOFILE)[0])) ++print("RLIMIT_STACK=" + normalize_limit(resource.getrlimit(resource.RLIMIT_STACK)[0])) ++print("RLIMIT_FSIZE=" + normalize_limit(resource.getrlimit(resource.RLIMIT_FSIZE)[0])) +diff --git a/llvm/utils/lit/tests/shtest-ulimit-nondarwin.py b/llvm/utils/lit/tests/shtest-ulimit-nondarwin.py +index 43811db750f80..80844d1d79460 100644 +--- a/llvm/utils/lit/tests/shtest-ulimit-nondarwin.py ++++ b/llvm/utils/lit/tests/shtest-ulimit-nondarwin.py +@@ -18,4 +18,4 @@ + # CHECK: ulimit -f 5 + # CHECK: RLIMIT_FSIZE=5 + # CHECK: ulimit -f unlimited +-# CHECK: RLIMIT_FSIZE=-1 ++# CHECK: RLIMIT_FSIZE=infinity diff --git a/22-185375.patch b/22-185375.patch deleted file mode 100644 index 82c3af9..0000000 --- a/22-185375.patch +++ /dev/null @@ -1,86 +0,0 @@ -From f463bef09be73ae9a415fcd3fd49689bd95b0f0a Mon Sep 17 00:00:00 2001 -From: Congcong Cai -Date: Fri, 20 Feb 2026 07:03:27 +0800 -Subject: [PATCH] [SimplifyCFG] process prof data when remove case in umin - (#182261) - -In #164097, we introduce a optimization for umin. But it does not handle -profile data correctly. -This PR remove profile data when remove cases. -Fixed: #181837 - -(cherry picked from commit 31e5f86a3cdc960ef7b2f0a533c4a37cf526cacd) ---- - llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 2 +- - .../Transforms/SimplifyCFG/switch-umin.ll | 43 +++++++++++++++++++ - 2 files changed, 44 insertions(+), 1 deletion(-) - -diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp -index 5f4807242581d..a16f274a4ed5a 100644 ---- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp -+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp -@@ -7724,7 +7724,7 @@ static bool simplifySwitchWhenUMin(SwitchInst *SI, DomTreeUpdater *DTU) { - BasicBlock *DeadCaseBB = I->getCaseSuccessor(); - DeadCaseBB->removePredecessor(BB); - Updates.push_back({DominatorTree::Delete, BB, DeadCaseBB}); -- I = SIW->removeCase(I); -+ I = SIW.removeCase(I); - E = SIW->case_end(); - } - -diff --git a/llvm/test/Transforms/SimplifyCFG/switch-umin.ll b/llvm/test/Transforms/SimplifyCFG/switch-umin.ll -index 44665365dc222..ff958e4d04147 100644 ---- a/llvm/test/Transforms/SimplifyCFG/switch-umin.ll -+++ b/llvm/test/Transforms/SimplifyCFG/switch-umin.ll -@@ -239,8 +239,51 @@ case4: - - } - -+define void @switch_remove_dead_cases(i32 %x) { -+; CHECK-LABEL: define void @switch_remove_dead_cases( -+; CHECK-SAME: i32 [[X:%.*]]) { -+; CHECK-NEXT: [[MIN:%.*]] = call i32 @llvm.umin.i32(i32 [[X]], i32 4) -+; CHECK-NEXT: switch i32 [[X]], label %[[COMMON_RET:.*]] [ -+; CHECK-NEXT: i32 2, label %[[CASE_A:.*]] -+; CHECK-NEXT: i32 3, label %[[CASE_B:.*]] -+; CHECK-NEXT: ], !prof [[PROF1:![0-9]+]] -+; CHECK: [[COMMON_RET]]: -+; CHECK-NEXT: ret void -+; CHECK: [[CASE_A]]: -+; CHECK-NEXT: call void @a() -+; CHECK-NEXT: br label %[[COMMON_RET]] -+; CHECK: [[CASE_B]]: -+; CHECK-NEXT: call void @b() -+; CHECK-NEXT: br label %[[COMMON_RET]] -+; -+ %min = call i32 @llvm.umin.i32(i32 %x, i32 4) -+ switch i32 %min, label %unreachable [ -+ i32 2, label %case_a -+ i32 3, label %case_b -+ i32 4, label %case_ret -+ i32 5, label %case_ret -+ ], !prof !1 -+ -+case_a: -+ call void @a() -+ ret void -+ -+case_b: -+ call void @b() -+ ret void -+ -+case_ret: -+ ret void -+ -+unreachable: -+ unreachable -+} - - !0 = !{!"branch_weights", i32 1, i32 2, i32 3, i32 99, i32 5} - ;. - ; CHECK: [[PROF0]] = !{!"branch_weights", i32 5, i32 2, i32 3, i32 99} - ;. -+!1 = !{!"branch_weights", i32 11, i32 12, i32 13, i32 14, i32 15} -+;. -+; CHECK: [[PROF1]] = !{!"branch_weights", i32 14, i32 12, i32 13} -+;. diff --git a/22-185922.patch b/22-185922.patch deleted file mode 100644 index 4513df1..0000000 --- a/22-185922.patch +++ /dev/null @@ -1,55 +0,0 @@ -From ccf0ee68b86f65a6a4e83756f717faad7c779cb1 Mon Sep 17 00:00:00 2001 -From: Nikita Popov -Date: Wed, 11 Mar 2026 18:03:05 +0100 -Subject: [PATCH] [SystemZ] Limit depth of findCCUse() - -The recursion here has potentially exponential complexity. Avoid -this by limiting the depth of recursion. - -An alternative would be to memoize the results. I went with the -simpler depth limit on the assumption that we don't particularly -care about very deep value chains here. ---- - llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 13 +++++++++---- - 1 file changed, 9 insertions(+), 4 deletions(-) - -diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp -index 2a9cb903f3921..84d66f88a812d 100644 ---- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp -+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp -@@ -8692,7 +8692,12 @@ SDValue SystemZTargetLowering::combineSETCC( - return SDValue(); - } - --static std::pair findCCUse(const SDValue &Val) { -+static std::pair findCCUse(const SDValue &Val, -+ unsigned Depth = 0) { -+ // Limit depth of potentially exponential walk. -+ if (Depth > 5) -+ return std::make_pair(SDValue(), SystemZ::CCMASK_NONE); -+ - switch (Val.getOpcode()) { - default: - return std::make_pair(SDValue(), SystemZ::CCMASK_NONE); -@@ -8705,7 +8710,7 @@ static std::pair findCCUse(const SDValue &Val) { - SDValue Op4CCReg = Val.getOperand(4); - if (Op4CCReg.getOpcode() == SystemZISD::ICMP || - Op4CCReg.getOpcode() == SystemZISD::TM) { -- auto [OpCC, OpCCValid] = findCCUse(Op4CCReg.getOperand(0)); -+ auto [OpCC, OpCCValid] = findCCUse(Op4CCReg.getOperand(0), Depth + 1); - if (OpCC != SDValue()) - return std::make_pair(OpCC, OpCCValid); - } -@@ -8722,10 +8727,10 @@ static std::pair findCCUse(const SDValue &Val) { - case ISD::SHL: - case ISD::SRA: - case ISD::SRL: -- auto [Op0CC, Op0CCValid] = findCCUse(Val.getOperand(0)); -+ auto [Op0CC, Op0CCValid] = findCCUse(Val.getOperand(0), Depth + 1); - if (Op0CC != SDValue()) - return std::make_pair(Op0CC, Op0CCValid); -- return findCCUse(Val.getOperand(1)); -+ return findCCUse(Val.getOperand(1), Depth + 1); - } - } - diff --git a/22-190701.patch b/22-190701.patch deleted file mode 100644 index 51c3246..0000000 --- a/22-190701.patch +++ /dev/null @@ -1,87 +0,0 @@ -From 3915d1efcdb1e9d10c8f6966acbe5c359d824ba1 Mon Sep 17 00:00:00 2001 -From: Josh Stone -Date: Mon, 6 Apr 2026 14:08:10 -0700 -Subject: [PATCH] [CodeGen] Preserve big-endian trunc in concat_vectors - -A transform from `concat_vectors(trunc(scalar), undef)` to -`scalar_to_vector(scalar)` is only equivalent for little-endian targets. -On big-endian, that would put the extra upper bytes ahead of the desired -truncated bytes. This problem was seen on Rust s390x in [RHEL-147748]. - -[RHEL-147748]: https://redhat.atlassian.net/browse/RHEL-147748 - -Assisted-by: Claude Code ---- - llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 +- - llvm/test/CodeGen/SystemZ/vec-trunc-to-i16.ll | 45 +++++++++++++++++++ - 2 files changed, 48 insertions(+), 1 deletion(-) - create mode 100644 llvm/test/CodeGen/SystemZ/vec-trunc-to-i16.ll - -diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp -index 383e45c5ea3a8..5485ee86251a5 100644 ---- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp -+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp -@@ -26513,9 +26513,11 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { - // If the bitcast type isn't legal, it might be a trunc of a legal type; - // look through the trunc so we can still do the transform: - // concat_vectors(trunc(scalar), undef) -> scalar_to_vector(scalar) -+ // However, this is only equivalent on little-endian targets. - if (Scalar->getOpcode() == ISD::TRUNCATE && - !TLI.isTypeLegal(Scalar.getValueType()) && -- TLI.isTypeLegal(Scalar->getOperand(0).getValueType())) -+ TLI.isTypeLegal(Scalar->getOperand(0).getValueType()) && -+ DAG.getDataLayout().isLittleEndian()) - Scalar = Scalar->getOperand(0); - - EVT SclTy = Scalar.getValueType(); -diff --git a/llvm/test/CodeGen/SystemZ/vec-trunc-to-i16.ll b/llvm/test/CodeGen/SystemZ/vec-trunc-to-i16.ll -new file mode 100644 -index 0000000000000..42d787d945145 ---- /dev/null -+++ b/llvm/test/CodeGen/SystemZ/vec-trunc-to-i16.ll -@@ -0,0 +1,45 @@ -+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -+ -+; Test that truncated scalars use the correct vector insert instruction. -+; On big-endian targets, concat_vectors should not skip truncates when -+; creating scalar_to_vector, as the bytes would be in the wrong position. -+ -+; This truncated i16 should use vlvgh (insert halfword), not vlvgf (insert fullword). -+define <16 x i8> @test_concat_trunc_i16(i32 %x) { -+; CHECK-LABEL: test_concat_trunc_i16: -+; CHECK: # %bb.0: -+; CHECK-NEXT: vlvgh %v24, %r2, 0 -+; CHECK-NEXT: br %r14 -+ %t = trunc i32 %x to i16 -+ %vec = bitcast i16 %t to <2 x i8> -+ %result = shufflevector <2 x i8> %vec, <2 x i8> poison, <16 x i32> -+ ret <16 x i8> %result -+} -+ -+; Test with a more complex shuffle pattern, reduced from a Rust bug report. -+define fastcc void @test_shuffle_with_trunc() { -+; CHECK-LABEL: test_shuffle_with_trunc: -+; CHECK: # %bb.0: -+; CHECK-NEXT: lh %r1, 0 -+; CHECK-NEXT: l %r0, 0 -+; CHECK-NEXT: vlvgh %v1, %r1, 0 -+; CHECK-NEXT: larl %r1, .LCPI1_0 -+; CHECK-NEXT: vl %v2, 0(%r1), 3 -+; CHECK-NEXT: vlvgf %v0, %r0, 0 -+; CHECK-NEXT: vperm %v0, %v0, %v1, %v2 -+; CHECK-NEXT: vst %v0, 0, 3 -+; CHECK-NEXT: br %r14 -+ %1 = load i32, ptr null, align 8 -+ %2 = load i16, ptr null, align 1 -+ br label %3 -+ -+3: -+ %4 = bitcast i32 %1 to <4 x i8> -+ %5 = shufflevector <4 x i8> %4, <4 x i8> zeroinitializer, <16 x i32> -+ %6 = bitcast i16 %2 to <2 x i8> -+ %7 = shufflevector <2 x i8> %6, <2 x i8> zeroinitializer, <16 x i32> -+ %8 = shufflevector <16 x i8> %5, <16 x i8> %7, <16 x i32> -+ store <16 x i8> %8, ptr null, align 8 -+ ret void -+} diff --git a/changelog b/changelog index 8d60930..6d462fc 100644 --- a/changelog +++ b/changelog @@ -1,3 +1,6 @@ +* Thu Jun 25 2026 Nikita Popov - 22.1.8-1 +- Update to LLVM 22.1.8 + * Wed Apr 22 2026 Nikita Popov - 22.1.3-1 - Update to LLVM 22.1.3 diff --git a/llvm.spec b/llvm.spec index 6cd9957..c2b60f6 100644 --- a/llvm.spec +++ b/llvm.spec @@ -2,7 +2,7 @@ #region version %global maj_ver 22 %global min_ver 1 -%global patch_ver 3 +%global patch_ver 8 #global rc_ver rc3 %bcond_with snapshot_build @@ -42,7 +42,7 @@ %bcond_with compat_build # Bundle compat libraries for a previous LLVM version, as part of llvm-libs and # clang-libs. Used on RHEL. -%bcond_without bundle_compat_lib +%bcond_with bundle_compat_lib %bcond_without check %if %{with bundle_compat_lib} @@ -57,6 +57,14 @@ %bcond_without python_lit %endif +%if %{maj_ver} >= 23 +%global build_docs 0 +%global build_docs_toggle OFF +%else +%global build_docs 1 +%global build_docs_toggle ON +%endif + %bcond_without lldb %ifarch ppc64le @@ -209,15 +217,16 @@ end %endif %endif -# Historically, LLD was used used at the same combinations that enabled PGO. -# If this changes, we need to update the following lines. -# However, we should be able to link using LLD even if PGO is disabled. -# Reminder: RHEL8 still builds with gcc + ld.bfd. -%if %{with pgo} -%bcond_without use_lld -%else + +%if 0%{?rhel} == 8 # RHEL8 still builds with gcc + ld.bfd. %bcond_with use_lld +%else +%bcond_without use_lld +%endif + +%if %{with pgo} && %{without use_lld} +%{error:PGO requires --with=lld} %endif # For PGO Disable LTO for now because of LLVMgold.so not found error @@ -263,6 +272,12 @@ end %bcond_without libedit %endif +%if %{defined rhel} && 0%{?rhel} >= 10 +%bcond_with multilib +%else +%bcond_without multilib +%endif + # Opt out of https://fedoraproject.org/wiki/Changes/fno-omit-frame-pointer # https://bugzilla.redhat.com/show_bug.cgi?id=2158587 %undefine _include_frame_pointers @@ -279,8 +294,10 @@ end # Suffixless tarball name (essentially: basename -s .tar.xz llvm-project-17.0.6.src.tar.xz) %if %{with snapshot_build} %global src_tarball_dir llvm-project-%{llvm_snapshot_git_revision} +%global src_manpage_tarball_dir llvm_man_pages-%{llvm_snapshot_yyyymmdd} %else %global src_tarball_dir llvm-project-%{maj_ver}.%{min_ver}.%{patch_ver}%{?rc_ver:-%{rc_ver}}.src +%global src_manpage_tarball_dir llvm_man_pages-%{maj_ver}.%{min_ver}.%{patch_ver} %endif # LLD uses "fast" as the algortithm for generating build-id @@ -437,9 +454,15 @@ URL: http://llvm.org %if %{with snapshot_build} Source0: https://github.com/llvm/llvm-project/archive/%{llvm_snapshot_git_revision}.tar.gz +%if %{build_docs} == 0 +Source42: https://github.com/fedora-llvm-team/llvm-snapshots/releases/download/snapshot-version-sync/%{src_manpage_tarball_dir}.tar.xz +%endif %else Source0: https://github.com/llvm/llvm-project/releases/download/llvmorg-%{maj_ver}.%{min_ver}.%{patch_ver}%{?rc_ver:-%{rc_ver}}/%{src_tarball_dir}.tar.xz Source1: https://github.com/llvm/llvm-project/releases/download/llvmorg-%{maj_ver}.%{min_ver}.%{patch_ver}%{?rc_ver:-%{rc_ver}}/%{src_tarball_dir}.tar.xz.sig +%if %{build_docs} == 0 +Source42: https://github.com/llvm/llvm-project/releases/download/llvmorg-%{maj_ver}.%{min_ver}.%{patch_ver}%{?rc_ver:-%{rc_ver}}/%{src_manpage_tarball_dir}.tar.xz +%endif %endif Source6: release-keys.asc @@ -501,6 +524,12 @@ Patch103: 0001-Workaround-a-bug-in-ORC-on-ppc64le.patch Patch104: 0001-Driver-Give-devtoolset-path-precedence-over-Installe.patch #endregion CLANG patches +# Fix lit tests for Python 3.15+ https://bugzilla.redhat.com/show_bug.cgi?id=2448969 +Patch2209: https://github.com/llvm/llvm-project/commit/0b6a1ef429.patch + +# s390x fix for unaligned memory access performance regressions. +Patch2210: 0001-SystemZ-Avoid-unaligned-VL-VST-s-with-memcpy-memmove.patch + #region LLD patches Patch106: 0001-19-Always-build-shared-libs-for-LLD.patch Patch2103: 0001-lld-Adjust-compressed-debug-level-test-for-s390x-wit.patch @@ -539,9 +568,6 @@ Patch2105: 43cb4631c1f42dbfce78288b8ae30b5840ed59b3.patch # Fix for s390x vector miscompilation (rhbz#2430017) Patch2106: 0001-SystemZ-Fix-code-in-widening-vector-multiplication-1.patch -# Fix for s390x vector miscompilation (RHEL-147748) -Patch2203: 22-190701.patch - %if 0%{?rhel} == 8 %global python3_pkgversion 3.12 %global __python3 /usr/bin/python3.12 @@ -591,20 +617,22 @@ BuildRequires: lld %endif %endif +%if %{build_docs} # This intentionally does not use python3_pkgversion. RHEL 8 does not have # python3.12-sphinx, and we are only using it as a binary anyway. BuildRequires: python3-sphinx -%if 0%{?rhel} != 8 -# RHEL 8 does not have these packages for python3.12. However, they are only -# needed for LLDB tests. -BuildRequires: python%{python3_pkgversion}-psutil -BuildRequires: python%{python3_pkgversion}-pexpect %endif -%if %{undefined rhel} +%if 0%{?rhel} != 8 +# RHEL 8 does not have these packages for python3.12. +BuildRequires: python%{python3_pkgversion}-psutil +%endif +%if %{undefined rhel} && %{build_docs} BuildRequires: python%{python3_pkgversion}-myst-parser %endif # Needed for %%multilib_fix_c_header +%if %{with multilib} BuildRequires: multilib-rpm-config +%endif %if %{with gold} BuildRequires: binutils-devel %if %{undefined rhel} || 0%{?rhel} > 8 @@ -925,7 +953,7 @@ Development header files for clang tools. %package -n git-clang-format%{pkg_suffix} Summary: Integration of clang-format for git Requires: %{pkg_name_clang}-tools-extra = %{version}-%{release} -Requires: git +Requires: git-core Requires: python%{python3_pkgversion} %description -n git-clang-format%{pkg_suffix} @@ -1055,6 +1083,9 @@ License: Apache-2.0 WITH LLVM-exception OR NCSA URL: http://lldb.llvm.org/ Requires: %{pkg_name_clang}-libs%{?_isa} = %{version}-%{release} +%if 0%{?fedora} >= 45 +Recommends: yama-ptrace-enable +%endif %if %{without compat_build} Requires: python%{python3_pkgversion}-lldb %endif @@ -1325,8 +1356,9 @@ targets is welcome. Summary: Spirv subset of %{name} %description -n %{pkg_name_libclc}-spirv -The %{pkg_name_libclc}-spirv package contains the spirv*-mesa3d-.spv files only, -which are the subset required for upstream Mesa OpenCL support with RustiCL. +The %{pkg_name_libclc}-spirv package contains the spirv32-unknown-unknown/libclc.spv and +spirv64-unknown-unknown/libclc.spv files only, which are the subset required for upstream +Mesa OpenCL support with RustiCL. %endif #endregion libclc packages @@ -1359,6 +1391,11 @@ which are the subset required for upstream Mesa OpenCL support with RustiCL. %endif +# Unpack the man pages first +%if %{build_docs} == 0 +%autosetup -N -T -b 42 -n %{src_manpage_tarball_dir} +%endif + # -T : Do Not Perform Default Archive Unpacking (without this, the th source would be unpacked twice) # -b : Unpack The nth Sources Before Changing Directory # -n : Set Name of Build Directory @@ -1409,10 +1446,12 @@ which are the subset required for upstream Mesa OpenCL support with RustiCL. #endregion COMPILER-RT preparation #region lldb preparation +%if %{build_docs} # Compat builds don't build python bindings, but should still build man pages. %if %{with compat_build} sed -i 's/LLDB_ENABLE_PYTHON/TRUE/' lldb/docs/CMakeLists.txt %endif +%endif #endregion #region libcxx preparation @@ -1454,6 +1493,8 @@ cd llvm/utils/lit %global projects clang;clang-tools-extra;lld %global runtimes compiler-rt;openmp +%global runtime_targets default + %if %{with lldb} %global projects %{projects};lldb %endif @@ -1481,10 +1522,15 @@ cd llvm/utils/lit %if %{with offload} %global runtimes %{runtimes};offload +%global runtime_targets %{runtime_targets};amdgcn-amd-amdhsa +%endif + +%if %{with libclc} || %{with offload} +%global runtime_targets %{runtime_targets};nvptx64-nvidia-cuda %endif %if %{with libclc} -%global runtimes %{runtimes};libclc +%global runtime_targets %{runtime_targets};spirv32-unknown-unknown;spirv64-unknown-unknown;amdgcn-amd-amdhsa-llvm %endif %global gcc_triple --gcc-triple=%{_target_cpu}-redhat-linux @@ -1602,7 +1648,7 @@ CLANG_LDFLAGS=$(strip_specs "$LDFLAGS $CLANG_LDFLAGS_EXTRA") -DCLANG_DEFAULT_UNWINDLIB=libgcc \\\ -DCLANG_ENABLE_ARCMT:BOOL=ON \\\ -DCLANG_ENABLE_STATIC_ANALYZER:BOOL=ON \\\ - -DCLANG_INCLUDE_DOCS:BOOL=ON \\\ + -DCLANG_INCLUDE_DOCS:BOOL=%{build_docs_toggle} \\\ -DCLANG_INCLUDE_TESTS:BOOL=ON \\\ -DCLANG_PLUGIN_SUPPORT:BOOL=ON \\\ -DCLANG_REPOSITORY_STRING="%{?dist_vendor} %{version}-%{release}" \\\ @@ -1629,15 +1675,15 @@ CLANG_LDFLAGS=$(strip_specs "$LDFLAGS $CLANG_LDFLAGS_EXTRA") # Add all *enabled* documentation targets (no doxygen but sphinx) %global cmake_config_args %{cmake_config_args} \\\ -DLLVM_ENABLE_DOXYGEN:BOOL=OFF \\\ - -DLLVM_ENABLE_SPHINX:BOOL=ON \\\ - -DLLVM_BUILD_DOCS:BOOL=ON + -DLLVM_ENABLE_SPHINX:BOOL=%{build_docs_toggle} \\\ + -DLLVM_BUILD_DOCS:BOOL=%{build_docs_toggle} # Configure sphinx: # Build man-pages but no HTML docs using sphinx %global cmake_config_args %{cmake_config_args} \\\ -DSPHINX_EXECUTABLE=/usr/bin/sphinx-build-3 \\\ -DSPHINX_OUTPUT_HTML:BOOL=OFF \\\ - -DSPHINX_OUTPUT_MAN:BOOL=ON \\\ + -DSPHINX_OUTPUT_MAN:BOOL=%{build_docs_toggle} \\\ -DSPHINX_WARNINGS_AS_ERRORS=OFF #endregion docs options @@ -1649,11 +1695,7 @@ CLANG_LDFLAGS=$(strip_specs "$LDFLAGS $CLANG_LDFLAGS_EXTRA") %ifarch ppc64le %global cmake_config_args %{cmake_config_args} -DLLDB_TEST_USER_ARGS=--skip-category=watchpoint %endif -%if 0%{?rhel} == 8 - %global cmake_config_args %{cmake_config_args} -DLLDB_INCLUDE_TESTS:BOOL=OFF -%else - %global cmake_config_args %{cmake_config_args} -DLLDB_ENFORCE_STRICT_TEST_REQUIREMENTS:BOOL=ON -%endif +%global cmake_config_args %{cmake_config_args} -DLLDB_INCLUDE_TESTS:BOOL=OFF %endif #endregion lldb options @@ -1715,7 +1757,7 @@ CLANG_LDFLAGS=$(strip_specs "$LDFLAGS $CLANG_LDFLAGS_EXTRA") #region mlir options %if %{with mlir} %global cmake_config_args %{cmake_config_args} \\\ - -DMLIR_INCLUDE_DOCS:BOOL=ON \\\ + -DMLIR_INCLUDE_DOCS:BOOL=%{build_docs_toggle} \\\ -DMLIR_INCLUDE_TESTS:BOOL=ON \\\ -DMLIR_INCLUDE_INTEGRATION_TESTS:BOOL=OFF \\\ -DMLIR_INSTALL_AGGREGATE_OBJECTS=OFF \\\ @@ -1734,11 +1776,17 @@ CLANG_LDFLAGS=$(strip_specs "$LDFLAGS $CLANG_LDFLAGS_EXTRA") # We reset the cxxflags to "" here because this is compiling for a GPU # target, where our cflags are either questionable or actively wrong. %global cmake_config_args %{cmake_config_args} \\\ - -DLLVM_RUNTIME_TARGETS='default;amdgcn-amd-amdhsa;nvptx64-nvidia-cuda' \\\ - -DRUNTIMES_nvptx64-nvidia-cuda_LLVM_ENABLE_RUNTIMES=openmp \\\ - -DRUNTIMES_amdgcn-amd-amdhsa_LLVM_ENABLE_RUNTIMES=openmp \\\ - -DRUNTIMES_amdgcn-amd-amdhsa_CMAKE_CXX_FLAGS="" \\\ - -DRUNTIMES_nvptx64-nvidia-cuda_CMAKE_CXX_FLAGS="" + -DRUNTIMES_amdgcn-amd-amdhsa_CMAKE_CXX_FLAGS="" \\\ + -DRUNTIMES_nvptx64-nvidia-cuda_CMAKE_CXX_FLAGS="" \\\ + -DRUNTIMES_amdgcn-amd-amdhsa_CMAKE_EXE_LINKER_FLAGS="" \\\ + -DRUNTIMES_nvptx64-nvidia-cuda_CMAKE_EXE_LINKER_FLAGS="" \\\ + -DRUNTIMES_amdgcn-amd-amdhsa_CMAKE_SHARED_LINKER_FLAGS="" \\\ + -DRUNTIMES_nvptx64-nvidia-cuda_CMAKE_SHARED_LINKER_FLAGS="" \\\ + -DRUNTIMES_amdgcn-amd-amdhsa_CMAKE_MODULE_LINKER_FLAGS="" \\\ + -DRUNTIMES_nvptx64-nvidia-cuda_CMAKE_MODULE_LINKER_FLAGS="" \\\ + -DRUNTIMES_amdgcn-amd-amdhsa_CMAKE_STATIC_LINKER_FLAGS="" \\\ + -DRUNTIMES_nvptx64-nvidia-cuda_CMAKE_STATIC_LINKER_FLAGS="" \\\ + -DRUNTIMES_amdgcn-amd-amdhsa_LLVM_ENABLE_RUNTIMES="openmp" %if 0%{?__isa_bits} == 64 # The following shouldn't be required, but due to a bug, we have to be @@ -1761,7 +1809,7 @@ CLANG_LDFLAGS=$(strip_specs "$LDFLAGS $CLANG_LDFLAGS_EXTRA") #region flang options %if %{with flang} %global cmake_config_args %{cmake_config_args} \\\ - -DFLANG_INCLUDE_DOCS:BOOL=ON + -DFLANG_INCLUDE_DOCS:BOOL=%{build_docs_toggle} # Build both, shared and static flang runtime objects. # See also https://llvm.org/devmtg/2025-04/slides/quick_talk/kruse_flang-rt.pdf %global cmake_config_args %{cmake_config_args} \\\ @@ -1777,12 +1825,31 @@ CLANG_LDFLAGS=$(strip_specs "$LDFLAGS $CLANG_LDFLAGS_EXTRA") #region libclc options %if %{with libclc} -# Build SPIR-V targets with the SPIR-V backend. + +# Build SPIR-V targets with the SPIR-V backend, reset CXX flags and build libclc +# runtime %global cmake_config_args %{cmake_config_args} \\\ - -DLIBCLC_USE_SPIRV_BACKEND:BOOL=ON + -DRUNTIMES_spirv32-unknown-unknown_LIBCLC_USE_SPIRV_BACKEND:BOOL=ON \\\ + -DRUNTIMES_spirv64-unknown-unknown_LIBCLC_USE_SPIRV_BACKEND:BOOL=ON \\\ + -DRUNTIMES_spirv32-unknown-unknown_CMAKE_CXX_FLAGS="" \\\ + -DRUNTIMES_spirv64-unknown-unknown_CMAKE_CXX_FLAGS="" \\\ + -DRUNTIMES_amdgcn-amd-amdhsa-llvm_CMAKE_CXX_FLAGS="" \\\ + -DRUNTIMES_spirv32-unknown-unknown_LLVM_ENABLE_RUNTIMES="libclc" \\\ + -DRUNTIMES_spirv64-unknown-unknown_LLVM_ENABLE_RUNTIMES="libclc" \\\ + -DRUNTIMES_amdgcn-amd-amdhsa-llvm_LLVM_ENABLE_RUNTIMES="libclc" %endif #endregion libclc options +%if %{with offload} || %{with libclc} +# For the NVIDIA triple we potentially build both, openmp and libclc +%global combined_runtimes %{?with_offload:openmp%{?with_libclc:;}}%{?with_libclc:libclc} +%global cmake_config_args %{cmake_config_args} \\\ + -DRUNTIMES_nvptx64-nvidia-cuda_LLVM_ENABLE_RUNTIMES="%{combined_runtimes}" + +%global cmake_config_args %{cmake_config_args} \\\ + -DLLVM_RUNTIME_TARGETS="%{runtime_targets}" +%endif + #region test options %global cmake_config_args %{cmake_config_args} \\\ -DLLVM_BUILD_TESTS:BOOL=ON \\\ @@ -2108,7 +2175,9 @@ install %{build_libdir}/libLLVMTestingSupport.a %{buildroot}%{install_libdir} install %{build_libdir}/libLLVMTestingAnnotations.a %{buildroot}%{install_libdir} # Fix multi-lib +%if %{with multilib} %multilib_fix_c_header --file %{install_includedir}/llvm/Config/llvm-config.h +%endif %if %{without compat_build} @@ -2221,7 +2290,9 @@ ln -s clang-%{maj_ver}.1 %{buildroot}%{install_mandir}/man1/clang++.1 chmod a+x %{buildroot}%{install_datadir}/scan-view/{Reporter.py,startfile.py} # multilib fix +%if %{with multilib} %multilib_fix_c_header --file %{install_includedir}/clang/Config/config.h +%endif # remove editor integrations (bbedit, sublime, emacs, vim) rm -vf %{buildroot}%{install_datadir}/clang/clang-format-bbedit.applescript @@ -2305,13 +2376,17 @@ rm %{buildroot}%{install_bindir}/llvm-omp-kernel-replay touch %{buildroot}%{_bindir}/ld %endif +%if %{build_docs} install -D -m 644 -t %{buildroot}%{install_mandir}/man1/ lld/docs/ld.lld.1 +%endif #endregion LLD installation #region LLDB installation %if %{with lldb} +%if %{with multilib} %multilib_fix_c_header --file %{install_includedir}/lldb/Host/Config.h +%endif %if %{without compat_build} # Move python package out of llvm prefix. @@ -2378,7 +2453,14 @@ rm -v %{buildroot}%{install_libdir}/libFIRAnalysis.a \ %{buildroot}%{install_libdir}/libFIROpenACCTransforms.a \ %{buildroot}%{install_libdir}/libMIFDialect.a + +%if %{maj_ver} < 23 find %{buildroot}%{install_includedir}/flang -type f -a ! -iname '*.mod' -delete +%else +# Remove header files that are only needed for writing plugins. +# TODO: Maybe we should package these in the future. +rm -Rf %{buildroot}%{install_includedir}/flang +%endif # this is a test binary rm -v %{buildroot}%{install_bindir}/f18-parse-demo @@ -2431,6 +2513,21 @@ move_and_replace_with_symlinks() { -exec ln -s --relative "$dest/{}" "$src/{}" \;) } +%if %{build_docs} == 0 +# Install the man pages before the symlinks below are created +cp -v ../%{src_manpage_tarball_dir}/* %{buildroot}%{install_mandir}/man1/ +%if %{without flang} +rm %{buildroot}%{install_mandir}/man1/flang.1 +%endif +%if %{without polly} +rm %{buildroot}%{install_mandir}/man1/polly.1 +%endif +%if %{without lldb} +rm %{buildroot}%{install_mandir}/man1/lldb.1 +rm %{buildroot}%{install_mandir}/man1/lldb-server.1 +%endif +%endif + %if %{without compat_build} # Move files from the llvm prefix to the system prefix and replace them with # symlinks. We do it this way around because symlinks between multilib packages @@ -2614,6 +2711,13 @@ reset_test_opts %cmake_build --target check-lit #endregion Test LLVM lit +#region Test libclc +%if %{with libclc} +reset_test_opts +%cmake_build --target check-libclc +%endif +#endregion Test libclc + #region Test LLVM reset_test_opts # Xfail testing of update utility tools @@ -3189,6 +3293,7 @@ fi %if %{maj_ver} >= 23 %{expand_bins %{expand: llubi + llvm-extract-bundle-entry llvm-gpu-loader }} %else @@ -3259,6 +3364,7 @@ fi %if %{maj_ver} >= 23 %{expand_mans %{expand: llubi + llvm-extract-bundle-entry }} %else %{expand_mans %{expand: @@ -3369,12 +3475,6 @@ fi }} %{install_bindir}/clang-%{maj_ver} -%{_sysconfdir}/%{pkg_name_clang}/%{_target_platform}-clang.cfg -%{_sysconfdir}/%{pkg_name_clang}/%{_target_platform}-clang++.cfg -%ifarch x86_64 -%{_sysconfdir}/%{pkg_name_clang}/i386-redhat-linux-gnu-clang.cfg -%{_sysconfdir}/%{pkg_name_clang}/i386-redhat-linux-gnu-clang++.cfg -%endif %{expand_mans clang clang++} %if 0%{with pgo} @@ -3401,6 +3501,13 @@ fi %{_libdir}/libclang-cpp.so.%{compat_maj_ver}* %endif +%{_sysconfdir}/%{pkg_name_clang}/%{_target_platform}-clang.cfg +%{_sysconfdir}/%{pkg_name_clang}/%{_target_platform}-clang++.cfg +%ifarch x86_64 +%{_sysconfdir}/%{pkg_name_clang}/i386-redhat-linux-gnu-clang.cfg +%{_sysconfdir}/%{pkg_name_clang}/i386-redhat-linux-gnu-clang++.cfg +%endif + %files -n %{pkg_name_clang}-devel %license clang/LICENSE.TXT %{expand_libs %{expand: @@ -3488,6 +3595,7 @@ fi %if %{maj_ver} >= 23 %{expand_bins %{expand: + clang-ssaf-analyzer clang-ssaf-format clang-ssaf-linker }} @@ -3742,9 +3850,15 @@ fi flang-new }} %{install_bindir}/flang-%{maj_ver} + +%if %{maj_ver} < 23 %{expand_includes %{expand: flang/*.mod }} +%else +%{_prefix}/lib/clang/%{maj_ver}/finclude/flang/%{llvm_triple}/*.mod +%{_prefix}/lib/clang/%{maj_ver}/finclude/flang/%{llvm_triple}/omp_lib.h +%endif %{_sysconfdir}/%{pkg_name_clang}/%{_target_platform}-flang.cfg %ifarch x86_64 @@ -3767,17 +3881,17 @@ fi %license libclc/LICENSE.TXT %doc libclc/README.md libclc/CREDITS.TXT %{_prefix}/lib/clang/%{maj_ver}/lib/amdgcn-amd-amdhsa-llvm/libclc.bc -%{_prefix}/lib/clang/%{maj_ver}/lib/nvptx64--/libclc.bc -%{_prefix}/lib/clang/%{maj_ver}/lib/nvptx64--nvidiacl/libclc.bc +%{_prefix}/lib/clang/%{maj_ver}/lib/amdgcn-amd-amdhsa-llvm/libclc.a %{_prefix}/lib/clang/%{maj_ver}/lib/nvptx64-nvidia-cuda/libclc.bc -%{_prefix}/lib/clang/%{maj_ver}/lib/spir--/libclc.bc -%{_prefix}/lib/clang/%{maj_ver}/lib/spir64--/libclc.bc +%{_prefix}/lib/clang/%{maj_ver}/lib/nvptx64-nvidia-cuda/libclc.a %files -n %{pkg_name_libclc}-spirv %license libclc/LICENSE.TXT %doc libclc/README.md libclc/CREDITS.TXT -%{_prefix}/lib/clang/%{maj_ver}/lib/spirv32--/libclc.spv -%{_prefix}/lib/clang/%{maj_ver}/lib/spirv64--/libclc.spv +%{_prefix}/lib/clang/%{maj_ver}/lib/spirv32-unknown-unknown/libclc.spv +%{_prefix}/lib/clang/%{maj_ver}/lib/spirv32-unknown-unknown/libclc.a +%{_prefix}/lib/clang/%{maj_ver}/lib/spirv64-unknown-unknown/libclc.spv +%{_prefix}/lib/clang/%{maj_ver}/lib/spirv64-unknown-unknown/libclc.a %endif #endregion libclc files diff --git a/sources b/sources index 191f498..1b09eae 100644 --- a/sources +++ b/sources @@ -1,4 +1,2 @@ -SHA512 (llvm-project-22.1.3.src.tar.xz) = 3557a955d55471671ae2f7b9c809affd59a29a6fb1e70a2a5d040dc1c6376246deb0635be8ca36cae09112981760e9afb128c822e5554bd722589fb8dee3f0df -SHA512 (llvm-project-22.1.3.src.tar.xz.sig) = 153a0d174492a0facd061b5cfa3e18dbf946cc0c7d1fb50f4d961410d41cea1f355515fd3e892be676b8b34d61a21962c48acb90aa5d310d05cf6452053e52ad -SHA512 (llvm-project-21.1.8.src.tar.xz) = cae4c44e7bf678071723da63ad5839491d717a7233e7f4791aa408207f3ea42f52de939ad15189b112c02a0770f1bb8d59bae6ad31ef53417a6eea7770fe52ab -SHA512 (llvm-project-21.1.8.src.tar.xz.sig) = 10f58eff58ed6e701d0f123b15e68c82ab8cbdf99b1c86c0d83e3b8553e90ea51055e30327e8e442ded57c8f503e2a2de9ee075e9c28b5ba815a0f8922f8671c +SHA512 (llvm-project-22.1.8.src.tar.xz) = 2615b20ba08534f83ab8ecc7b5ba43b5f1dfcf9cdb2534a32fcdbf0ccdd9a008b46276e45ef26ed9377f65b5e4ae89ea798f3863fd034484b5715140f3a7b35c +SHA512 (llvm-project-22.1.8.src.tar.xz.sig) = 99a457b5b1fb409a5fe72b59ebd4ddae5cade3e5f2493e33b44d4f4b4625f7a1743f80106efb1134668842b15ea3400ce2c29263bec8ff986e05040910125e15