Workaround for GFX11.5 export priority (RHEL-49517)
Resolves: RHEL-49517
This commit is contained in:
Konrad Kleine
parent
7150d01ea6
commit
416ec7276b
893
99273.patch
Normal file
893
99273.patch
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@ -0,0 +1,893 @@
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From 91052169960477fbc39169c10f9fae3bec732510 Mon Sep 17 00:00:00 2001
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From: Carl Ritson <carl.ritson@amd.com>
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Date: Wed, 17 Jul 2024 15:07:42 +0900
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Subject: [PATCH 1/3] [AMDGPU] Implement workaround for GFX11.5 export priority
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On GFX11.5 shaders having completed exports need to execute/wait
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at a lower priority than shaders still executing exports.
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Add code to maintain normal priority of 2 for shaders that export
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and drop to priority 0 after exports.
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---
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llvm/lib/Target/AMDGPU/AMDGPU.td | 15 +-
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.../lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 112 ++++++
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llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h | 1 +
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llvm/lib/Target/AMDGPU/GCNSubtarget.h | 3 +
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.../AMDGPU/required-export-priority.ll | 344 ++++++++++++++++++
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.../AMDGPU/required-export-priority.mir | 293 +++++++++++++++
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6 files changed, 765 insertions(+), 3 deletions(-)
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create mode 100644 llvm/test/CodeGen/AMDGPU/required-export-priority.ll
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create mode 100644 llvm/test/CodeGen/AMDGPU/required-export-priority.mir
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diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
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index dfc8eaea66f7b..14fcf6a210a78 100644
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--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
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+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
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@@ -947,6 +947,12 @@ def FeatureHasRestrictedSOffset : SubtargetFeature<"restricted-soffset",
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"Has restricted SOffset (immediate not supported)."
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>;
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+def FeatureRequiredExportPriority : SubtargetFeature<"required-export-priority",
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+ "HasRequiredExportPriority",
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+ "true",
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+ "Export priority must be explicitly manipulated on GFX11.5"
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+>;
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+
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//===------------------------------------------------------------===//
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// Subtarget Features (options and debugging)
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//===------------------------------------------------------------===//
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@@ -1597,14 +1603,16 @@ def FeatureISAVersion11_5_0 : FeatureSet<
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!listconcat(FeatureISAVersion11_Common.Features,
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[FeatureSALUFloatInsts,
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FeatureDPPSrc1SGPR,
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- FeatureVGPRSingleUseHintInsts])>;
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+ FeatureVGPRSingleUseHintInsts,
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+ FeatureRequiredExportPriority])>;
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def FeatureISAVersion11_5_1 : FeatureSet<
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!listconcat(FeatureISAVersion11_Common.Features,
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[FeatureSALUFloatInsts,
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FeatureDPPSrc1SGPR,
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FeatureVGPRSingleUseHintInsts,
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- FeatureGFX11FullVGPRs])>;
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+ FeatureGFX11FullVGPRs,
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+ FeatureRequiredExportPriority])>;
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def FeatureISAVersion12 : FeatureSet<
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[FeatureGFX12,
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diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
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index a402fc6d7e611..a8b171aa82840 100644
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--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
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+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
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@@ -14,6 +14,7 @@
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#include "GCNSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIMachineFunctionInfo.h"
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+#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/TargetParser/TargetParser.h"
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@@ -1104,6 +1105,7 @@ void GCNHazardRecognizer::fixHazards(MachineInstr *MI) {
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fixWMMAHazards(MI);
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fixShift64HighRegBug(MI);
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fixVALUMaskWriteHazard(MI);
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+ fixRequiredExportPriority(MI);
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}
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bool GCNHazardRecognizer::fixVcmpxPermlaneHazards(MachineInstr *MI) {
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@@ -2895,3 +2897,113 @@ bool GCNHazardRecognizer::fixVALUMaskWriteHazard(MachineInstr *MI) {
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return true;
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}
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+
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+static bool ensureEntrySetPrio(MachineFunction *MF, int Priority,
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+ const SIInstrInfo &TII) {
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+ MachineBasicBlock &EntryMBB = MF->front();
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+ if (EntryMBB.begin() != EntryMBB.end()) {
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+ auto &EntryMI = *EntryMBB.begin();
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+ if (EntryMI.getOpcode() == AMDGPU::S_SETPRIO &&
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+ EntryMI.getOperand(0).getImm() >= Priority)
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+ return false;
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+ }
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+
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+ BuildMI(EntryMBB, EntryMBB.begin(), DebugLoc(), TII.get(AMDGPU::S_SETPRIO))
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+ .addImm(Priority);
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+ return true;
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+}
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+
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+bool GCNHazardRecognizer::fixRequiredExportPriority(MachineInstr *MI) {
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+ if (!ST.hasRequiredExportPriority())
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+ return false;
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+
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+ // Assume the following shader types will never have exports,
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+ // and avoid adding or adjusting S_SETPRIO.
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+ MachineBasicBlock *MBB = MI->getParent();
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+ MachineFunction *MF = MBB->getParent();
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+ auto CC = MF->getFunction().getCallingConv();
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+ switch (CC) {
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+ case CallingConv::AMDGPU_CS:
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+ case CallingConv::AMDGPU_CS_Chain:
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+ case CallingConv::AMDGPU_CS_ChainPreserve:
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+ case CallingConv::AMDGPU_KERNEL:
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+ return false;
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+ default:
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+ break;
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+ }
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+
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+ const int MaxPriority = 3;
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+ const int NormalPriority = 2;
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+ const int PostExportPriority = 0;
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+
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+ auto It = MI->getIterator();
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+ switch (MI->getOpcode()) {
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+ case AMDGPU::S_ENDPGM:
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+ case AMDGPU::S_ENDPGM_SAVED:
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+ case AMDGPU::S_ENDPGM_ORDERED_PS_DONE:
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+ case AMDGPU::SI_RETURN_TO_EPILOG:
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+ // Ensure shader with calls raises priority at entry.
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+ // This ensures correct priority if exports exist in callee.
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+ if (MF->getFrameInfo().hasCalls())
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+ return ensureEntrySetPrio(MF, NormalPriority, TII);
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+ return false;
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+ case AMDGPU::S_SETPRIO: {
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+ // Raise minimum priority unless in workaround.
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+ auto &PrioOp = MI->getOperand(0);
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+ int Prio = PrioOp.getImm();
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+ bool InWA = (Prio == PostExportPriority) &&
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+ (It != MBB->begin() && TII.isEXP(*std::prev(It)));
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+ if (InWA || Prio >= NormalPriority)
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+ return false;
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+ PrioOp.setImm(std::min(Prio + NormalPriority, MaxPriority));
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+ return true;
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+ }
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+ default:
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+ if (!TII.isEXP(*MI))
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+ return false;
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+ break;
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+ }
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+
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+ // Check entry priority at each export (as there will only be a few).
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+ // Note: amdgpu_gfx can only be a callee, so defer to caller setprio.
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+ bool Changed = false;
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+ if (CC != CallingConv::AMDGPU_Gfx)
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+ Changed = ensureEntrySetPrio(MF, NormalPriority, TII);
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+
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+ auto NextMI = std::next(It);
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+ bool EndOfShader = false;
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+ if (NextMI != MBB->end()) {
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+ // Only need WA at end of sequence of exports.
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+ if (TII.isEXP(*NextMI))
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+ return Changed;
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+ // Assume appropriate S_SETPRIO after export means WA already applied.
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+ if (NextMI->getOpcode() == AMDGPU::S_SETPRIO &&
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+ NextMI->getOperand(0).getImm() == PostExportPriority)
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+ return Changed;
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+ EndOfShader = NextMI->getOpcode() == AMDGPU::S_ENDPGM;
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+ }
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+
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+ const DebugLoc &DL = MI->getDebugLoc();
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+
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+ // Lower priority.
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+ BuildMI(*MBB, NextMI, DL, TII.get(AMDGPU::S_SETPRIO))
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+ .addImm(PostExportPriority);
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+
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+ if (!EndOfShader) {
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+ // Wait for exports to complete.
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+ BuildMI(*MBB, NextMI, DL, TII.get(AMDGPU::S_WAITCNT_EXPCNT))
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+ .addReg(AMDGPU::SGPR_NULL)
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+ .addImm(0);
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+ }
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+
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+ BuildMI(*MBB, NextMI, DL, TII.get(AMDGPU::S_NOP)).addImm(0);
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+ BuildMI(*MBB, NextMI, DL, TII.get(AMDGPU::S_NOP)).addImm(0);
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+
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+ if (!EndOfShader) {
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+ // Return to normal (higher) priority.
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+ BuildMI(*MBB, NextMI, DL, TII.get(AMDGPU::S_SETPRIO))
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+ .addImm(NormalPriority);
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+ }
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+
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+ return true;
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+}
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diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
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index 3ccca527c626b..f2a64ab48e180 100644
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--- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
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+++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
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@@ -107,6 +107,7 @@ class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
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bool fixWMMAHazards(MachineInstr *MI);
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bool fixShift64HighRegBug(MachineInstr *MI);
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bool fixVALUMaskWriteHazard(MachineInstr *MI);
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+ bool fixRequiredExportPriority(MachineInstr *MI);
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int checkMAIHazards(MachineInstr *MI);
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int checkMAIHazards908(MachineInstr *MI);
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diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
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index e5817594a4521..def89c785b855 100644
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--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
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+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
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@@ -238,6 +238,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
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bool HasVOPDInsts = false;
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bool HasVALUTransUseHazard = false;
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bool HasForceStoreSC0SC1 = false;
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+ bool HasRequiredExportPriority = false;
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// Dummy feature to use for assembler in tablegen.
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bool FeatureDisable = false;
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@@ -1282,6 +1283,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
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bool hasRestrictedSOffset() const { return HasRestrictedSOffset; }
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+ bool hasRequiredExportPriority() const { return HasRequiredExportPriority; }
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+
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/// \returns true if the target uses LOADcnt/SAMPLEcnt/BVHcnt, DScnt/KMcnt
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/// and STOREcnt rather than VMcnt, LGKMcnt and VScnt respectively.
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bool hasExtendedWaitCounts() const { return getGeneration() >= GFX12; }
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diff --git a/llvm/test/CodeGen/AMDGPU/required-export-priority.ll b/llvm/test/CodeGen/AMDGPU/required-export-priority.ll
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new file mode 100644
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index 0000000000000..377902f3f0d1a
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--- /dev/null
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+++ b/llvm/test/CodeGen/AMDGPU/required-export-priority.ll
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@@ -0,0 +1,344 @@
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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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+; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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+
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+define amdgpu_ps void @test_export_zeroes_f32() #0 {
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+; GCN-LABEL: test_export_zeroes_f32:
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+; GCN: ; %bb.0:
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+; GCN-NEXT: s_setprio 2
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+; GCN-NEXT: v_mov_b32_e32 v0, 0
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+; GCN-NEXT: exp mrt0 off, off, off, off
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+; GCN-NEXT: exp mrt0 off, off, off, off done
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+; GCN-NEXT: s_setprio 0
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+; GCN-NEXT: s_nop 0
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+; GCN-NEXT: s_nop 0
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+; GCN-NEXT: s_endpgm
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+ call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0, i1 false, i1 false)
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+ call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0, i1 true, i1 false)
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+ ret void
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+}
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+
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+define amdgpu_ps void @test_export_en_src0_f32() #0 {
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+; GCN-LABEL: test_export_en_src0_f32:
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+; GCN: ; %bb.0:
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+; GCN-NEXT: s_setprio 2
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+; GCN-NEXT: v_mov_b32_e32 v0, 4.0
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+; GCN-NEXT: v_mov_b32_e32 v1, 0.5
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+; GCN-NEXT: v_mov_b32_e32 v2, 2.0
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+; GCN-NEXT: v_mov_b32_e32 v3, 1.0
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+; GCN-NEXT: exp mrt0 v3, off, off, off done
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+; GCN-NEXT: s_setprio 0
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+; GCN-NEXT: s_nop 0
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+; GCN-NEXT: s_nop 0
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+; GCN-NEXT: s_endpgm
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+ call void @llvm.amdgcn.exp.f32(i32 0, i32 1, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)
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+ ret void
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+}
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+
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+define amdgpu_gs void @test_export_gs() #0 {
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+; GCN-LABEL: test_export_gs:
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+; GCN: ; %bb.0:
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+; GCN-NEXT: s_setprio 2
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+; GCN-NEXT: v_mov_b32_e32 v0, 4.0
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+; GCN-NEXT: v_mov_b32_e32 v1, 0.5
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+; GCN-NEXT: v_mov_b32_e32 v2, 2.0
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+; GCN-NEXT: v_mov_b32_e32 v3, 1.0
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+; GCN-NEXT: exp mrt0 off, v2, off, off done
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+; GCN-NEXT: s_setprio 0
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+; GCN-NEXT: s_nop 0
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+; GCN-NEXT: s_nop 0
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+; GCN-NEXT: s_endpgm
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+ call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)
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+ ret void
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+}
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+
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+define amdgpu_hs void @test_export_hs() #0 {
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+; GCN-LABEL: test_export_hs:
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+; GCN: ; %bb.0:
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+; GCN-NEXT: s_setprio 2
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+; GCN-NEXT: v_mov_b32_e32 v0, 4.0
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+; GCN-NEXT: v_mov_b32_e32 v1, 0.5
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+; GCN-NEXT: v_mov_b32_e32 v2, 2.0
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+; GCN-NEXT: v_mov_b32_e32 v3, 1.0
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+; GCN-NEXT: exp mrt0 off, v2, off, off done
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+; GCN-NEXT: s_setprio 0
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+; GCN-NEXT: s_nop 0
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+; GCN-NEXT: s_nop 0
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+; GCN-NEXT: s_endpgm
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+ call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)
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+ ret void
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+}
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+
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+define amdgpu_gfx void @test_export_gfx(float %v) #0 {
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+; GCN-LABEL: test_export_gfx:
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+; GCN: ; %bb.0:
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+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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+; GCN-NEXT: v_mov_b32_e32 v1, 4.0
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+; GCN-NEXT: v_mov_b32_e32 v2, 0.5
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+; GCN-NEXT: v_mov_b32_e32 v3, 2.0
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+; GCN-NEXT: exp mrt0 off, v3, off, off done
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+; GCN-NEXT: s_setprio 0
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+; GCN-NEXT: s_waitcnt_expcnt null, 0x0
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+; GCN-NEXT: s_nop 0
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+; GCN-NEXT: s_nop 0
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+; GCN-NEXT: s_setprio 2
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+; GCN-NEXT: s_waitcnt expcnt(0)
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+; GCN-NEXT: s_setpc_b64 s[30:31]
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+ call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float %v, float 2.0, float 0.5, float 4.0, i1 true, i1 false)
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+ ret void
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+}
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+
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+define amdgpu_cs void @test_export_cs() #0 {
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+; GCN-LABEL: test_export_cs:
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+; GCN: ; %bb.0:
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+; GCN-NEXT: v_mov_b32_e32 v0, 4.0
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+; GCN-NEXT: v_mov_b32_e32 v1, 0.5
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+; GCN-NEXT: v_mov_b32_e32 v2, 2.0
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+; GCN-NEXT: v_mov_b32_e32 v3, 1.0
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+; GCN-NEXT: exp mrt0 off, v2, off, off done
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+; GCN-NEXT: s_endpgm
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+ call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)
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+ ret void
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+}
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+
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+define amdgpu_kernel void @test_export_kernel() #0 {
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+; GCN-LABEL: test_export_kernel:
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+; GCN: ; %bb.0:
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+; GCN-NEXT: v_mov_b32_e32 v0, 4.0
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+; GCN-NEXT: v_mov_b32_e32 v1, 0.5
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+; GCN-NEXT: v_mov_b32_e32 v2, 2.0
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+; GCN-NEXT: v_mov_b32_e32 v3, 1.0
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+; GCN-NEXT: exp mrt0 off, v2, off, off done
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+; GCN-NEXT: s_endpgm
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+ call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false)
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+ ret void
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+}
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+
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+define amdgpu_gfx void @test_no_export_gfx(float %v) #0 {
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+; GCN-LABEL: test_no_export_gfx:
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+; GCN: ; %bb.0:
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+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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+; GCN-NEXT: s_setpc_b64 s[30:31]
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+ ret void
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+}
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+
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+define amdgpu_ps void @test_no_export_ps(float %v) #0 {
|
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+; GCN-LABEL: test_no_export_ps:
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||||
+; GCN: ; %bb.0:
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+; GCN-NEXT: s_endpgm
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+ ret void
|
||||
+}
|
||||
+
|
||||
+define amdgpu_ps void @test_if_export_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 {
|
||||
+; GCN-LABEL: test_if_export_f32:
|
||||
+; GCN: ; %bb.0:
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: s_mov_b32 s0, exec_lo
|
||||
+; GCN-NEXT: v_cmpx_ne_u32_e32 0, v0
|
||||
+; GCN-NEXT: s_cbranch_execz .LBB9_2
|
||||
+; GCN-NEXT: ; %bb.1: ; %exp
|
||||
+; GCN-NEXT: exp mrt0 v1, v2, v3, v4
|
||||
+; GCN-NEXT: s_setprio 0
|
||||
+; GCN-NEXT: s_waitcnt_expcnt null, 0x0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: .LBB9_2: ; %end
|
||||
+; GCN-NEXT: s_endpgm
|
||||
+ %cc = icmp eq i32 %flag, 0
|
||||
+ br i1 %cc, label %end, label %exp
|
||||
+
|
||||
+exp:
|
||||
+ call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 false, i1 false)
|
||||
+ br label %end
|
||||
+
|
||||
+end:
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+define amdgpu_ps void @test_if_export_vm_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 {
|
||||
+; GCN-LABEL: test_if_export_vm_f32:
|
||||
+; GCN: ; %bb.0:
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: s_mov_b32 s0, exec_lo
|
||||
+; GCN-NEXT: v_cmpx_ne_u32_e32 0, v0
|
||||
+; GCN-NEXT: s_cbranch_execz .LBB10_2
|
||||
+; GCN-NEXT: ; %bb.1: ; %exp
|
||||
+; GCN-NEXT: exp mrt0 v1, v2, v3, v4
|
||||
+; GCN-NEXT: s_setprio 0
|
||||
+; GCN-NEXT: s_waitcnt_expcnt null, 0x0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: .LBB10_2: ; %end
|
||||
+; GCN-NEXT: s_endpgm
|
||||
+ %cc = icmp eq i32 %flag, 0
|
||||
+ br i1 %cc, label %end, label %exp
|
||||
+
|
||||
+exp:
|
||||
+ call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 false, i1 true)
|
||||
+ br label %end
|
||||
+
|
||||
+end:
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+define amdgpu_ps void @test_if_export_done_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 {
|
||||
+; GCN-LABEL: test_if_export_done_f32:
|
||||
+; GCN: ; %bb.0:
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: s_mov_b32 s0, exec_lo
|
||||
+; GCN-NEXT: v_cmpx_ne_u32_e32 0, v0
|
||||
+; GCN-NEXT: s_cbranch_execz .LBB11_2
|
||||
+; GCN-NEXT: ; %bb.1: ; %exp
|
||||
+; GCN-NEXT: exp mrt0 v1, v2, v3, v4 done
|
||||
+; GCN-NEXT: s_setprio 0
|
||||
+; GCN-NEXT: s_waitcnt_expcnt null, 0x0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: .LBB11_2: ; %end
|
||||
+; GCN-NEXT: s_endpgm
|
||||
+ %cc = icmp eq i32 %flag, 0
|
||||
+ br i1 %cc, label %end, label %exp
|
||||
+
|
||||
+exp:
|
||||
+ call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 false)
|
||||
+ br label %end
|
||||
+
|
||||
+end:
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+define amdgpu_ps void @test_if_export_vm_done_f32(i32 %flag, float %x, float %y, float %z, float %w) #0 {
|
||||
+; GCN-LABEL: test_if_export_vm_done_f32:
|
||||
+; GCN: ; %bb.0:
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: s_mov_b32 s0, exec_lo
|
||||
+; GCN-NEXT: v_cmpx_ne_u32_e32 0, v0
|
||||
+; GCN-NEXT: s_cbranch_execz .LBB12_2
|
||||
+; GCN-NEXT: ; %bb.1: ; %exp
|
||||
+; GCN-NEXT: exp mrt0 v1, v2, v3, v4 done
|
||||
+; GCN-NEXT: s_setprio 0
|
||||
+; GCN-NEXT: s_waitcnt_expcnt null, 0x0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: .LBB12_2: ; %end
|
||||
+; GCN-NEXT: s_endpgm
|
||||
+ %cc = icmp eq i32 %flag, 0
|
||||
+ br i1 %cc, label %end, label %exp
|
||||
+
|
||||
+exp:
|
||||
+ call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 true)
|
||||
+ br label %end
|
||||
+
|
||||
+end:
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+define amdgpu_ps void @test_export_pos_before_param_across_load(i32 %idx) #0 {
|
||||
+; GCN-LABEL: test_export_pos_before_param_across_load:
|
||||
+; GCN: ; %bb.0:
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: buffer_load_b32 v0, v0, s[0:3], 0 offen
|
||||
+; GCN-NEXT: v_mov_b32_e32 v1, 0
|
||||
+; GCN-NEXT: v_mov_b32_e32 v2, 1.0
|
||||
+; GCN-NEXT: v_mov_b32_e32 v3, 0.5
|
||||
+; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
+; GCN-NEXT: exp pos0 v1, v1, v1, v0 done
|
||||
+; GCN-NEXT: exp invalid_target_32 v2, v2, v2, v2
|
||||
+; GCN-NEXT: exp invalid_target_33 v2, v2, v2, v3
|
||||
+; GCN-NEXT: s_setprio 0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_endpgm
|
||||
+ call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float 1.0, float 1.0, float 1.0, float 1.0, i1 false, i1 false)
|
||||
+ call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float 1.0, float 1.0, float 1.0, float 0.5, i1 false, i1 false)
|
||||
+ %load = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) undef, i32 %idx, i32 0, i32 0)
|
||||
+ call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float 0.0, float 0.0, float 0.0, float %load, i1 true, i1 false)
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+define amdgpu_ps void @test_export_across_store_load(i32 %idx, float %v) #0 {
|
||||
+; GCN-LABEL: test_export_across_store_load:
|
||||
+; GCN: ; %bb.0:
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: v_mov_b32_e32 v2, 24
|
||||
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
|
||||
+; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
||||
+; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 8, vcc_lo
|
||||
+; GCN-NEXT: v_mov_b32_e32 v2, 0
|
||||
+; GCN-NEXT: scratch_store_b32 v0, v1, off
|
||||
+; GCN-NEXT: scratch_load_b32 v0, off, off
|
||||
+; GCN-NEXT: v_mov_b32_e32 v1, 1.0
|
||||
+; GCN-NEXT: exp pos0 v2, v2, v2, v1 done
|
||||
+; GCN-NEXT: s_setprio 0
|
||||
+; GCN-NEXT: s_waitcnt_expcnt null, 0x0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
+; GCN-NEXT: exp invalid_target_32 v0, v2, v1, v2
|
||||
+; GCN-NEXT: exp invalid_target_33 v0, v2, v1, v2
|
||||
+; GCN-NEXT: s_setprio 0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_nop 0
|
||||
+; GCN-NEXT: s_endpgm
|
||||
+ %data0 = alloca <4 x float>, align 8, addrspace(5)
|
||||
+ %data1 = alloca <4 x float>, align 8, addrspace(5)
|
||||
+ %cmp = icmp eq i32 %idx, 1
|
||||
+ %data = select i1 %cmp, ptr addrspace(5) %data0, ptr addrspace(5) %data1
|
||||
+ store float %v, ptr addrspace(5) %data, align 8
|
||||
+ call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float 0.0, float 0.0, float 0.0, float 1.0, i1 true, i1 false)
|
||||
+ %load0 = load float, ptr addrspace(5) %data0, align 8
|
||||
+ call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %load0, float 0.0, float 1.0, float 0.0, i1 false, i1 false)
|
||||
+ call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %load0, float 0.0, float 1.0, float 0.0, i1 false, i1 false)
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+define amdgpu_ps void @test_export_in_callee(float %v) #0 {
|
||||
+; GCN-LABEL: test_export_in_callee:
|
||||
+; GCN: ; %bb.0:
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: s_getpc_b64 s[0:1]
|
||||
+; GCN-NEXT: s_add_u32 s0, s0, test_export_gfx@gotpcrel32@lo+4
|
||||
+; GCN-NEXT: s_addc_u32 s1, s1, test_export_gfx@gotpcrel32@hi+12
|
||||
+; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0
|
||||
+; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
|
||||
+; GCN-NEXT: s_mov_b32 s32, 0
|
||||
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
+; GCN-NEXT: s_swappc_b64 s[30:31], s[0:1]
|
||||
+; GCN-NEXT: s_endpgm
|
||||
+ %x = fadd float %v, 1.0
|
||||
+ call void @test_export_gfx(float %x)
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+define amdgpu_ps void @test_export_in_callee_prio(float %v) #0 {
|
||||
+; GCN-LABEL: test_export_in_callee_prio:
|
||||
+; GCN: ; %bb.0:
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: s_mov_b32 s32, 0
|
||||
+; GCN-NEXT: v_add_f32_e32 v0, 1.0, v0
|
||||
+; GCN-NEXT: s_setprio 2
|
||||
+; GCN-NEXT: s_getpc_b64 s[0:1]
|
||||
+; GCN-NEXT: s_add_u32 s0, s0, test_export_gfx@gotpcrel32@lo+4
|
||||
+; GCN-NEXT: s_addc_u32 s1, s1, test_export_gfx@gotpcrel32@hi+12
|
||||
+; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
|
||||
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
+; GCN-NEXT: s_swappc_b64 s[30:31], s[0:1]
|
||||
+; GCN-NEXT: s_endpgm
|
||||
+ %x = fadd float %v, 1.0
|
||||
+ call void @llvm.amdgcn.s.setprio(i16 0)
|
||||
+ call void @test_export_gfx(float %x)
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
+declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
|
||||
+declare void @llvm.amdgcn.exp.i32(i32, i32, i32, i32, i32, i32, i1, i1) #1
|
||||
+declare float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8), i32, i32, i32) #2
|
||||
+declare void @llvm.amdgcn.s.setprio(i16)
|
||||
+
|
||||
+attributes #0 = { nounwind }
|
||||
+attributes #1 = { nounwind inaccessiblememonly }
|
||||
+attributes #2 = { nounwind readnone }
|
||||
diff --git a/llvm/test/CodeGen/AMDGPU/required-export-priority.mir b/llvm/test/CodeGen/AMDGPU/required-export-priority.mir
|
||||
new file mode 100644
|
||||
index 0000000000000..eee04468036e5
|
||||
--- /dev/null
|
||||
+++ b/llvm/test/CodeGen/AMDGPU/required-export-priority.mir
|
||||
@@ -0,0 +1,293 @@
|
||||
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
|
||||
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -mattr=-wavefrontsize32,+wavefrontsize64 -run-pass=post-RA-hazard-rec -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX1150 %s
|
||||
+
|
||||
+--- |
|
||||
+ define amdgpu_ps void @end_of_shader() {
|
||||
+ ret void
|
||||
+ }
|
||||
+ define amdgpu_ps void @end_of_shader_return_to_epilogue() {
|
||||
+ ret void
|
||||
+ }
|
||||
+ define amdgpu_ps void @end_of_block() {
|
||||
+ ret void
|
||||
+ }
|
||||
+ define amdgpu_ps void @start_of_block() {
|
||||
+ ret void
|
||||
+ }
|
||||
+ define amdgpu_ps void @block_of_exports() {
|
||||
+ ret void
|
||||
+ }
|
||||
+ define amdgpu_ps void @sparse_exports() {
|
||||
+ ret void
|
||||
+ }
|
||||
+ define amdgpu_ps void @existing_setprio_1() {
|
||||
+ ret void
|
||||
+ }
|
||||
+ define amdgpu_ps void @existing_setprio_2() {
|
||||
+ ret void
|
||||
+ }
|
||||
+...
|
||||
+
|
||||
+---
|
||||
+name: end_of_shader
|
||||
+tracksRegLiveness: true
|
||||
+liveins:
|
||||
+ - { reg: '$vgpr0' }
|
||||
+body: |
|
||||
+ bb.0:
|
||||
+ liveins: $vgpr0
|
||||
+ ; GFX1150-LABEL: name: end_of_shader
|
||||
+ ; GFX1150: liveins: $vgpr0
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_ENDPGM 0
|
||||
+ EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ S_ENDPGM 0
|
||||
+...
|
||||
+
|
||||
+---
|
||||
+name: end_of_shader_return_to_epilogue
|
||||
+tracksRegLiveness: true
|
||||
+liveins:
|
||||
+ - { reg: '$vgpr0' }
|
||||
+body: |
|
||||
+ bb.0:
|
||||
+ liveins: $vgpr0
|
||||
+ ; GFX1150-LABEL: name: end_of_shader_return_to_epilogue
|
||||
+ ; GFX1150: liveins: $vgpr0
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 0
|
||||
+ ; GFX1150-NEXT: S_WAITCNT_EXPCNT $sgpr_null, 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: SI_RETURN_TO_EPILOG $vgpr0
|
||||
+ EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ SI_RETURN_TO_EPILOG $vgpr0
|
||||
+...
|
||||
+
|
||||
+---
|
||||
+name: end_of_block
|
||||
+tracksRegLiveness: true
|
||||
+liveins:
|
||||
+ - { reg: '$vgpr0' }
|
||||
+body: |
|
||||
+ ; GFX1150-LABEL: name: end_of_block
|
||||
+ ; GFX1150: bb.0:
|
||||
+ ; GFX1150-NEXT: successors: %bb.1(0x80000000)
|
||||
+ ; GFX1150-NEXT: liveins: $vgpr0
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 0
|
||||
+ ; GFX1150-NEXT: S_WAITCNT_EXPCNT $sgpr_null, 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: bb.1:
|
||||
+ ; GFX1150-NEXT: S_ENDPGM 0
|
||||
+ bb.0:
|
||||
+ liveins: $vgpr0
|
||||
+ EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+
|
||||
+ bb.1:
|
||||
+ S_ENDPGM 0
|
||||
+...
|
||||
+
|
||||
+---
|
||||
+name: start_of_block
|
||||
+tracksRegLiveness: true
|
||||
+liveins:
|
||||
+ - { reg: '$vgpr0' }
|
||||
+body: |
|
||||
+ ; GFX1150-LABEL: name: start_of_block
|
||||
+ ; GFX1150: bb.0:
|
||||
+ ; GFX1150-NEXT: successors: %bb.1(0x80000000)
|
||||
+ ; GFX1150-NEXT: liveins: $vgpr0
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: bb.1:
|
||||
+ ; GFX1150-NEXT: successors: %bb.2(0x80000000)
|
||||
+ ; GFX1150-NEXT: liveins: $vgpr0
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 0
|
||||
+ ; GFX1150-NEXT: S_WAITCNT_EXPCNT $sgpr_null, 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: bb.2:
|
||||
+ ; GFX1150-NEXT: S_ENDPGM 0
|
||||
+ bb.0:
|
||||
+ liveins: $vgpr0
|
||||
+
|
||||
+ bb.1:
|
||||
+ liveins: $vgpr0
|
||||
+ EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+
|
||||
+ bb.2:
|
||||
+ S_ENDPGM 0
|
||||
+...
|
||||
+
|
||||
+---
|
||||
+name: block_of_exports
|
||||
+tracksRegLiveness: true
|
||||
+liveins:
|
||||
+ - { reg: '$vgpr0' }
|
||||
+body: |
|
||||
+ bb.0:
|
||||
+ liveins: $vgpr0
|
||||
+ ; GFX1150-LABEL: name: block_of_exports
|
||||
+ ; GFX1150: liveins: $vgpr0
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: EXP 2, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: EXP 1, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_ENDPGM 0
|
||||
+ EXP 2, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ EXP 1, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ S_ENDPGM 0
|
||||
+...
|
||||
+
|
||||
+---
|
||||
+name: sparse_exports
|
||||
+tracksRegLiveness: true
|
||||
+liveins:
|
||||
+ - { reg: '$vgpr0' }
|
||||
+body: |
|
||||
+ bb.0:
|
||||
+ liveins: $vgpr0
|
||||
+ ; GFX1150-LABEL: name: sparse_exports
|
||||
+ ; GFX1150: liveins: $vgpr0
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: EXP 2, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 0
|
||||
+ ; GFX1150-NEXT: S_WAITCNT_EXPCNT $sgpr_null, 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: $vgpr0 = V_AND_B32_e32 1, $vgpr0, implicit $exec
|
||||
+ ; GFX1150-NEXT: EXP 1, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 0
|
||||
+ ; GFX1150-NEXT: S_WAITCNT_EXPCNT $sgpr_null, 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: $vgpr0 = V_OR_B32_e32 2, $vgpr0, implicit $exec
|
||||
+ ; GFX1150-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_ENDPGM 0
|
||||
+ EXP 2, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ $vgpr0 = V_AND_B32_e32 1, $vgpr0, implicit $exec
|
||||
+ EXP 1, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ $vgpr0 = V_OR_B32_e32 2, $vgpr0, implicit $exec
|
||||
+ EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ S_ENDPGM 0
|
||||
+...
|
||||
+
|
||||
+---
|
||||
+name: existing_setprio_1
|
||||
+tracksRegLiveness: true
|
||||
+liveins:
|
||||
+ - { reg: '$vgpr0' }
|
||||
+body: |
|
||||
+ ; GFX1150-LABEL: name: existing_setprio_1
|
||||
+ ; GFX1150: bb.0:
|
||||
+ ; GFX1150-NEXT: successors: %bb.1(0x80000000)
|
||||
+ ; GFX1150-NEXT: liveins: $vgpr0
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: $vgpr0 = V_AND_B32_e32 1, $vgpr0, implicit $exec
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: bb.1:
|
||||
+ ; GFX1150-NEXT: successors: %bb.2(0x80000000)
|
||||
+ ; GFX1150-NEXT: liveins: $vgpr0
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 3
|
||||
+ ; GFX1150-NEXT: $vgpr0 = V_OR_B32_e32 2, $vgpr0, implicit $exec
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: bb.2:
|
||||
+ ; GFX1150-NEXT: successors: %bb.3(0x80000000)
|
||||
+ ; GFX1150-NEXT: liveins: $vgpr0
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 3
|
||||
+ ; GFX1150-NEXT: $vgpr0 = V_OR_B32_e32 3, $vgpr0, implicit $exec
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: bb.3:
|
||||
+ ; GFX1150-NEXT: liveins: $vgpr0
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: EXP 1, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_ENDPGM 0
|
||||
+ bb.0:
|
||||
+ liveins: $vgpr0
|
||||
+ $vgpr0 = V_AND_B32_e32 1, $vgpr0, implicit $exec
|
||||
+
|
||||
+ bb.1:
|
||||
+ liveins: $vgpr0
|
||||
+ S_SETPRIO 3
|
||||
+ $vgpr0 = V_OR_B32_e32 2, $vgpr0, implicit $exec
|
||||
+ S_SETPRIO 0
|
||||
+
|
||||
+ bb.2:
|
||||
+ liveins: $vgpr0
|
||||
+ S_SETPRIO 1
|
||||
+ $vgpr0 = V_OR_B32_e32 3, $vgpr0, implicit $exec
|
||||
+ S_SETPRIO 0
|
||||
+
|
||||
+ bb.3:
|
||||
+ liveins: $vgpr0
|
||||
+ EXP 1, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ S_ENDPGM 0
|
||||
+...
|
||||
+
|
||||
+---
|
||||
+name: existing_setprio_2
|
||||
+tracksRegLiveness: true
|
||||
+liveins:
|
||||
+ - { reg: '$vgpr0' }
|
||||
+body: |
|
||||
+ bb.0:
|
||||
+ liveins: $vgpr0
|
||||
+ ; GFX1150-LABEL: name: existing_setprio_2
|
||||
+ ; GFX1150: liveins: $vgpr0
|
||||
+ ; GFX1150-NEXT: {{ $}}
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 3
|
||||
+ ; GFX1150-NEXT: EXP 1, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 0
|
||||
+ ; GFX1150-NEXT: S_WAITCNT_EXPCNT $sgpr_null, 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_NOP 0
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 2
|
||||
+ ; GFX1150-NEXT: S_SETPRIO 3
|
||||
+ ; GFX1150-NEXT: S_ENDPGM 0
|
||||
+ S_SETPRIO 3
|
||||
+ EXP 1, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ EXP_DONE 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
|
||||
+ S_SETPRIO 3
|
||||
+ S_ENDPGM 0
|
||||
+...
|
||||
|
||||
From 8ea44e65f2c19facff751aeb2ac960f907fb210f Mon Sep 17 00:00:00 2001
|
||||
From: Carl Ritson <carl.ritson@amd.com>
|
||||
Date: Wed, 17 Jul 2024 16:18:02 +0900
|
||||
Subject: [PATCH 2/3] Remove -verify-machineinstrs from test.
|
||||
|
||||
---
|
||||
llvm/test/CodeGen/AMDGPU/required-export-priority.ll | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/llvm/test/CodeGen/AMDGPU/required-export-priority.ll b/llvm/test/CodeGen/AMDGPU/required-export-priority.ll
|
||||
index 377902f3f0d1a..ebc209bd4d451 100644
|
||||
--- a/llvm/test/CodeGen/AMDGPU/required-export-priority.ll
|
||||
+++ b/llvm/test/CodeGen/AMDGPU/required-export-priority.ll
|
||||
@@ -1,5 +1,5 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
||||
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -amdgpu-enable-vopd=0 < %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
define amdgpu_ps void @test_export_zeroes_f32() #0 {
|
||||
; GCN-LABEL: test_export_zeroes_f32:
|
||||
10
llvm.spec
10
llvm.spec
@ -101,7 +101,7 @@
|
||||
|
||||
Name: %{pkg_name}
|
||||
Version: %{maj_ver}.%{min_ver}.%{patch_ver}%{?rc_ver:~rc%{rc_ver}}%{?llvm_snapshot_version_suffix:~%{llvm_snapshot_version_suffix}}
|
||||
Release: 2%{?dist}
|
||||
Release: 3%{?dist}
|
||||
Summary: The Low Level Virtual Machine
|
||||
|
||||
License: Apache-2.0 WITH LLVM-exception OR NCSA
|
||||
@ -126,6 +126,11 @@ Source8: https://github.com/llvm/llvm-project/releases/download/llvmorg-%{compat
|
||||
%endif
|
||||
%endif
|
||||
|
||||
# Backport with modifications from
|
||||
# https://github.com/llvm/llvm-project/pull/99273
|
||||
# Fixes RHEL-49517.
|
||||
Patch001: 99273.patch
|
||||
|
||||
# RHEL-specific patch to avoid unwanted python3-myst-parser dep
|
||||
Patch101: 0101-Deactivate-markdown-doc.patch
|
||||
|
||||
@ -653,6 +658,9 @@ fi
|
||||
%license LICENSE.TXT
|
||||
|
||||
%changelog
|
||||
* Thu Aug 15 2024 Konrad Kleine <kkleine@redhat.com> - 18.1.8-3
|
||||
- Workaround for GFX11.5 export priority (RHEL-49517)
|
||||
|
||||
* Thu Aug 08 2024 Konrad Kleine <kkleine@redhat.com> - 18.1.8-2
|
||||
- Remove llvm 17 compat lib
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user