From 861ce2a29b214ce182e105f428f55cdc2ed51af1 Mon Sep 17 00:00:00 2001 From: "Kotaro, Tokai" Date: Wed, 18 Jun 2025 12:01:43 +0900 Subject: [PATCH] The FUJITSU-MONAKA PMU events have been changed to match the v1.1 specification and v1.0 errata. FUJITSU-MONAKA Specification URL: https://github.com/fujitsu/FUJITSU-MONAKA The changed events are as follows: Removed events: - L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT Added events: - ASE_FP_VREDUCE_SPEC - SVE_FP_PREDUCE_SPEC - ASE_FP_BF16_MIN_SPEC - ASE_FP_FP8_MIN_SPEC - ASE_SVE_FP_BF16_MIN_SPEC - ASE_SVE_FP_FP8_MIN_SPEC - SVE_FP_BF16_MIN_SPEC - SVE_FP_FP8_MIN_SPEC - FP_BF16_MIN_SPEC - FP_FP8_MIN_SPEC - FP_BF16_FIXED_MIN_OPS_SPEC - FP_FP8_FIXED_MIN_OPS_SPEC - FP_BF16_SCALE_MIN_OPS_SPEC - FP_FP8_SCALE_MIN_OPS_SPEC Renamed events: - L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM => L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT - L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_RD => L2D_CACHE_REFILL_L3D_MISS_DM_RD_PFTGT_HIT - L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_WR => L2D_CACHE_REFILL_L3D_MISS_DM_WR_PFTGT_HIT - L2D_CACHE_REFILL_L3D_MISS_L_MEM => L2D_CACHE_REFILL_L3D_MISS_DM_L_MEM - L2D_CACHE_REFILL_L3D_MISS_FR_MEM => L2D_CACHE_REFILL_L3D_MISS_DM_FR_MEM - L2D_CACHE_REFILL_L3D_MISS_L_L2 => L2D_CACHE_REFILL_L3D_MISS_DM_L_L2 - L2D_CACHE_REFILL_L3D_MISS_NR_L2 => L2D_CACHE_REFILL_L3D_MISS_DM_NR_L2 - L2D_CACHE_REFILL_L3D_MISS_NR_L3 => L2D_CACHE_REFILL_L3D_MISS_DM_NR_L3 - L2D_CACHE_REFILL_L3D_MISS_FR_L2 => L2D_CACHE_REFILL_L3D_MISS_DM_FR_L2 - L2D_CACHE_REFILL_L3D_MISS_FR_L3 => L2D_CACHE_REFILL_L3D_MISS_DM_FR_L3 Description changed events: - STALL_BACKEND - LL_CACHE_MISS_RD - L2D_CACHE_RD - L2D_CACHE_WR - L2D_CACHE_REFILL_RD - L2D_CACHE_REFILL_WR - CSDB_SPEC - EXC_SMC - FP_MV_SPEC - IEL_SPEC - IREG_SPEC - BC_LD_SPEC - LD_COMP_WAIT - LD_COMP_WAIT_EX - L1_PIPE_COMP_GATHER_2FLOW - L1_PIPE_COMP_GATHER_1FLOW - L1_PIPE_COMP_GATHER_0FLOW - L2D_CACHE_HWPRF_ADJACENT - L2D_CACHE_REFILL_L3D_CACHE_PRF - L2D_CACHE_REFILL_L3D_CACHE_HWPRF - L2D_CACHE_REFILL_L3D_MISS_PRF - L2D_CACHE_REFILL_L3D_MISS_HWPRF - L2D_CACHE_REFILL_L3D_HIT_PRF - L2D_CACHE_REFILL_L3D_HIT_HWPRF - L1I_TLB_REFILL_4K - L1I_TLB_REFILL_64K - L1I_TLB_REFILL_2M - L1I_TLB_REFILL_32M - L1I_TLB_REFILL_512M - L1I_TLB_REFILL_1G - L1I_TLB_REFILL_16G - L1D_TLB_REFILL_4K - L1D_TLB_REFILL_64K - L1D_TLB_REFILL_2M - L1D_TLB_REFILL_32M - L1D_TLB_REFILL_512M - L1D_TLB_REFILL_1G - L1D_TLB_REFILL_16G - L2I_TLB_REFILL_4K - L2I_TLB_REFILL_64K - L2I_TLB_REFILL_2M - L2I_TLB_REFILL_32M - L2I_TLB_REFILL_512M - L2I_TLB_REFILL_1G - L2I_TLB_REFILL_16G - L2D_TLB_REFILL_4K - L2D_TLB_REFILL_64K - L2D_TLB_REFILL_2M - L2D_TLB_REFILL_32M - L2D_TLB_REFILL_512M - L2D_TLB_REFILL_1G - L2D_TLB_REFILL_16G - L2D_CACHE_LMISS_RD - L3D_CACHE_LMISS_RD - ASE_INST_SPEC - ASE_SVE_INST_SPEC - UOP_SPEC - ASE_SVE_FP_SPEC - ASE_SVE_FP_HP_SPEC - ASE_SVE_FP_SP_SPEC - ASE_SVE_FP_DP_SPEC - ASE_SVE_FP_DIV_SPEC - ASE_SVE_FP_SQRT_SPEC - FP_FMA_SPEC - ASE_SVE_FP_FMA_SPEC - FP_MUL_SPEC - ASE_SVE_FP_MUL_SPEC - FP_ADDSUB_SPEC - ASE_SVE_FP_ADDSUB_SPEC - ASE_FP_RECPE_SPEC - SVE_FP_RECPE_SPEC - ASE_SVE_FP_RECPE_SPEC - ASE_SVE_FP_CVT_SPEC - SVE_FP_AREDUCE_SPEC - ASE_FP_PREDUCE_SPEC - ASE_SVE_FP_VREDUCE_SPEC - ASE_INT_SPEC - SVE_INT_SPEC - ASE_SVE_INT_SPEC - ASE_SVE_INT_MUL_SPEC - SVE_INT_MULH64_SPEC - NONFP_SPEC - ASE_NONFP_SPEC - SVE_NONFP_SPEC - ASE_SVE_NONFP_SPEC - ASE_SVE_INT_VREDUCE_SPEC - ASE_SVE_LD_SPEC - ASE_SVE_ST_SPEC - ASE_SVE_LD_MULTI_SPEC - ASE_SVE_ST_MULTI_SPEC - FP_SCALE_OPS_SPEC - FP_FIXED_OPS_SPEC - FP_HP_SCALE_OPS_SPEC - FP_HP_FIXED_OPS_SPEC - FP_SP_SCALE_OPS_SPEC - FP_SP_FIXED_OPS_SPEC - FP_DP_SCALE_OPS_SPEC - FP_DP_FIXED_OPS_SPEC - L1I_CACHE_HWPRF - L1D_CACHE_HWPRF - L2D_CACHE_HWPRF - STALL_BACKEND_L2D - L1I_CACHE_REFILL_HWPRF - L1D_CACHE_REFILL_HWPRF - L2D_CACHE_REFILL_HWPRF - L2D_CACHE_HIT_RD - L2D_CACHE_HIT_WR - L2D_CACHE_HIT - L1I_CACHE_PRF - L1D_CACHE_PRF - L2D_CACHE_PRF - L1I_CACHE_REFILL_PRF - L1D_CACHE_REFILL_PRF - L2D_CACHE_REFILL_PRF - L1D_CACHE_REFILL_PERCYC - L2D_CACHE_REFILL_PERCYC - L1I_CACHE_REFILL_PERCYC Signed-off-by: Kotaro, Tokai --- lib/events/arm_fujitsu_monaka_events.h | 368 +++++++++++++++---------- 1 file changed, 223 insertions(+), 145 deletions(-) diff --git a/lib/events/arm_fujitsu_monaka_events.h b/lib/events/arm_fujitsu_monaka_events.h index 00c3e4f..4a97e7d 100644 --- a/lib/events/arm_fujitsu_monaka_events.h +++ b/lib/events/arm_fujitsu_monaka_events.h @@ -153,7 +153,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "STALL_BACKEND", .modmsk = ARMV9_ATTRS, .code = 0x0024, - .desc = "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because the backend is unable to accept any operations.", + .desc = "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because the backend is unable to accept any operation.", }, { .name = "L1D_TLB", @@ -219,7 +219,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "LL_CACHE_MISS_RD", .modmsk = ARMV9_ATTRS, .code = 0x0037, - .desc = "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events.", + .desc = "This event counts access counted by L3D_CACHE that is not completed by the L3 cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events. Note: This event may count inaccurately.", }, { .name = "L1D_CACHE_LMISS_RD", @@ -291,25 +291,25 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L2D_CACHE_RD", .modmsk = ARMV9_ATTRS, .code = 0x0050, - .desc = "This event counts L2D CACHE caused by read access.", + .desc = "This event counts L2D_CACHE caused by read access.", }, { .name = "L2D_CACHE_WR", .modmsk = ARMV9_ATTRS, .code = 0x0051, - .desc = "This event counts L2D CACHE caused by write access.", + .desc = "This event counts L2D_CACHE caused by write access.", }, { .name = "L2D_CACHE_REFILL_RD", .modmsk = ARMV9_ATTRS, .code = 0x0052, - .desc = "This event counts L2D CACHE_REFILL caused by read access.", + .desc = "This event counts L2D_CACHE_REFILL caused by read access.", }, { .name = "L2D_CACHE_REFILL_WR", .modmsk = ARMV9_ATTRS, .code = 0x0053, - .desc = "This event counts L2D CACHE_REFILL caused by write access.", + .desc = "This event counts L2D_CACHE_REFILL caused by write access.", }, { .name = "L2D_CACHE_WB_VICTIM", @@ -423,7 +423,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "CSDB_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x007f, - .desc = "This event counts speculatively executed control speculation barrier instructions.", + .desc = "This event counts architecturally executed control speculation barrier instructions.", }, { .name = "EXC_UNDEF", @@ -465,7 +465,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "EXC_SMC", .modmsk = ARMV9_ATTRS, .code = 0x0088, - .desc = "This event counts only Secure Monitor Call exceptions. The counter does not increment on SMC instructions trapped as a Hyp Trap exception.", + .desc = "This event counts only Secure Monitor Call exceptions. This event does not increment on SMC instructions trapped as a Hyp Trap exception.", }, { .name = "EXC_HVC", @@ -483,7 +483,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "FP_MV_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x0105, - .desc = "This event counts architecturally executed floating-point move operations.", + .desc = "This event counts architecturally executed floating-point move operation.", }, { .name = "PRD_SPEC", @@ -495,13 +495,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "IEL_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x0109, - .desc = "This event counts architecturally executed inter-element manipulation operations.", + .desc = "This event counts architecturally executed inter-element manipulation operation.", }, { .name = "IREG_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x010a, - .desc = "This event counts architecturally executed inter-register manipulation operations.", + .desc = "This event counts architecturally executed inter-register manipulation operation.", }, { .name = "FP_LD_SPEC", @@ -519,7 +519,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "BC_LD_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x011a, - .desc = "This event counts architecturally executed SIMD broadcast floating-point load operations.", + .desc = "This event counts architecturally executed SIMD broadcast floating-point load operation.", }, { .name = "DCZVA_SPEC", @@ -567,13 +567,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "LD_COMP_WAIT", .modmsk = ARMV9_ATTRS, .code = 0x0184, - .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access.", + .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache, L3 cache and memory access.", }, { .name = "LD_COMP_WAIT_EX", .modmsk = ARMV9_ATTRS, .code = 0x0185, - .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access.", + .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache, L3 cache and memory access.", }, { .name = "LD_COMP_WAIT_PFP_BUSY", @@ -993,19 +993,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L1_PIPE_COMP_GATHER_2FLOW", .modmsk = ARMV9_ATTRS, .code = 0x02b0, - .desc = "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined.", + .desc = "This event counts the number of times where 2 elements of the gather instructions became 2-flows because 2 elements could not be combined.", }, { .name = "L1_PIPE_COMP_GATHER_1FLOW", .modmsk = ARMV9_ATTRS, .code = 0x02b1, - .desc = "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined.", + .desc = "This event counts the number of times where 2 elements of the gather instructions became 1-flow because 2 elements could be combined.", }, { .name = "L1_PIPE_COMP_GATHER_0FLOW", .modmsk = ARMV9_ATTRS, .code = 0x02b2, - .desc = "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0.", + .desc = "This event counts the number of times where 2 elements of the gather instructions became 0-flow because both predicate values are 0.", }, { .name = "L1_PIPE_COMP_SCATTER_1FLOW", @@ -1047,7 +1047,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L2D_CACHE_HWPRF_ADJACENT", .modmsk = ARMV9_ATTRS, .code = 0x0305, - .desc = "This event counts L2D_CACHE caused by hardware adjacent prefetch access.", + .desc = "This event counts L2D_CACHE caused by hardware adjacent prefetch.", }, { .name = "L2D_CACHE_REFILL_DM", @@ -1131,19 +1131,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L2D_CACHE_REFILL_L3D_CACHE_PRF", .modmsk = ARMV9_ATTRS, .code = 0x0394, - .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by prefetch access.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch or software prefetch.", }, { .name = "L2D_CACHE_REFILL_L3D_CACHE_HWPRF", .modmsk = ARMV9_ATTRS, .code = 0x0395, - .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch access.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch.", }, { .name = "L2D_CACHE_REFILL_L3D_MISS", .modmsk = ARMV9_ATTRS, .code = 0x0396, - .desc = "This event counts operations that cause a miss of the L3 cache.", + .desc = "This event counts operations that cause a miss of the L3 cache. Note: This event may count inaccurately.", }, { .name = "L2D_CACHE_REFILL_L3D_MISS_DM", @@ -1167,19 +1167,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L2D_CACHE_REFILL_L3D_MISS_PRF", .modmsk = ARMV9_ATTRS, .code = 0x039a, - .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by prefetch access.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch or software prefetch. Note: This event may count inaccurately.", }, { .name = "L2D_CACHE_REFILL_L3D_MISS_HWPRF", .modmsk = ARMV9_ATTRS, .code = 0x039b, - .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch access.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch. Note: This event may count inaccurately.", }, { .name = "L2D_CACHE_REFILL_L3D_HIT", .modmsk = ARMV9_ATTRS, .code = 0x039c, - .desc = "This event counts operations that cause a hit of the L3 cache.", + .desc = "This event counts operations that cause a hit of the L3 cache. Note: This event may count inaccurately.", }, { .name = "L2D_CACHE_REFILL_L3D_HIT_DM", @@ -1203,79 +1203,73 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L2D_CACHE_REFILL_L3D_HIT_PRF", .modmsk = ARMV9_ATTRS, .code = 0x03a0, - .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by prefetch access.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch or software prefetch. Note: This event may count inaccurately.", }, { .name = "L2D_CACHE_REFILL_L3D_HIT_HWPRF", .modmsk = ARMV9_ATTRS, .code = 0x03a1, - .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch access.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch. Note: This event may count inaccurately.", }, { - .name = "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT", - .modmsk = ARMV9_ATTRS, - .code = 0x03a2, - .desc = "This event counts the number of L3 cache misses where the requests hit the PFTGT buffer.", - }, - { - .name = "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM", + .name = "L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT", .modmsk = ARMV9_ATTRS, .code = 0x03a3, - .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand access.", + .desc = "This event counts the number of L3 cache misses caused by demand access where the requests hit the PFTGT buffer.", }, { - .name = "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_RD", + .name = "L2D_CACHE_REFILL_L3D_MISS_DM_RD_PFTGT_HIT", .modmsk = ARMV9_ATTRS, .code = 0x03a4, - .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand read access.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT caused by read access.", }, { - .name = "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_WR", + .name = "L2D_CACHE_REFILL_L3D_MISS_DM_WR_PFTGT_HIT", .modmsk = ARMV9_ATTRS, .code = 0x03a5, - .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand write access.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT caused by write access.", }, { - .name = "L2D_CACHE_REFILL_L3D_MISS_L_MEM", + .name = "L2D_CACHE_REFILL_L3D_MISS_DM_L_MEM", .modmsk = ARMV9_ATTRS, .code = 0x03a6, - .desc = "This event counts the number of L3 cache misses where the requests access the memory in the same socket as the requests.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access the memory in the same socket as the requests.", }, { - .name = "L2D_CACHE_REFILL_L3D_MISS_FR_MEM", + .name = "L2D_CACHE_REFILL_L3D_MISS_DM_FR_MEM", .modmsk = ARMV9_ATTRS, .code = 0x03a7, - .desc = "This event counts the number of L3 cache misses where the requests access the memory in the different socket from the requests.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access the memory in the different socket from the requests.", }, { - .name = "L2D_CACHE_REFILL_L3D_MISS_L_L2", + .name = "L2D_CACHE_REFILL_L3D_MISS_DM_L_L2", .modmsk = ARMV9_ATTRS, .code = 0x03a8, - .desc = "This event counts the number of L3 cache misses where the requests access the different L2 cache from the requests in the same Numa nodes as the requests.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access the different L2 cache from the requests in the same Numa nodes as the requests.", }, { - .name = "L2D_CACHE_REFILL_L3D_MISS_NR_L2", + .name = "L2D_CACHE_REFILL_L3D_MISS_DM_NR_L2", .modmsk = ARMV9_ATTRS, .code = 0x03a9, - .desc = "This event counts the number of L3 cache misses where the requests access L2 cache in the different Numa nodes from the requests in the same socket as the requests.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L2 cache in the different Numa nodes from the requests in the same socket as the requests.", }, { - .name = "L2D_CACHE_REFILL_L3D_MISS_NR_L3", + .name = "L2D_CACHE_REFILL_L3D_MISS_DM_NR_L3", .modmsk = ARMV9_ATTRS, .code = 0x03aa, - .desc = "This event counts the number of L3 cache misses where the requests access L3 cache in the different Numa nodes from the requests in the same socket as the requests.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L3 cache in the different Numa nodes from the requests in the same socket as the requests.", }, { - .name = "L2D_CACHE_REFILL_L3D_MISS_FR_L2", + .name = "L2D_CACHE_REFILL_L3D_MISS_DM_FR_L2", .modmsk = ARMV9_ATTRS, .code = 0x03ab, - .desc = "This event counts the number of L3 cache misses where the requests access L2 cache in the different socket from the requests.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L2 cache in the different socket from the requests.", }, { - .name = "L2D_CACHE_REFILL_L3D_MISS_FR_L3", + .name = "L2D_CACHE_REFILL_L3D_MISS_DM_FR_L3", .modmsk = ARMV9_ATTRS, .code = 0x03ac, - .desc = "This event counts the number of L3 cache misses where the requests access L3 cache in the different socket from the requests.", + .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L3 cache in the different socket from the requests.", }, { .name = "L2D_CACHE_WB_VICTIM_CLEAN", @@ -1515,85 +1509,85 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L1I_TLB_REFILL_4K", .modmsk = ARMV9_ATTRS, .code = 0x0c10, - .desc = "This event counts operations that cause a TLB refill to the L1I in 4KB page.", + .desc = "This event counts operations that cause a TLB refill of the L1I in 4KB page.", }, { .name = "L1I_TLB_REFILL_64K", .modmsk = ARMV9_ATTRS, .code = 0x0c11, - .desc = "This event counts operations that cause a TLB refill to the L1I in 64KB page.", + .desc = "This event counts operations that cause a TLB refill of the L1I in 64KB page.", }, { .name = "L1I_TLB_REFILL_2M", .modmsk = ARMV9_ATTRS, .code = 0x0c12, - .desc = "This event counts operations that cause a TLB refill to the L1I in 2MB page.", + .desc = "This event counts operations that cause a TLB refill of the L1I in 2MB page.", }, { .name = "L1I_TLB_REFILL_32M", .modmsk = ARMV9_ATTRS, .code = 0x0c13, - .desc = "This event counts operations that cause a TLB refill to the L1I in 32MB page.", + .desc = "This event counts operations that cause a TLB refill of the L1I in 32MB page.", }, { .name = "L1I_TLB_REFILL_512M", .modmsk = ARMV9_ATTRS, .code = 0x0c14, - .desc = "This event counts operations that cause a TLB refill to the L1I in 512MB page.", + .desc = "This event counts operations that cause a TLB refill of the L1I in 512MB page.", }, { .name = "L1I_TLB_REFILL_1G", .modmsk = ARMV9_ATTRS, .code = 0x0c15, - .desc = "This event counts operations that cause a TLB refill to the L1I in 1GB page.", + .desc = "This event counts operations that cause a TLB refill of the L1I in 1GB page.", }, { .name = "L1I_TLB_REFILL_16G", .modmsk = ARMV9_ATTRS, .code = 0x0c16, - .desc = "This event counts operations that cause a TLB refill to the L1I in 16GB page.", + .desc = "This event counts operations that cause a TLB refill of the L1I in 16GB page.", }, { .name = "L1D_TLB_REFILL_4K", .modmsk = ARMV9_ATTRS, .code = 0x0c18, - .desc = "This event counts operations that cause a TLB refill to the L1D in 4KB page.", + .desc = "This event counts operations that cause a TLB refill of the L1D in 4KB page.", }, { .name = "L1D_TLB_REFILL_64K", .modmsk = ARMV9_ATTRS, .code = 0x0c19, - .desc = "This event counts operations that cause a TLB refill to the L1D in 64KB page.", + .desc = "This event counts operations that cause a TLB refill of the L1D in 64KB page.", }, { .name = "L1D_TLB_REFILL_2M", .modmsk = ARMV9_ATTRS, .code = 0x0c1a, - .desc = "This event counts operations that cause a TLB refill to the L1D in 2MB page.", + .desc = "This event counts operations that cause a TLB refill of the L1D in 2MB page.", }, { .name = "L1D_TLB_REFILL_32M", .modmsk = ARMV9_ATTRS, .code = 0x0c1b, - .desc = "This event counts operations that cause a TLB refill to the L1D in 32MB page.", + .desc = "This event counts operations that cause a TLB refill of the L1D in 32MB page.", }, { .name = "L1D_TLB_REFILL_512M", .modmsk = ARMV9_ATTRS, .code = 0x0c1c, - .desc = "This event counts operations that cause a TLB refill to the L1D in 512MB page.", + .desc = "This event counts operations that cause a TLB refill of the L1D in 512MB page.", }, { .name = "L1D_TLB_REFILL_1G", .modmsk = ARMV9_ATTRS, .code = 0x0c1d, - .desc = "This event counts operations that cause a TLB refill to the L1D in 1GB page.", + .desc = "This event counts operations that cause a TLB refill of the L1D in 1GB page.", }, { .name = "L1D_TLB_REFILL_16G", .modmsk = ARMV9_ATTRS, .code = 0x0c1e, - .desc = "This event counts operations that cause a TLB refill to the L1D in 16GB page.", + .desc = "This event counts operations that cause a TLB refill of the L1D in 16GB page.", }, { .name = "L2I_TLB_4K", @@ -1683,85 +1677,85 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L2I_TLB_REFILL_4K", .modmsk = ARMV9_ATTRS, .code = 0x0c30, - .desc = "This event counts operations that cause a TLB refill to the L2Iin 4KB page.", + .desc = "This event counts operations that cause a TLB refill of the L2I in 4KB page.", }, { .name = "L2I_TLB_REFILL_64K", .modmsk = ARMV9_ATTRS, .code = 0x0c31, - .desc = "This event counts operations that cause a TLB refill to the L2I in 64KB page.", + .desc = "This event counts operations that cause a TLB refill of the L2I in 64KB page.", }, { .name = "L2I_TLB_REFILL_2M", .modmsk = ARMV9_ATTRS, .code = 0x0c32, - .desc = "This event counts operations that cause a TLB refill to the L2I in 2MB page.", + .desc = "This event counts operations that cause a TLB refill of the L2I in 2MB page.", }, { .name = "L2I_TLB_REFILL_32M", .modmsk = ARMV9_ATTRS, .code = 0x0c33, - .desc = "This event counts operations that cause a TLB refill to the L2I in 32MB page.", + .desc = "This event counts operations that cause a TLB refill of the L2I in 32MB page.", }, { .name = "L2I_TLB_REFILL_512M", .modmsk = ARMV9_ATTRS, .code = 0x0c34, - .desc = "This event counts operations that cause a TLB refill to the L2I in 512MB page.", + .desc = "This event counts operations that cause a TLB refill of the L2I in 512MB page.", }, { .name = "L2I_TLB_REFILL_1G", .modmsk = ARMV9_ATTRS, .code = 0x0c35, - .desc = "This event counts operations that cause a TLB refill to the L2I in 1GB page.", + .desc = "This event counts operations that cause a TLB refill of the L2I in 1GB page.", }, { .name = "L2I_TLB_REFILL_16G", .modmsk = ARMV9_ATTRS, .code = 0x0c36, - .desc = "This event counts operations that cause a TLB refill to the L2I in 16GB page.", + .desc = "This event counts operations that cause a TLB refill of the L2I in 16GB page.", }, { .name = "L2D_TLB_REFILL_4K", .modmsk = ARMV9_ATTRS, .code = 0x0c38, - .desc = "This event counts operations that cause a TLB refill to the L2D in 4KB page.", + .desc = "This event counts operations that cause a TLB refill of the L2D in 4KB page.", }, { .name = "L2D_TLB_REFILL_64K", .modmsk = ARMV9_ATTRS, .code = 0x0c39, - .desc = "This event counts operations that cause a TLB refill to the L2D in 64KB page.", + .desc = "This event counts operations that cause a TLB refill of the L2D in 64KB page.", }, { .name = "L2D_TLB_REFILL_2M", .modmsk = ARMV9_ATTRS, .code = 0x0c3a, - .desc = "This event counts operations that cause a TLB refill to the L2D in 2MB page.", + .desc = "This event counts operations that cause a TLB refill of the L2D in 2MB page.", }, { .name = "L2D_TLB_REFILL_32M", .modmsk = ARMV9_ATTRS, .code = 0x0c3b, - .desc = "This event counts operations that cause a TLB refill to the L2D in 32MB page.", + .desc = "This event counts operations that cause a TLB refill of the L2D in 32MB page.", }, { .name = "L2D_TLB_REFILL_512M", .modmsk = ARMV9_ATTRS, .code = 0x0c3c, - .desc = "This event counts operations that cause a TLB refill to the L2D in 512MB page.", + .desc = "This event counts operations that cause a TLB refill of the L2D in 512MB page.", }, { .name = "L2D_TLB_REFILL_1G", .modmsk = ARMV9_ATTRS, .code = 0x0c3d, - .desc = "This event counts operations that cause a TLB refill to the L2D in 1GB page.", + .desc = "This event counts operations that cause a TLB refill of the L2D in 1GB page.", }, { .name = "L2D_TLB_REFILL_16G", .modmsk = ARMV9_ATTRS, .code = 0x0c3e, - .desc = "This event counts operations that cause a TLB refill to the L2D in 16GB page.", + .desc = "This event counts operations that cause a TLB refill of the L2D in 16GB page.", }, { .name = "CNT_CYCLES", @@ -1785,13 +1779,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L2D_CACHE_LMISS_RD", .modmsk = ARMV9_ATTRS, .code = 0x4009, - .desc = "This event counts operations that cause a refill of the L2D cache that incurs additional latency.", + .desc = "This event counts operations that cause a refill of the L2 cache that incurs additional latency.", }, { .name = "L3D_CACHE_LMISS_RD", .modmsk = ARMV9_ATTRS, .code = 0x400b, - .desc = "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events.", + .desc = "This event counts access counted by L3D_CACHE that is not completed by the L3 cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events. Note: This event may count inaccurately.", }, { .name = "TRB_WRAP", @@ -1845,7 +1839,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_INST_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8005, - .desc = "This event counts architecturally executed Advanced SIMD operations.", + .desc = "This event counts architecturally executed Advanced SIMD operation.", }, { .name = "SVE_INST_SPEC", @@ -1857,13 +1851,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_INST_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8007, - .desc = "This event counts architecturally executed Advanced SIMD and SVE operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE operation.", }, { .name = "UOP_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8008, - .desc = "This event counts all architecturally executed micro-operations.", + .desc = "This event counts all architecturally executed micro-operation.", }, { .name = "SVE_MATH_SPEC", @@ -1893,7 +1887,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_FP_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8013, - .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point operation.", }, { .name = "FP_HP_SPEC", @@ -1917,7 +1911,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_FP_HP_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8017, - .desc = "This event counts architecturally executed Advanced SIMD and SVE half-precision floating-point operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE half-precision floating-point operation.", }, { .name = "FP_SP_SPEC", @@ -1941,7 +1935,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_FP_SP_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x801b, - .desc = "This event counts architecturally executed Advanced SIMD and SVE single-precision floating-point operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE single-precision floating-point operation.", }, { .name = "FP_DP_SPEC", @@ -1965,7 +1959,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_FP_DP_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x801f, - .desc = "This event counts architecturally executed Advanced SIMD and SVE double-precision floating-point operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE double-precision floating-point operation.", }, { .name = "FP_DIV_SPEC", @@ -1989,7 +1983,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_FP_DIV_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8023, - .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point divide operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point divide operation.", }, { .name = "FP_SQRT_SPEC", @@ -2013,13 +2007,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_FP_SQRT_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8027, - .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point square root operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point square root operation.", }, { .name = "FP_FMA_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8028, - .desc = "This event counts architecturally executed floating-point fused multiply-add and multiply-subtract operations.", + .desc = "This event counts architecturally executed floating-point fused multiply-add and multiply-subtract operation.", }, { .name = "ASE_FP_FMA_SPEC", @@ -2037,13 +2031,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_FP_FMA_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x802b, - .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point FMA operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point FMA operation.", }, { .name = "FP_MUL_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x802c, - .desc = "This event counts architecturally executed floating-point multiply operations.", + .desc = "This event counts architecturally executed floating-point multiply operation.", }, { .name = "ASE_FP_MUL_SPEC", @@ -2061,13 +2055,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_FP_MUL_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x802f, - .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point multiply operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point multiply operation.", }, { .name = "FP_ADDSUB_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8030, - .desc = "This event counts architecturally executed floating-point add or subtract operations.", + .desc = "This event counts architecturally executed floating-point add or subtract operation.", }, { .name = "ASE_FP_ADDSUB_SPEC", @@ -2085,7 +2079,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_FP_ADDSUB_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8033, - .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point add or subtract operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point add or subtract operation.", }, { .name = "FP_RECPE_SPEC", @@ -2097,19 +2091,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_FP_RECPE_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8035, - .desc = "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operations.", + .desc = "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operation.", }, { .name = "SVE_FP_RECPE_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8036, - .desc = "This event counts architecturally executed SVE floating-point reciprocal estimate operations.", + .desc = "This event counts architecturally executed SVE floating-point reciprocal estimate operation.", }, { .name = "ASE_SVE_FP_RECPE_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8037, - .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point reciprocal estimate operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point reciprocal estimate operation.", }, { .name = "FP_CVT_SPEC", @@ -2133,19 +2127,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_FP_CVT_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x803b, - .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point convert operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point convert operation.", }, { .name = "SVE_FP_AREDUCE_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x803c, - .desc = "This event counts architecturally executed SVE floating-point accumulating reduction operations.", + .desc = "This event counts architecturally executed SVE floating-point accumulating reduction operation.", }, { .name = "ASE_FP_PREDUCE_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x803d, - .desc = "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operations.", + .desc = "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operation.", }, { .name = "SVE_FP_VREDUCE_SPEC", @@ -2157,7 +2151,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_FP_VREDUCE_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x803f, - .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point vector reduction operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point vector reduction operation.", }, { .name = "INT_SPEC", @@ -2169,19 +2163,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_INT_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8041, - .desc = "This event counts architecturally executed Advanced SIMD integer operations.", + .desc = "This event counts architecturally executed Advanced SIMD integer operation.", }, { .name = "SVE_INT_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8042, - .desc = "This event counts architecturally executed SVE integer operations.", + .desc = "This event counts architecturally executed SVE integer operation.", }, { .name = "ASE_SVE_INT_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8043, - .desc = "This event counts architecturally executed Advanced SIMD and SVE integer operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE integer operation.", }, { .name = "INT_DIV_SPEC", @@ -2229,7 +2223,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_INT_MUL_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x804b, - .desc = "This event counts architecturally executed Advanced SIMD and SVE integer multiply operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE integer multiply operation.", }, { .name = "INT_MUL64_SPEC", @@ -2253,31 +2247,31 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "SVE_INT_MULH64_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x804f, - .desc = "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply returning high part operations.", + .desc = "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply returning high part operation.", }, { .name = "NONFP_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8058, - .desc = "This event counts architecturally executed non-floating-point operations.", + .desc = "This event counts architecturally executed non-floating-point operation.", }, { .name = "ASE_NONFP_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8059, - .desc = "This event counts architecturally executed Advanced SIMD non-floating-point operations.", + .desc = "This event counts architecturally executed Advanced SIMD non-floating-point operation.", }, { .name = "SVE_NONFP_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x805a, - .desc = "This event counts architecturally executed SVE non-floating-point operations.", + .desc = "This event counts architecturally executed SVE non-floating-point operation.", }, { .name = "ASE_SVE_NONFP_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x805b, - .desc = "This event counts architecturally executed Advanced SIMD and SVE non-floating-point operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE non-floating-point operation.", }, { .name = "ASE_INT_VREDUCE_SPEC", @@ -2295,7 +2289,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_INT_VREDUCE_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x805f, - .desc = "This event counts architecturally executed Advanced SIMD and SVE integer reduction operations.", + .desc = "This event counts architecturally executed Advanced SIMD or SVE integer reduction operation.", }, { .name = "SVE_PERM_SPEC", @@ -2367,13 +2361,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_LD_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8085, - .desc = "This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD load instructions.", + .desc = "This event counts architecturally executed operations that read from memory due to Advanced SIMD or SVE load instructions.", }, { .name = "ASE_SVE_ST_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x8086, - .desc = "This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD store instructions.", + .desc = "This event counts architecturally executed operations that write to memory due to Advanced SIMD or SVE store instructions.", }, { .name = "PRF_SPEC", @@ -2439,13 +2433,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "ASE_SVE_LD_MULTI_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x80a5, - .desc = "This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD multiple vector contiguous structure load instructions.", + .desc = "This event counts architecturally executed operations that read from memory due to Advanced SIMD or SVE multiple vector contiguous structure load instructions.", }, { .name = "ASE_SVE_ST_MULTI_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x80a6, - .desc = "This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD multiple vector contiguous structure store instructions.", + .desc = "This event counts architecturally executed operations that write to memory due to Advanced SIMD or SVE multiple vector contiguous structure store instructions.", }, { .name = "SVE_LD_GATHER_SPEC", @@ -2475,49 +2469,49 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "FP_SCALE_OPS_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x80c0, - .desc = "This event counts architecturally executed SVE arithmetic operations. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC.", + .desc = "This event counts architecturally executed SVE arithmetic operation. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC.", }, { .name = "FP_FIXED_OPS_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x80c1, - .desc = "This event counts architecturally executed v8SIMD&FP arithmetic operations. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. The event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", + .desc = "This event counts architecturally executed v8SIMD&FP arithmetic operation. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", }, { .name = "FP_HP_SCALE_OPS_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x80c2, - .desc = "This event counts architecturally executed SVE half-precision arithmetic operations. See FP_HP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 8, or by 16 for operations that would also be counted by SVE_FP_FMA_SPEC.", + .desc = "This event counts architecturally executed SVE half-precision arithmetic operation. See FP_HP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 8, or by 16 for operations that would also be counted by SVE_FP_FMA_SPEC.", }, { .name = "FP_HP_FIXED_OPS_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x80c3, - .desc = "This event counts architecturally executed v8SIMD&FP half-precision arithmetic operations. See FP_HP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 16-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", + .desc = "This event counts architecturally executed v8SIMD&FP half-precision arithmetic operation. See FP_HP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 16-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", }, { .name = "FP_SP_SCALE_OPS_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x80c4, - .desc = "This event counts architecturally executed SVE single-precision arithmetic operations. See FP_SP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 4, or by 8 for operations that would also be counted by SVE_FP_FMA_SPEC.", + .desc = "This event counts architecturally executed SVE single-precision arithmetic operation. See FP_SP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 4, or by 8 for operations that would also be counted by SVE_FP_FMA_SPEC.", }, { .name = "FP_SP_FIXED_OPS_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x80c5, - .desc = "This event counts architecturally executed v8SIMD&FP single-precision arithmetic operations. See FP_SP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 32-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", + .desc = "This event counts architecturally executed v8SIMD&FP single-precision arithmetic operation. See FP_SP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 32-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", }, { .name = "FP_DP_SCALE_OPS_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x80c6, - .desc = "This event counts architecturally executed SVE double-precision arithmetic operations. See FP_DP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2, or by 4 for operations that would also be counted by SVE_FP_FMA_SPEC.", + .desc = "This event counts architecturally executed SVE double-precision arithmetic operation. See FP_DP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2, or by 4 for operations that would also be counted by SVE_FP_FMA_SPEC.", }, { .name = "FP_DP_FIXED_OPS_SPEC", .modmsk = ARMV9_ATTRS, .code = 0x80c7, - .desc = "This event counts architecturally executed v8SIMD&FP double-precision arithmetic operations. See FP_DP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2 for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", + .desc = "This event counts architecturally executed v8SIMD&FP double-precision arithmetic operation. See FP_DP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2 for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", }, { .name = "INT_SCALE_OPS_SPEC", @@ -2613,7 +2607,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L1I_CACHE_HWPRF", .modmsk = ARMV9_ATTRS, .code = 0x8145, - .desc = "This event counts access counted by L1I_CACHE that is due to a hardware prefetch.", + .desc = "This event counts L1I_CACHE caused by hardware prefetch.", }, { .name = "L2D_CACHE_MISS", @@ -2625,13 +2619,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L1D_CACHE_HWPRF", .modmsk = ARMV9_ATTRS, .code = 0x8154, - .desc = "This event counts access counted by L1D_CACHE that is due to a hardware prefetch.", + .desc = "This event counts L1D_CACHE caused by hardware prefetch.", }, { .name = "L2D_CACHE_HWPRF", .modmsk = ARMV9_ATTRS, .code = 0x8155, - .desc = "This event counts access counted by L2D_CACHE that is due to a hardware prefetch.", + .desc = "This event counts L2D_CACHE caused by hardware prefetch.", }, { .name = "STALL_FRONTEND_MEMBOUND", @@ -2703,7 +2697,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "STALL_BACKEND_L2D", .modmsk = ARMV9_ATTRS, .code = 0x8166, - .desc = "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L2D cache.", + .desc = "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L2 cache.", }, { .name = "STALL_BACKEND_TLB", @@ -2787,19 +2781,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L1I_CACHE_REFILL_HWPRF", .modmsk = ARMV9_ATTRS, .code = 0x81b8, - .desc = "This event counts hardware prefetch counted by L1I_CACHE_HWPRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache.", + .desc = "This event counts L1I_CACHE_REFILL caused by hardware prefetch.", }, { .name = "L1D_CACHE_REFILL_HWPRF", .modmsk = ARMV9_ATTRS, .code = 0x81bc, - .desc = "This event counts hardware prefetch counted by L1D_CACHE_HWPRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache.", + .desc = "This event counts L1D_CACHE_REFILL caused by hardware prefetch.", }, { .name = "L2D_CACHE_REFILL_HWPRF", .modmsk = ARMV9_ATTRS, .code = 0x81bd, - .desc = "This event counts hardware prefetch counted by L2D_CACHE_HWPRF that causes a refill of the Level 2 cache, or any Level 1 data and instruction cache of this PE, from outside of those caches.", + .desc = "This event counts L2D_CACHE_REFILL caused by hardware prefetch.", }, { .name = "L1I_CACHE_HIT_RD", @@ -2817,7 +2811,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L2D_CACHE_HIT_RD", .modmsk = ARMV9_ATTRS, .code = 0x81c5, - .desc = "This event counts demand read counted by L2D_CACHE_RD that hits in the Level 2 data cache.", + .desc = "This event counts demand read counted by L2D_CACHE_RD that hits in the Level 2 cache.", }, { .name = "L1D_CACHE_HIT_WR", @@ -2829,7 +2823,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L2D_CACHE_HIT_WR", .modmsk = ARMV9_ATTRS, .code = 0x81c9, - .desc = "This event counts demand write counted by L2D_CACHE_WR that hits in the Level 2 data cache.", + .desc = "This event counts demand write counted by L2D_CACHE_WR that hits in the Level 2 cache.", }, { .name = "L1I_CACHE_HIT", @@ -2847,7 +2841,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L2D_CACHE_HIT", .modmsk = ARMV9_ATTRS, .code = 0x8205, - .desc = "This event counts access counted by L2D_CACHE that hits in the Level 2 data cache.", + .desc = "This event counts access counted by L2D_CACHE that hits in the Level 2 cache.", }, { .name = "L1I_LFB_HIT_RD", @@ -2883,54 +2877,138 @@ static const arm_entry_t arm_monaka_pe[ ] = { .name = "L1I_CACHE_PRF", .modmsk = ARMV9_ATTRS, .code = 0x8280, - .desc = "This event counts fetch counted by either Level 1 instruction hardware prefetch or Level 1 instruction software prefetch.", + .desc = "This event counts L1I_CACHE caused by hardware prefetch or software prefetch.", }, { .name = "L1D_CACHE_PRF", .modmsk = ARMV9_ATTRS, .code = 0x8284, - .desc = "This event counts fetch counted by either Level 1 data hardware prefetch or Level 1 data software prefetch.", + .desc = "This event counts L1D_CACHE caused by hardware prefetch or software prefetch.", }, { .name = "L2D_CACHE_PRF", .modmsk = ARMV9_ATTRS, .code = 0x8285, - .desc = "This event counts fetch counted by either Level 2 data hardware prefetch or Level 2 data software prefetch.", + .desc = "This event counts L2D_CACHE caused by hardware prefetch or software prefetch.", }, { .name = "L1I_CACHE_REFILL_PRF", .modmsk = ARMV9_ATTRS, .code = 0x8288, - .desc = "This event counts hardware prefetch counted by L1I_CACHE_PRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache.", + .desc = "This event counts L1I_CACHE_REFILL caused by hardware prefetch or software prefetch.", }, { .name = "L1D_CACHE_REFILL_PRF", .modmsk = ARMV9_ATTRS, .code = 0x828c, - .desc = "This event counts hardware prefetch counted by L1D_CACHE_PRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache.", + .desc = "This event counts L1D_CACHE_REFILL caused by hardware prefetch or software prefetch.", }, { .name = "L2D_CACHE_REFILL_PRF", .modmsk = ARMV9_ATTRS, .code = 0x828d, - .desc = "This event counts hardware prefetch counted by L2D_CACHE_PRF that causes a refill of the Level 2 data cache from outside of the Level 1 data cache.", + .desc = "This event counts L2D_CACHE_REFILL caused by hardware prefetch or software prefetch.", }, { .name = "L1D_CACHE_REFILL_PERCYC", .modmsk = ARMV9_ATTRS, .code = 0x8320, - .desc = "The counter counts by the number of cache refills counted by L1D_CACHE_REFILL in progress on each Processor cycle.", + .desc = "This counter counts by the number of cache refills counted by L1D_CACHE_REFILL in progress on each Processor cycle.", }, { .name = "L2D_CACHE_REFILL_PERCYC", .modmsk = ARMV9_ATTRS, .code = 0x8321, - .desc = "The counter counts by the number of cache refills counted by L2D_CACHE_REFILL in progress on each Processor cycle.", + .desc = "This counter counts by the number of cache refills counted by L2D_CACHE_REFILL in progress on each Processor cycle.", }, { .name = "L1I_CACHE_REFILL_PERCYC", .modmsk = ARMV9_ATTRS, .code = 0x8324, - .desc = "The counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle.", + .desc = "This counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle.", + }, + { + .name = "ASE_FP_VREDUCE_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8431, + .desc = "This event counts architecturally executed Advanced SIMD floating-point vector reduction operation.", + }, + { + .name = "SVE_FP_PREDUCE_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8432, + .desc = "This event counts architecturally executed SVE floating-point pairwise add step operation.", + }, + { + .name = "ASE_FP_BF16_MIN_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8443, + .desc = "This event counts architecturally executed Advanced SIMD data processing operations, smallest type is BFloat16 floating-point.", + }, + { + .name = "ASE_FP_FP8_MIN_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8444, + .desc = "This event counts architecturally executed Advanced SIMD data processing operations, smallest type is 8-bit floating-point.", + }, + { + .name = "ASE_SVE_FP_BF16_MIN_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x844b, + .desc = "This event counts architecturally executed Advanced SIMD data processing or SVE data processing operations, smallest type is BFloat16 floating-point.", + }, + { + .name = "ASE_SVE_FP_FP8_MIN_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x844c, + .desc = "This event counts architecturally executed Advanced SIMD data processing or SVE data processing operations, smallest type is 8-bit floating-point.", + }, + { + .name = "SVE_FP_BF16_MIN_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8463, + .desc = "This event counts architecturally executed SVE data processing operations, smallest type is BFloat16 floating-point.", + }, + { + .name = "SVE_FP_FP8_MIN_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8464, + .desc = "This event counts architecturally executed SVE data processing operations, smallest type is 8-bit floating-point.", + }, + { + .name = "FP_BF16_MIN_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8473, + .desc = "This event counts architecturally executed data processing operations, smallest type is BFloat16 floating-point.", + }, + { + .name = "FP_FP8_MIN_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8474, + .desc = "This event counts architecturally executed data processing operations, smallest type is 8-bit floating-point.", + }, + { + .name = "FP_BF16_FIXED_MIN_OPS_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8483, + .desc = "This event counts architecturally executed non-scalable element arithmetic operations, smallest type is BFloat16 floating-point.", + }, + { + .name = "FP_FP8_FIXED_MIN_OPS_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8484, + .desc = "This event counts architecturally executed non-scalable element arithmetic operations, smallest type is 8-bit floating-point.", + }, + { + .name = "FP_BF16_SCALE_MIN_OPS_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x848b, + .desc = "This event counts architecturally executed scalable element arithmetic operations, smallest type is BFloat16 floating-point.", + }, + { + .name = "FP_FP8_SCALE_MIN_OPS_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x848c, + .desc = "This event counts architecturally executed scalable element arithmetic operations, smallest type is 8-bit floating-point.", }, }; -- 2.54.0