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Update to libpfm-4.5.0

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This commit is contained in:
William Cohen 2014-05-23 13:38:02 -04:00
parent bbc8d2ec41
commit dbbf2a9355
5 changed files with 968 additions and 1185 deletions
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1
.gitignore vendored
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@ -3,3 +3,4 @@
/libpfm-4.4.0-3.199.g0b87987.tar.gz
/libpfm-4.4.0-3.200.g9df2031.tar.gz
/libpfm-4.4.0-5.217.gbca43a5.tar.gz
/libpfm-4.5.0.tar.gz

958
libpfm-ac57.patch Normal file
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@ -0,0 +1,958 @@
commit b1a3bf942376a3eaddc6f089c74bf5e322295822
Author: Stephane Eranian <eranian@gmail.com>
Date: Tue May 6 14:42:23 2014 +0200
Add ARM Cortex A57 support
This patch adds support for ARM Cortex A57 processor
for both 64 and 32 bit modes (armv8).
Based on Table 11-24 from the "Cortex A57 Technical Reference Manual"
The validation tests for A57 in 64-bit mode is also added.
Signed-off-by: Stephane Eranian <eranian@gmail.com>
diff --git a/config.mk b/config.mk
index 457d943..9553cbe 100644
--- a/config.mk
+++ b/config.mk
@@ -66,6 +66,15 @@ endif
ifeq (armv7,$(findstring armv7,$(ARCH)))
override ARCH=arm
endif
+ifeq (armv7,$(findstring armv7,$(ARCH)))
+override ARCH=arm
+endif
+ifeq (aarch32,$(findstring aarch32,$(ARCH)))
+override ARCH=arm
+endif
+ifeq (armv8l,$(findstring armv8l,$(ARCH)))
+override ARCH=arm
+endif
ifeq (mips64,$(findstring mips64,$(ARCH)))
override ARCH=mips
endif
@@ -152,6 +161,14 @@ ifeq ($(ARCH),arm)
CONFIG_PFMLIB_ARCH_ARM=y
endif
+ifeq ($(ARCH),aarch64)
+CONFIG_PFMLIB_ARCH_ARM64=y
+endif
+
+ifeq ($(ARCH),arm64)
+CONFIG_PFMLIB_ARCH_ARM64=y
+endif
+
ifeq ($(ARCH),s390x)
CONFIG_PFMLIB_ARCH_S390X=y
endif
diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h
index dfdd471..b08df66 100644
--- a/include/perfmon/pfmlib.h
+++ b/include/perfmon/pfmlib.h
@@ -237,6 +237,8 @@ typedef enum {
PFM_PMU_S390X_CPUM_SF, /* s390x: CPU-M sampling facility */
+ PFM_PMU_ARM_CORTEX_A57, /* ARM Cortex A57 (ARMv8) */
+
/* MUST ADD NEW PMU MODELS HERE */
PFM_PMU_MAX /* end marker */
diff --git a/lib/Makefile b/lib/Makefile
index 531167e..6ca3287 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -139,10 +139,21 @@ SRCS += pfmlib_arm_perf_event.c
endif
INCARCH = $(INC_ARM)
-SRCS += pfmlib_arm.c pfmlib_arm_armv7_pmuv1.c pfmlib_arm_armv6.c
+SRCS += pfmlib_arm.c pfmlib_arm_armv7_pmuv1.c pfmlib_arm_armv6.c pfmlib_arm_armv8.c
CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM
endif
+ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y)
+
+ifeq ($(SYS),Linux)
+SRCS += pfmlib_arm_perf_event.c
+endif
+
+INCARCH = $(INC_ARM64)
+SRCS += pfmlib_arm.c pfmlib_arm_armv8.c
+CFLAGS += -DCONFIG_PFMLIB_ARCH_ARM64
+endif
+
ifeq ($(CONFIG_PFMLIB_ARCH_MIPS),y)
ifeq ($(SYS),Linux)
@@ -272,6 +283,8 @@ INC_ARM=pfmlib_arm_priv.h \
events/arm_cortex_a9_events.h \
events/arm_cortex_a15_events.h
+INC_ARM64=events/arm_cortex_a57_events.h
+
INCDEP=$(INC_COMMON) $(INCARCH)
all: $(TARGETS)
diff --git a/lib/events/arm_cortex_a57_events.h b/lib/events/arm_cortex_a57_events.h
new file mode 100644
index 0000000..9d1d407
--- /dev/null
+++ b/lib/events/arm_cortex_a57_events.h
@@ -0,0 +1,440 @@
+/*
+ * Copyright (c) 2014 Google Inc. All rights reserved
+ * Contributed by Stephane Eranian <eranian@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Cortex A57 r1p1
+ * based on Table 11-24 from the "Cortex A57 Technical Reference Manual"
+ */
+
+static const arm_entry_t arm_cortex_a57_pe[]={
+ {.name = "SW_INCR",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x00,
+ .desc = "Instruction architecturally executed (condition check pass) Software increment"
+ },
+ {.name = "L1I_CACHE_REFILL",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x01,
+ .desc = "Level 1 instruction cache refill"
+ },
+ {.name = "L1I_TLB_REFILL",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x02,
+ .desc = "Level 1 instruction TLB refill"
+ },
+ {.name = "L1D_CACHE_REFILL",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x03,
+ .desc = "Level 1 data cache refill"
+ },
+ {.name = "L1D_CACHE_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x04,
+ .desc = "Level 1 data cache access"
+ },
+ {.name = "L1D_TLB_REFILL",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x05,
+ .desc = "Level 1 data TLB refill"
+ },
+
+ {.name = "INST_RETIRED",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x08,
+ .desc = "Instruction architecturally executed"
+ },
+ {.name = "EXCEPTION_TAKEN",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x09,
+ .desc = "Exception taken"
+ },
+ {.name = "EXCEPTION_RETURN",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x0a,
+ .desc = "Instruction architecturally executed (condition check pass) Exception return"
+ },
+ {.name = "CID_WRITE_RETIRED",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x0b,
+ .desc = "Instruction architecturally executed (condition check pass) Write to CONTEXTIDR"
+ },
+
+ {.name = "BRANCH_MISPRED",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x10,
+ .desc = "Mispredicted or not predicted branch speculatively executed"
+ },
+ {.name = "CPU_CYCLES",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x11,
+ .desc = "Cycles"
+ },
+ {.name = "BRANCH_PRED",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x12,
+ .desc = "Predictable branch speculatively executed"
+ },
+ {.name = "DATA_MEM_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x13,
+ .desc = "Data memory access"
+ },
+ {.name = "L1I_CACHE_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x14,
+ .desc = "Level 1 instruction cache access"
+ },
+ {.name = "L1D_CACHE_WB",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x15,
+ .desc = "Level 1 data cache WriteBack"
+ },
+ {.name = "L2D_CACHE_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x16,
+ .desc = "Level 2 data cache access"
+ },
+ {.name = "L2D_CACHE_REFILL",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x17,
+ .desc = "Level 2 data cache refill"
+ },
+ {.name = "L2D_CACHE_WB",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x18,
+ .desc = "Level 2 data cache WriteBack"
+ },
+ {.name = "BUS_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x19,
+ .desc = "Bus access"
+ },
+ {.name = "LOCAL_MEMORY_ERROR",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x1a,
+ .desc = "Local memory error"
+ },
+ {.name = "INST_SPEC_EXEC",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x1b,
+ .desc = "Instruction speculatively executed"
+ },
+ {.name = "TTBR_WRITE_RETIRED",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x1c,
+ .desc = "Instruction architecturally executed (condition check pass) Write to translation table base"
+ },
+ {.name = "BUS_CYCLES",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x1d,
+ .desc = "Bus cycle"
+ },
+ {.name = "L1D_READ_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x40,
+ .desc = "Level 1 data cache read access"
+ },
+ {.name = "L1D_WRITE_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x41,
+ .desc = "Level 1 data cache write access"
+ },
+ {.name = "L1D_READ_REFILL",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x42,
+ .desc = "Level 1 data cache read refill"
+ },
+ {.name = "L1D_WRITE_REFILL",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x43,
+ .desc = "Level 1 data cache write refill"
+ },
+ {.name = "L1D_WB_VICTIM",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x46,
+ .desc = "Level 1 data cache writeback victim"
+ },
+ {.name = "L1D_WB_CLEAN_COHERENCY",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x47,
+ .desc = "Level 1 data cache writeback cleaning and coherency"
+ },
+ {.name = "L1D_INVALIDATE",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x48,
+ .desc = "Level 1 data cache invalidate"
+ },
+ {.name = "L1D_TLB_READ_REFILL",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x4c,
+ .desc = "Level 1 data TLB read refill"
+ },
+ {.name = "L1D_TLB_WRITE_REFILL",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x4d,
+ .desc = "Level 1 data TLB write refill"
+ },
+ {.name = "L2D_READ_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x50,
+ .desc = "Level 2 data cache read access"
+ },
+ {.name = "L2D_WRITE_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x51,
+ .desc = "Level 2 data cache write access"
+ },
+ {.name = "L2D_READ_REFILL",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x52,
+ .desc = "Level 2 data cache read refill"
+ },
+ {.name = "L2D_WRITE_REFILL",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x53,
+ .desc = "Level 2 data cache write refill"
+ },
+ {.name = "L2D_WB_VICTIM",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x56,
+ .desc = "Level 2 data cache writeback victim"
+ },
+ {.name = "L2D_WB_CLEAN_COHERENCY",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x57,
+ .desc = "Level 2 data cache writeback cleaning and coherency"
+ },
+ {.name = "L2D_INVALIDATE",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x58,
+ .desc = "Level 2 data cache invalidate"
+ },
+ {.name = "BUS_READ_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x60,
+ .desc = "Bus read access"
+ },
+ {.name = "BUS_WRITE_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x61,
+ .desc = "Bus write access"
+ },
+ {.name = "BUS_NORMAL_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x62,
+ .desc = "Bus normal access"
+ },
+ {.name = "BUS_NOT_NORMAL_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x63,
+ .desc = "Bus not normal access"
+ },
+ {.name = "BUS_NORMAL_ACCESS_2",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x64,
+ .desc = "Bus normal access"
+ },
+ {.name = "BUS_PERIPH_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x65,
+ .desc = "Bus peripheral access"
+ },
+ {.name = "DATA_MEM_READ_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x66,
+ .desc = "Data memory read access"
+ },
+ {.name = "DATA_MEM_WRITE_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x67,
+ .desc = "Data memory write access"
+ },
+ {.name = "UNALIGNED_READ_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x68,
+ .desc = "Unaligned read access"
+ },
+ {.name = "UNALIGNED_WRITE_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x69,
+ .desc = "Unaligned read access"
+ },
+ {.name = "UNALIGNED_ACCESS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x6a,
+ .desc = "Unaligned access"
+ },
+ {.name = "INST_SPEC_EXEC_LDREX",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x6c,
+ .desc = "LDREX exclusive instruction speculatively executed"
+ },
+ {.name = "INST_SPEC_EXEC_STREX_PASS",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x6d,
+ .desc = "STREX pass exclusive instruction speculatively executed"
+ },
+ {.name = "INST_SPEC_EXEC_STREX_FAIL",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x6e,
+ .desc = "STREX fail exclusive instruction speculatively executed"
+ },
+ {.name = "INST_SPEC_EXEC_LOAD",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x70,
+ .desc = "Load instruction speculatively executed"
+ },
+ {.name = "INST_SPEC_EXEC_STORE",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x71,
+ .desc = "Store instruction speculatively executed"
+ },
+ {.name = "INST_SPEC_EXEC_LOAD_STORE",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x72,
+ .desc = "Load or store instruction speculatively executed"
+ },
+ {.name = "INST_SPEC_EXEC_INTEGER_INST",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x73,
+ .desc = "Integer data processing instruction speculatively executed"
+ },
+ {.name = "INST_SPEC_EXEC_SIMD",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x74,
+ .desc = "Advanced SIMD instruction speculatively executed"
+ },
+ {.name = "INST_SPEC_EXEC_VFP",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x75,
+ .desc = "VFP instruction speculatively executed"
+ },
+ {.name = "INST_SPEC_EXEC_SOFT_PC",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x76,
+ .desc = "Software of the PC instruction speculatively executed"
+ },
+ {.name = "BRANCH_SPEC_EXEC_IMM_BRANCH",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x78,
+ .desc = "Immediate branch speculatively executed"
+ },
+ {.name = "BRANCH_SPEC_EXEC_RET",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x79,
+ .desc = "Return branch speculatively executed"
+ },
+ {.name = "BRANCH_SPEC_EXEC_IND",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x7a,
+ .desc = "Indirect branch speculatively executed"
+ },
+ {.name = "BARRIER_SPEC_EXEC_ISB",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x7c,
+ .desc = "ISB barrier speculatively executed"
+ },
+ {.name = "BARRIER_SPEC_EXEC_DSB",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x7d,
+ .desc = "DSB barrier speculatively executed"
+ },
+ {.name = "BARRIER_SPEC_EXEC_DMB",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x7e,
+ .desc = "DMB barrier speculatively executed"
+ },
+ {.name = "EXCEPTION_UNDEF",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x81,
+ .desc = "Exception taken, other synchronous"
+ },
+ {.name = "EXCEPTION_SVC",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x82,
+ .desc = "Exception taken, supervisor call"
+ },
+ {.name = "EXCEPTION_PABORT",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x83,
+ .desc = "Exception taken, instruction abort"
+ },
+ {.name = "EXCEPTION_DABORT",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x84,
+ .desc = "Exception taken, data abort or SError"
+ },
+ {.name = "EXCEPTION_IRQ",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x86,
+ .desc = "Exception taken, irq"
+ },
+ {.name = "EXCEPTION_FIQ",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x87,
+ .desc = "Exception taken, irq"
+ },
+ {.name = "EXCEPTION_SMC",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x88,
+ .desc = "Exception taken, secure monitor call"
+ },
+ {.name = "EXCEPTION_HVC",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x8a,
+ .desc = "Exception taken, hypervisor call"
+ },
+ {.name = "EXCEPTION_TRAP_PABORT",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x8b,
+ .desc = "Exception taken, instruction abort not taken locally"
+ },
+ {.name = "EXCEPTION_TRAP_DABORT",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x8c,
+ .desc = "Exception taken, data abort or SError not taken locally"
+ },
+ {.name = "EXCEPTION_TRAP_OTHER",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x8d,
+ .desc = "Exception taken, other traps not taken locally"
+ },
+ {.name = "EXCEPTION_TRAP_IRQ",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x8e,
+ .desc = "Exception taken, irq not taken locally"
+ },
+ {.name = "EXCEPTION_TRAP_FIQ",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x8f,
+ .desc = "Exception taken, fiq not taken locally"
+ },
+ {.name = "RC_LD_SPEC",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x90,
+ .desc = "Release consistency instruction speculatively executed (load-acquire)",
+ },
+ {.name = "RC_ST_SPEC",
+ .modmsk = ARMV8_ATTRS,
+ .code = 0x91,
+ .desc = "Release consistency instruction speculatively executed (store-release)",
+ },
+ /* END Cortex A47 specific events */
+};
diff --git a/lib/pfmlib_arm_armv8.c b/lib/pfmlib_arm_armv8.c
new file mode 100644
index 0000000..880d566
--- /dev/null
+++ b/lib/pfmlib_arm_armv8.c
@@ -0,0 +1,74 @@
+/*
+ * pfmlib_arm_armv8.c : support for ARMv8 processors
+ *
+ * Copyright (c) 2014 Google Inc. All rights reserved
+ * Contributed by Stephane Eranian <eranian@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include <sys/types.h>
+#include <string.h>
+#include <stdlib.h>
+
+/* private headers */
+#include "pfmlib_priv.h" /* library private */
+#include "pfmlib_arm_priv.h"
+
+#include "events/arm_cortex_a57_events.h" /* event tables */
+
+static int
+pfm_arm_detect_cortex_a57(void *this)
+{
+ int ret;
+
+ ret = pfm_arm_detect(this);
+ if (ret != PFM_SUCCESS)
+ return PFM_ERR_NOTSUPP;
+
+ if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */
+ (pfm_arm_cfg.part == 0xc00)) { /* Cortex A57 */
+ return PFM_SUCCESS;
+ }
+ return PFM_ERR_NOTSUPP;
+}
+
+/* ARM Cortex A57 support */
+pfmlib_pmu_t arm_cortex_a57_support={
+ .desc = "ARM Cortex A57",
+ .name = "arm_ac57",
+ .pmu = PFM_PMU_ARM_CORTEX_A57,
+ .pme_count = LIBPFM_ARRAY_SIZE(arm_cortex_a57_pe),
+ .type = PFM_PMU_TYPE_CORE,
+ .pe = arm_cortex_a57_pe,
+
+ .pmu_detect = pfm_arm_detect_cortex_a57,
+ .max_encoding = 1,
+ .num_cntrs = 6,
+
+ .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding,
+ PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding),
+ .get_event_first = pfm_arm_get_event_first,
+ .get_event_next = pfm_arm_get_event_next,
+ .event_is_valid = pfm_arm_event_is_valid,
+ .validate_table = pfm_arm_validate_table,
+ .get_event_info = pfm_arm_get_event_info,
+ .get_event_attr_info = pfm_arm_get_event_attr_info,
+ PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs),
+ .get_event_nattrs = pfm_arm_get_event_nattrs,
+};
diff --git a/lib/pfmlib_arm_priv.h b/lib/pfmlib_arm_priv.h
index ef367b7..227508b 100644
--- a/lib/pfmlib_arm_priv.h
+++ b/lib/pfmlib_arm_priv.h
@@ -86,6 +86,9 @@ extern int pfm_arm_get_perf_encoding(void *this, pfmlib_event_desc_t *e);
#define ARMV7_A15_ATTRS (_ARM_ATTR_K|_ARM_ATTR_U|_ARM_ATTR_HV)
#define ARMV7_A15_PLM (PFM_PLM0|PFM_PLM3|PFM_PLMH)
+#define ARMV8_ATTRS (_ARM_ATTR_K|_ARM_ATTR_U|_ARM_ATTR_HV)
+#define ARMV8_PLM (PFM_PLM0|PFM_PLM3|PFM_PLMH)
+
static inline int
arm_has_plm(void *this, pfmlib_event_desc_t *e)
{
diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c
index 8e4b1a1..900d7de 100644
--- a/lib/pfmlib_common.c
+++ b/lib/pfmlib_common.c
@@ -199,7 +199,12 @@ static pfmlib_pmu_t *pfmlib_pmus[]=
&arm_cortex_a15_support,
&arm_1176_support,
&arm_qcom_krait_support,
+ &arm_cortex_a57_support,
#endif
+#ifdef CONFIG_PFMLIB_ARCH_ARM64
+ &arm_cortex_a57_support,
+#endif
+
#ifdef CONFIG_PFMLIB_ARCH_S390X
&s390x_cpum_cf_support,
&s390x_cpum_sf_support,
diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h
index 715c4b0..3031d3b 100644
--- a/lib/pfmlib_priv.h
+++ b/lib/pfmlib_priv.h
@@ -332,6 +332,7 @@ extern pfmlib_pmu_t arm_cortex_a9_support;
extern pfmlib_pmu_t arm_cortex_a15_support;
extern pfmlib_pmu_t arm_1176_support;
extern pfmlib_pmu_t arm_qcom_krait_support;
+extern pfmlib_pmu_t arm_cortex_a57_support;
extern pfmlib_pmu_t mips_74k_support;
extern pfmlib_pmu_t s390x_cpum_cf_support;
extern pfmlib_pmu_t s390x_cpum_sf_support;
diff --git a/tests/Makefile b/tests/Makefile
index 7076fb7..7dd82c3 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -39,6 +39,10 @@ ifeq ($(CONFIG_PFMLIB_ARCH_ARM),y)
SRCS += validate_arm.c
endif
+ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y)
+SRCS += validate_arm64.c
+endif
+
ifeq ($(CONFIG_PFMLIB_ARCH_POWERPC),y)
SRCS += validate_power.c
endif
diff --git a/tests/validate_arm.c b/tests/validate_arm.c
index fe97aa9..d6c0168 100644
--- a/tests/validate_arm.c
+++ b/tests/validate_arm.c
@@ -159,6 +159,34 @@ static const test_event_t arm_test_events[]={
.codes[0] = 0x480000ff,
.fstr = "qcom_krait::CPU_CYCLES:k=0:u=1:hv=0",
},
+ { SRC_LINE,
+ .name = "arm_ac57::CPU_CYCLES",
+ .ret = PFM_SUCCESS,
+ .count = 1,
+ .codes[0] = 0x8000011,
+ .fstr = "arm_ac57::CPU_CYCLES:k=1:u=1:hv=0",
+ },
+ { SRC_LINE,
+ .name = "arm_ac57::CPU_CYCLES:k",
+ .ret = PFM_SUCCESS,
+ .count = 1,
+ .codes[0] = 0x88000011,
+ .fstr = "arm_ac57::CPU_CYCLES:k=1:u=0:hv=0",
+ },
+ { SRC_LINE,
+ .name = "arm_ac57::CPU_CYCLES:k:u",
+ .ret = PFM_SUCCESS,
+ .count = 1,
+ .codes[0] = 0x8000011,
+ .fstr = "arm_ac57::CPU_CYCLES:k=1:u=1:hv=0",
+ },
+ { SRC_LINE,
+ .name = "arm_ac57::INST_RETIRED",
+ .ret = PFM_SUCCESS,
+ .count = 1,
+ .codes[0] = 0x8000008,
+ .fstr = "arm_ac57::INST_RETIRED:k=1:u=1:hv=0",
+ },
};
#define NUM_TEST_EVENTS (int)(sizeof(arm_test_events)/sizeof(test_event_t))
diff --git a/tests/validate_arm64.c b/tests/validate_arm64.c
new file mode 100644
index 0000000..0f0174c
--- /dev/null
+++ b/tests/validate_arm64.c
@@ -0,0 +1,138 @@
+/*
+ * validate_arm64.c - validate ARM64 event tables + encodings
+ *
+ * Copyright (c) 2014 Google, Inc
+ * Contributed by Stephane Eranian <eranian@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+ * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+ * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include <sys/types.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <inttypes.h>
+#include <stdarg.h>
+#include <errno.h>
+#include <unistd.h>
+#include <string.h>
+
+#include <perfmon/pfmlib.h>
+
+#define MAX_ENCODING 1
+#define SRC_LINE .line = __LINE__
+
+typedef struct {
+ const char *name;
+ const char *fstr;
+ uint64_t codes[MAX_ENCODING];
+ int ret, count, line;
+} test_event_t;
+
+static const test_event_t arm64_test_events[]={
+ { SRC_LINE,
+ .name = "arm_ac57::CPU_CYCLES",
+ .ret = PFM_SUCCESS,
+ .count = 1,
+ .codes[0] = 0x8000011,
+ .fstr = "arm_ac57::CPU_CYCLES:k=1:u=1:hv=0",
+ },
+ { SRC_LINE,
+ .name = "arm_ac57::CPU_CYCLES:k",
+ .ret = PFM_SUCCESS,
+ .count = 1,
+ .codes[0] = 0x88000011,
+ .fstr = "arm_ac57::CPU_CYCLES:k=1:u=0:hv=0",
+ },
+ { SRC_LINE,
+ .name = "arm_ac57::CPU_CYCLES:k:u",
+ .ret = PFM_SUCCESS,
+ .count = 1,
+ .codes[0] = 0x8000011,
+ .fstr = "arm_ac57::CPU_CYCLES:k=1:u=1:hv=0",
+ },
+ { SRC_LINE,
+ .name = "arm_ac57::INST_RETIRED",
+ .ret = PFM_SUCCESS,
+ .count = 1,
+ .codes[0] = 0x8000008,
+ .fstr = "arm_ac57::INST_RETIRED:k=1:u=1:hv=0",
+ },
+};
+#define NUM_TEST_EVENTS (int)(sizeof(arm64_test_events)/sizeof(test_event_t))
+
+static int check_test_events(FILE *fp)
+{
+ const test_event_t *e;
+ char *fstr;
+ uint64_t *codes;
+ int count, i, j;
+ int ret, errors = 0;
+
+ for (i = 0, e = arm64_test_events; i < NUM_TEST_EVENTS; i++, e++) {
+ codes = NULL;
+ count = 0;
+ fstr = NULL;
+ ret = pfm_get_event_encoding(e->name, PFM_PLM0 | PFM_PLM3, &fstr, NULL, &codes, &count);
+ if (ret != e->ret) {
+ fprintf(fp,"Line %d, Event%d %s, ret=%s(%d) expected %s(%d)\n", e->line, i, e->name, pfm_strerror(ret), ret, pfm_strerror(e->ret), e->ret);
+ errors++;
+ } else {
+ if (ret != PFM_SUCCESS) {
+ if (fstr) {
+ fprintf(fp,"Line %d, Event%d %s, expected fstr NULL but it is not\n", e->line, i, e->name);
+ errors++;
+ }
+ if (count != 0) {
+ fprintf(fp,"Line %d, Event%d %s, expected count=0 instead of %d\n", e->line, i, e->name, count);
+ errors++;
+ }
+ if (codes) {
+ fprintf(fp,"Line %d, Event%d %s, expected codes[] NULL but it is not\n", e->line, i, e->name);
+ errors++;
+ }
+ } else {
+ if (count != e->count) {
+ fprintf(fp,"Line %d, Event%d %s, count=%d expected %d\n", e->line, i, e->name, count, e->count);
+ errors++;
+ }
+ for (j=0; j < count; j++) {
+ if (codes[j] != e->codes[j]) {
+ fprintf(fp,"Line %d, Event%d %s, codes[%d]=%#"PRIx64" expected %#"PRIx64"\n", e->line, i, e->name, j, codes[j], e->codes[j]);
+ errors++;
+ }
+ }
+ if (e->fstr && strcmp(fstr, e->fstr)) {
+ fprintf(fp,"Line %d, Event%d %s, fstr=%s expected %s\n", e->line, i, e->name, fstr, e->fstr);
+ errors++;
+ }
+ }
+ }
+ if (codes)
+ free(codes);
+ if (fstr)
+ free(fstr);
+ }
+ printf("\t %d ARM64 events: %d errors\n", i, errors);
+ return errors;
+}
+
+int
+validate_arch(FILE *fp)
+{
+ return check_test_events(fp);
+}
commit b95de18085dd74738752341e0004b3dd11f00a53
Author: Stephane Eranian <eranian@gmail.com>
Date: Mon May 12 14:15:57 2014 +0200
Add ARM Cortex A57 documentation
Signed-off-by: Stephane Eranian <eranian@gmail.com>
diff --git a/docs/Makefile b/docs/Makefile
index ecf6769..9b79ec7 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -76,7 +76,11 @@ endif
endif
ifeq ($(CONFIG_PFMLIB_ARCH_ARM),y)
-ARCH_MAN += libpfm_arm_ac15.3 libpfm_arm_ac8.3 libpfm_arm_ac9.3 libpfm_arm_qcom_krait.3
+ARCH_MAN += libpfm_arm_ac57.3 libpfm_arm_ac15.3 libpfm_arm_ac8.3 libpfm_arm_ac9.3 libpfm_arm_qcom_krait.3
+endif
+
+ifeq ($(CONFIG_PFMLIB_ARCH_ARM64),y)
+ARCH_MAN += libpfm_arm_ac57.3
endif
ifeq ($(CONFIG_PFMLIB_ARCH_MIPS),y)
diff --git a/docs/man3/libpfm_arm_ac57.3 b/docs/man3/libpfm_arm_ac57.3
new file mode 100644
index 0000000..c471ff1
--- /dev/null
+++ b/docs/man3/libpfm_arm_ac57.3
@@ -0,0 +1,36 @@
+.TH LIBPFM 4 "May, 2014" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_arm_ac57 - support for Arm Cortex A57 PMU
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: arm_ac57
+.B PMU desc: ARM Cortex A57
+.sp
+.SH DESCRIPTION
+The library supports the ARM Cortex A57 core PMU.
+
+This PMU supports 6 counters and privilege levels filtering.
+It can operate in both 32 and 64 bit modes.
+
+.SH MODIFIERS
+The following modifiers are supported on ARM Cortex A57:
+.TP
+.B u
+Measure at the user level. This corresponds to \fBPFM_PLM3\fR.
+This is a boolean modifier.
+.TP
+.B k
+Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR.
+This is a boolean modifier.
+.TP
+.B hv
+Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR.
+This is a boolean modifier.
+
+.SH AUTHORS
+.nf
+Stephane Eranian <eranian@gmail.com>
+.if
+.PP
commit 399aa947ca6f4c58acac8c6be52d2ad4e5268210
Author: Stephane Eranian <eranian@gmail.com>
Date: Fri May 16 15:42:40 2014 +0200
fix the ARM Cortex A57 detection
This patch fixes the detection of ARM Cortex A57.
Was using the wrong part number. Correct number
is 0xD07.
Signed-off-by: Stephane Eranian <eranian@gmail.com>
diff --git a/lib/pfmlib_arm_armv8.c b/lib/pfmlib_arm_armv8.c
index 880d566..4bc863b 100644
--- a/lib/pfmlib_arm_armv8.c
+++ b/lib/pfmlib_arm_armv8.c
@@ -42,7 +42,7 @@ pfm_arm_detect_cortex_a57(void *this)
return PFM_ERR_NOTSUPP;
if ((pfm_arm_cfg.implementer == 0x41) && /* ARM */
- (pfm_arm_cfg.part == 0xc00)) { /* Cortex A57 */
+ (pfm_arm_cfg.part == 0xd07)) { /* Cortex A57 */
return PFM_SUCCESS;
}
return PFM_ERR_NOTSUPP;

1171
libpfm-power8.patch
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File diff suppressed because it is too large Load Diff

21
libpfm.spec
View File

@ -9,15 +9,16 @@
%endif
Name: libpfm
Version: 4.4.0
Release: 5.217.gbca43a5%{?dist}
Version: 4.5.0
Release: 1%{?dist}
Summary: Library to encode performance events for use by perf tool
Group: System Environment/Libraries
License: MIT
URL: http://perfmon2.sourceforge.net/
Source0: %{name}-%{version}-5.217.gbca43a5.tar.gz
Source0: http://sourceforge.net/projects/perfmon2/files/libpfm4/%{name}-%{version}.tar.gz
Patch12: libpfm-ac57.patch
%if %{with python}
BuildRequires: python-devel
@ -62,6 +63,8 @@ Python bindings for libpfm4 and perf_event_open system call.
%prep
%setup -q
%patch12 -p1
%build
%if %{with python}
%global python_config CONFIG_PFMLIB_NOPYTHON=n
@ -108,16 +111,8 @@ make \
%endif
%changelog
* Wed Jan 15 2014 Lukas Berk <lberk@redhat.com> - 4.4.0-5.217.gbca43a5
- Automated weekly rawhide release
* Mon Nov 25 2013 Lukas Berk <lberk@redhat.com> - 4.4.0-3.200.g9df2031
- Automated weekly rawhide release
- Removed patch1 set
* Tue Nov 19 2013 Lukas Berk <lberk@redhat.com> - 4.4.0-3.199.g0b87987
- Automated weekly rawhide Release
- Comment out Patch1 as applied upstream
* Fri May 23 2014 William Cohen <wcohen@redhat.com> 4.5.0-1
- Rebase on libpfm-4.5.0.
* Sat Aug 03 2013 Fedora Release Engineering <rel-eng@lists.fedoraproject.org> - 4.4.0-3
- Rebuilt for https://fedoraproject.org/wiki/Fedora_20_Mass_Rebuild

2
sources
View File

@ -1 +1 @@
2b01e4f1bdec4d0b0283f0b98c942a40 libpfm-4.4.0-5.217.gbca43a5.tar.gz
8eda1e3741c8f3359a33ebd553243333 libpfm-4.5.0.tar.gz