From 0b45296c8e05940958038f7bd7db850dd265ca0f Mon Sep 17 00:00:00 2001 From: AlmaLinux RelEng Bot Date: Tue, 21 Jul 2026 08:34:37 -0400 Subject: [PATCH] import Oracle_OSS libpfm-4.13.0-11.el10_2.1 --- .gitignore | 2 +- SOURCES/libpfm-initp.patch | 31 - SOURCES/libpfm-zen4.patch | 29 - libpfm-gcc14.patch | 21 + libpfm-ibm-counters.patch | 695 ++++ libpfm-monaka-v1.1.patch | 1271 +++++++ libpfm-monaka.patch | 3189 +++++++++++++++++ ...-setup.patch => libpfm-python3-setup.patch | 0 SPECS/libpfm.spec => libpfm.spec | 178 +- sources | 1 + 10 files changed, 5323 insertions(+), 94 deletions(-) delete mode 100644 SOURCES/libpfm-initp.patch delete mode 100644 SOURCES/libpfm-zen4.patch create mode 100644 libpfm-gcc14.patch create mode 100644 libpfm-ibm-counters.patch create mode 100644 libpfm-monaka-v1.1.patch create mode 100644 libpfm-monaka.patch rename SOURCES/libpfm-python3-setup.patch => libpfm-python3-setup.patch (100%) rename SPECS/libpfm.spec => libpfm.spec (57%) create mode 100644 sources diff --git a/.gitignore b/.gitignore index 320911a..161ab7d 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1 @@ -SOURCES/libpfm-4.13.0.tar.gz +libpfm-4.13.0.tar.gz diff --git a/SOURCES/libpfm-initp.patch b/SOURCES/libpfm-initp.patch deleted file mode 100644 index 6796191..0000000 --- a/SOURCES/libpfm-initp.patch +++ /dev/null @@ -1,31 +0,0 @@ -commit 874feacbbe97fe567d3d8b1582d881d1b424dd5e -Author: William Cohen -Date: Fri Apr 14 16:07:07 2023 -0400 - - Make sure that p is set to a known value before using. - - Need to ensure that p was initialized at the start of function - gen_tracepoint_table otherwise on some architectures such as s390x - will get the following error when compiling with -Werror: - - make[1]: Entering directory '/root/rpmbuild/BUILD/libpfm-4.13.0/lib' - cc -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -march=z14 -mtune=z15 -fasynchronous-unwind-tables -fstack-clash-protection -g -Wall -Werror -Wextra -Wno-unused-parameter -I. -I/root/rpmbuild/BUILD/libpfm-4.13.0/lib/../include -DCONFIG_PFMLIB_DEBUG -DCONFIG_PFMLIB_OS_LINUX -D_REENTRANT -I. -fvisibility=hidden -DCONFIG_PFMLIB_ARCH_S390X -I. -c pfmlib_perf_event_pmu.c - pfmlib_perf_event_pmu.c: In function 'gen_tracepoint_table': - pfmlib_perf_event_pmu.c:434:35: error: 'p' may be used uninitialized in this function [-Werror=maybe-uninitialized] - 434 | p->modmsk = 0; - | ~~~~~~~~~~^~~ - cc1: all warnings being treated as errors - -diff --git a/lib/pfmlib_perf_event_pmu.c b/lib/pfmlib_perf_event_pmu.c -index 637c5b1..8f7d7d1 100644 ---- a/lib/pfmlib_perf_event_pmu.c -+++ b/lib/pfmlib_perf_event_pmu.c -@@ -361,7 +361,7 @@ gen_tracepoint_table(void) - { - DIR *dir1, *dir2; - struct dirent *d1, *d2; -- perf_event_t *p; -+ perf_event_t *p = NULL; - perf_umask_t *um; - char d2path[MAXPATHLEN]; - char idpath[MAXPATHLEN]; diff --git a/SOURCES/libpfm-zen4.patch b/SOURCES/libpfm-zen4.patch deleted file mode 100644 index e319e32..0000000 --- a/SOURCES/libpfm-zen4.patch +++ /dev/null @@ -1,29 +0,0 @@ -commit 1befa3d200cc17d5a278fcb2f597c4876c58f949 -Author: Stephane Eranian -Date: Tue Apr 25 00:35:41 2023 -0700 - - fix AMD Zen3/Zen4 detection - - To cover more models of Zen4. - - Signed-off-by: Stephane Eranian - -diff --git a/lib/pfmlib_amd64.c b/lib/pfmlib_amd64.c -index e51a43d..0c6702d 100644 ---- a/lib/pfmlib_amd64.c -+++ b/lib/pfmlib_amd64.c -@@ -181,10 +181,10 @@ amd64_get_revision(pfm_amd64_config_t *cfg) - } else if (cfg->family == 22) { /* family 16h */ - rev = PFM_PMU_AMD64_FAM16H; - } else if (cfg->family == 25) { /* family 19h */ -- if (cfg->model <= 0x0f || (cfg->model >= 0x20 && cfg->model <= 0x5f)) { -- rev = PFM_PMU_AMD64_FAM19H_ZEN3; -- } else if (cfg->model == 17) { -- rev = PFM_PMU_AMD64_FAM19H_ZEN4; -+ if (cfg->model >= 0x60 || (cfg->model >= 0x10 && cfg->model <= 0x1f)) { -+ rev = PFM_PMU_AMD64_FAM19H_ZEN4; -+ } else { -+ rev = PFM_PMU_AMD64_FAM19H_ZEN3; - } - } - diff --git a/libpfm-gcc14.patch b/libpfm-gcc14.patch new file mode 100644 index 0000000..9f2a62d --- /dev/null +++ b/libpfm-gcc14.patch @@ -0,0 +1,21 @@ +commit cb944829e0940d74009e09b8985b4f2139f5cb3b +Author: William Cohen +Date: Mon Jan 29 16:23:43 2024 -0500 + + Correct s390x code to avoid GCC-14 -Werror=calloc-transposed-args errors + +diff --git a/lib/pfmlib_s390x_cpumf.c b/lib/pfmlib_s390x_cpumf.c +index d8ce22d..718f5f8 100644 +--- a/lib/pfmlib_s390x_cpumf.c ++++ b/lib/pfmlib_s390x_cpumf.c +@@ -216,8 +216,8 @@ static int pfm_cpumcf_init(void *this) + break; + } + +- cpumcf_pe = calloc(sizeof(*cpumcf_pe), +- cfvn_set_count + csvn_set_count + ext_set_count); ++ cpumcf_pe = calloc(cfvn_set_count + csvn_set_count + ext_set_count, ++ sizeof(*cpumcf_pe)); + if (cpumcf_pe == NULL) + return PFM_ERR_NOMEM; + diff --git a/libpfm-ibm-counters.patch b/libpfm-ibm-counters.patch new file mode 100644 index 0000000..0896820 --- /dev/null +++ b/libpfm-ibm-counters.patch @@ -0,0 +1,695 @@ +From 964baf9d35d5f88d8422f96d8a82c672042e7064 Mon Sep 17 00:00:00 2001 +From: Thomas Richter +Date: Tue, 18 Jun 2024 11:56:18 +0200 +Subject: [PATCH] s390: Add counter definition for IBM z17 + +Add the libpfm4 s390 counter definitions for IBM z17 according +to documentation: + +SA23-2261-09:The CPU-Measurement Facility Extended Counters + Definition for z10, z196/z114, zEC12/zBC12, z13/z13s, + z14, z15, z16 and z17 + April 2025 + +https://www.ibm.com/docs/en/module_1678991624569/pdf/SA23-2261-09.pdf + +Signed-off-by: Thomas Richter +--- + lib/events/s390x_cpumf_events.h | 635 ++++++++++++++++++++++++++++++++ + lib/pfmlib_s390x_cpumf.c | 7 +- + 2 files changed, 641 insertions(+), 1 deletion(-) + +diff --git a/lib/events/s390x_cpumf_events.h b/lib/events/s390x_cpumf_events.h +index 0eeeb7e..5a0b457 100644 +--- a/lib/events/s390x_cpumf_events.h ++++ b/lib/events/s390x_cpumf_events.h +@@ -2843,6 +2843,641 @@ static const pme_cpumf_ctr_t cpumcf_z16_counters[] = { + }, + }; + ++static const pme_cpumf_ctr_t cpumcf_z17_counters[] = { ++ { ++ .ctrnum = 128, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "L1D_RO_EXCL_WRITES", ++ .desc = "A directory write to the Level-1 Data cache where" ++ " the line was originally in a Read-Only state in the" ++ " cache but has been updated to be in the Exclusive" ++ " state that allows stores to the cache line.", ++ }, ++ { ++ .ctrnum = 129, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DTLB2_WRITES", ++ .desc = "A translation has been written into The Translation" ++ " Lookaside Buffer 2 (TLB2) and the request was made" ++ " by the Level-1 Data cache. This is a replacement" ++ " for what was provided for the DTLB on z13 and prior" ++ " machines.", ++ }, ++ { ++ .ctrnum = 130, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DTLB2_MISSES", ++ .desc = "A TLB2 miss is in progress for a request made by" ++ " the Level-1 Data cache. Incremented by one for" ++ " every TLB2 miss in progress for the Level-1 Data" ++ " cache on this cycle. This is a replacement for what" ++ " was provided for the DTLB on z13 and prior" ++ " machines.", ++ }, ++ { ++ .ctrnum = 131, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "CRSTE_1MB_WRITES", ++ .desc = "A translation entry was written into the Combined" ++ " Region and Segment Table Entry array in the Level-2" ++ " TLB for a one-megabyte page.", ++ }, ++ { ++ .ctrnum = 132, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DTLB2_GPAGE_WRITES", ++ .desc = "A translation entry for a two-gigabyte page was" ++ " written into the Level-2 TLB.", ++ }, ++ { ++ .ctrnum = 134, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ITLB2_WRITES", ++ .desc = "A translation entry has been written into the" ++ " Translation Lookaside Buffer 2 (TLB2) and the" ++ " request was made by the Level-1 Instruction cache." ++ " This is a replacement for what was provided for the" ++ " ITLB on z13 and prior machines.", ++ }, ++ { ++ .ctrnum = 135, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ITLB2_MISSES", ++ .desc = "A TLB2 miss is in progress for a request made by" ++ " the Level-1 Instruction cache. Incremented by one" ++ " for every TLB2 miss in progress for the Level-1" ++ " Instruction cache in a cycle. This is a replacement" ++ " for what was provided for the ITLB on z13 and prior" ++ " machines.", ++ }, ++ { ++ .ctrnum = 137, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TLB2_PTE_WRITES", ++ .desc = "A translation entry was written into the Page Table" ++ " Entry array in the Level-2 TLB.", ++ }, ++ { ++ .ctrnum = 138, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TLB2_CRSTE_WRITES", ++ .desc = "Translation entries were written into the Combined" ++ " Region and Segment Table Entry array and the Page" ++ " Table Entry array in the Level-2 TLB.", ++ }, ++ { ++ .ctrnum = 139, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TLB2_ENGINES_BUSY", ++ .desc = "The number of Level-2 TLB translation engines busy" ++ " in a cycle.", ++ }, ++ { ++ .ctrnum = 140, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TX_C_TEND", ++ .desc = "A TEND instruction has completed in a constrained" ++ " transactional-execution mode.", ++ }, ++ { ++ .ctrnum = 141, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TX_NC_TEND", ++ .desc = "A TEND instruction has completed in a non-" ++ " constrained transactional-execution mode.", ++ }, ++ { ++ .ctrnum = 143, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "L1C_TLB2_MISSES", ++ .desc = "Increments by one for any cycle where a Level-1" ++ " cache or Level-2 TLB miss is in progress.", ++ }, ++ { ++ .ctrnum = 145, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_REQ", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from the requestors Level-2 cache.", ++ }, ++ { ++ .ctrnum = 146, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_REQ_IV", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from the requestors Level-2 cache with" ++ " intervention.", ++ }, ++ { ++ .ctrnum = 147, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_REQ_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from the requestors Level-2 cache after using" ++ " chip level horizontal persistence, Chip-HP hit.", ++ }, ++ { ++ .ctrnum = 148, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_REQ_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from the requestors Level-2 cache after using" ++ " drawer level horizontal persistence, Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 149, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_CHIP", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache.", ++ }, ++ { ++ .ctrnum = 150, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_CHIP_IV", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache with intervention.", ++ }, ++ { ++ .ctrnum = 151, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_CHIP_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache after using chip" ++ " level horizontal persistence, Chip-HP hit.", ++ }, ++ { ++ .ctrnum = 152, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_CHIP_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache after using drawer" ++ " level horizontal persistence, Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 153, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_MODULE", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Module Level-2 cache.", ++ }, ++ { ++ .ctrnum = 154, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_DRAWER", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Drawer Level-2 cache.", ++ }, ++ { ++ .ctrnum = 155, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_OFF_DRAWER", ++ .desc = "A directory write to the Level-1 Data cache" ++ " directory where the returned cache line was sourced" ++ " from an Off-Drawer Level-2 cache.", ++ }, ++ { ++ .ctrnum = 156, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_CHIP_MEMORY", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from On-Chip memory.", ++ }, ++ { ++ .ctrnum = 157, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_MODULE_MEMORY", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from On-Module memory.", ++ }, ++ { ++ .ctrnum = 158, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_ON_DRAWER_MEMORY", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from On-Drawer memory.", ++ }, ++ { ++ .ctrnum = 159, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DCW_OFF_DRAWER_MEMORY", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from Off-Drawer memory.", ++ }, ++ { ++ .ctrnum = 160, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_ON_MODULE_IV", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from an On-Module Level-2" ++ " cache with intervention.", ++ }, ++ { ++ .ctrnum = 161, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_ON_MODULE_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from an On-Module Level-2" ++ " cache after using chip level horizontal" ++ " persistence, Chip-HP hit.", ++ }, ++ { ++ .ctrnum = 162, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_ON_MODULE_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from an On-Module Level-2" ++ " cache after using drawer level horizontal" ++ " persistence, Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 163, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_ON_DRAWER_IV", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from an On-Drawer Level-2" ++ " cache with intervention.", ++ }, ++ { ++ .ctrnum = 164, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_ON_DRAWER_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " instruction cache directory where the returned" ++ " cache line was sourced from an On-Drawer Level-2" ++ " cache after using chip level horizontal" ++ " persistence, Chip-HP hit.", ++ }, ++ { ++ .ctrnum = 165, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_ON_DRAWER_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " instruction cache directory where the returned" ++ " cache line was sourced from an On-Drawer Level-2" ++ " cache after using drawer level horizontal" ++ " persistence, Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 166, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_OFF_DRAWER_IV", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " instruction cache directory where the returned" ++ " cache line was sourced from an Off-Drawer Level-2" ++ " cache with intervention.", ++ }, ++ { ++ .ctrnum = 167, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_OFF_DRAWER_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " instruction cache directory where the returned" ++ " cache line was sourced from an Off-Drawer Level-2" ++ " cache after using chip level horizontal" ++ " persistence, Chip-HP hit.", ++ }, ++ { ++ .ctrnum = 168, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "IDCW_OFF_DRAWER_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Data or Level-1" ++ " Instruction cache directory where the returned" ++ " cache line was sourced from an Off-Drawer Level-2" ++ " cache after using drawer level horizontal" ++ " persistence, Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 169, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_REQ", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " the requestors Level-2 cache.", ++ }, ++ { ++ .ctrnum = 170, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_REQ_IV", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from the requestors Level-2 cache with" ++ " intervention.", ++ }, ++ { ++ .ctrnum = 171, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_REQ_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from the requestors Level-2 cache after using" ++ " chip level horizontal persistence, Chip-HP hit.", ++ }, ++ { ++ .ctrnum = 172, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_REQ_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from the requestors Level-2 cache after using" ++ " drawer level horizontal persistence, Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 173, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_CHIP", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache.", ++ }, ++ { ++ .ctrnum = 174, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_CHIP_IV", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache with intervention.", ++ }, ++ { ++ .ctrnum = 175, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_CHIP_CHIP_HIT", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip Level-2 cache after using chip" ++ " level horizontal persistence, Chip-HP hit.", ++ }, ++ { ++ .ctrnum = 176, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_CHIP_DRAWER_HIT", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Chip level 2 cache after using drawer" ++ " level horizontal persistence, Drawer-HP hit.", ++ }, ++ { ++ .ctrnum = 177, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_MODULE", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Module Level-2 cache.", ++ }, ++ { ++ .ctrnum = 178, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_ON_DRAWER", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from an On-Drawer Level-2 cache.", ++ }, ++ { ++ .ctrnum = 179, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "ICW_OFF_DRAWER", ++ .desc = "A directory write to the Level-1 Instruction cache" ++ " directory where the returned cache line was sourced" ++ " from an Off-Drawer Level-2 cache.", ++ }, ++ { ++ .ctrnum = 202, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "CYCLES_SAMETHRD", ++ .desc = "The number of cycles the CPU is not in wait state" ++ " and the CPU is running by itself on the Core.", ++ }, ++ { ++ .ctrnum = 203, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "CYCLES_DIFFTHRD", ++ .desc = "The number of cycles the CPU is not in wait state" ++ " and the CPU is running with another thread on the" ++ " Core.", ++ }, ++ { ++ .ctrnum = 204, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "INST_SAMETHRD", ++ .desc = "The number of instructions executed on the CPU and" ++ " the CPU is running by itself on the Core.", ++ }, ++ { ++ .ctrnum = 205, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "INST_DIFFTHRD", ++ .desc = "The number of instructions executed on the CPU and" ++ " the CPU is running with another thread on the Core.", ++ }, ++ { ++ .ctrnum = 206, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "WRONG_BRANCH_PREDICTION", ++ .desc = "A count of the number of branches that were" ++ " predicted incorrectly by the branch prediction" ++ " logic in the Core. This includes incorrectly" ++ " predicted branches that are executed in Firmware." ++ " Examples of instructions implemented in Firmware" ++ " are complicated instructions like MVCL (Move" ++ " Character Long) and PC (Program Call).", ++ }, ++ { ++ .ctrnum = 225, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "VX_BCD_EXECUTION_SLOTS", ++ .desc = "Count of floating point execution slots used for" ++ " finished vector arithmetic Binary Coded Decimal" ++ " instructions. Instructions: VAP, VSP, VMP, VMSP," ++ " VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ," ++ " VUPKZ, VCVB, VCVBG, VCVD, VCVDG, VSCHP, VSCSHP," ++ " VCSPH, VCLZDP, VPKZR, VSRPR, VUPKZH, VUPKZL, VTZ," ++ " VUPH, VUPL, VCVBX, VCVDX.", ++ }, ++ { ++ .ctrnum = 226, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DECIMAL_INSTRUCTIONS", ++ .desc = "Decimal instruction dispatched. Instructions: CVB," ++ " CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP, TP.", ++ }, ++ { ++ .ctrnum = 232, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "LAST_HOST_TRANSLATIONS", ++ .desc = "Last Host Translation done.", ++ }, ++ { ++ .ctrnum = 244, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TX_NC_TABORT", ++ .desc = "A transaction abort has occurred in a non-" ++ " constrained transactional-execution mode.", ++ }, ++ { ++ .ctrnum = 245, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TX_C_TABORT_NO_SPECIAL", ++ .desc = "A transaction abort has occurred in a constrained" ++ " transactional-execution mode and the CPU is not" ++ " using any special logic to allow the transaction to" ++ " complete.", ++ }, ++ { ++ .ctrnum = 246, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "TX_C_TABORT_SPECIAL", ++ .desc = "A transaction abort has occurred in a constrained" ++ " transactional-execution mode and the CPU is using" ++ " special logic to allow the transaction to complete.", ++ }, ++ { ++ .ctrnum = 248, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DFLT_ACCESS", ++ .desc = "Cycles CPU spent obtaining access to Deflate unit.", ++ }, ++ { ++ .ctrnum = 253, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DFLT_CYCLES", ++ .desc = "Cycles CPU is using Deflate unit.", ++ }, ++ { ++ .ctrnum = 256, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "SORTL", ++ .desc = "Increments by one for every SORT LISTS (SORTL)" ++ " instruction executed.", ++ }, ++ { ++ .ctrnum = 265, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DFLT_CC", ++ .desc = "Increments by one for every DEFLATE CONVERSION CALL" ++ " (DFLTCC) instruction executed.", ++ }, ++ { ++ .ctrnum = 266, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "DFLT_CCFINISH", ++ .desc = "Increments by one for every DEFLATE CONVERSION CALL" ++ " (DFLTCC) instruction executed that ended in" ++ " Condition Codes 0, 1 or 2.", ++ }, ++ { ++ .ctrnum = 267, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_INVOCATIONS", ++ .desc = "Increments by one for every NEURAL NETWORK" ++ " PROCESSING ASSIST (NNPA) instruction executed.", ++ }, ++ { ++ .ctrnum = 268, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_COMPLETIONS", ++ .desc = "Increments by one for every NEURAL NETWORK" ++ " PROCESSING ASSIST (NNPA) instruction executed that" ++ " ended in Condition Code 0.", ++ }, ++ { ++ .ctrnum = 269, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_WAIT_LOCK", ++ .desc = "Cycles CPU spent obtaining access to IBM Z" ++ " Integrated Accelerator for AI.", ++ }, ++ { ++ .ctrnum = 270, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_HOLD_LOCK", ++ .desc = "Cycles CPU is using IBM Z Integrated Accelerator" ++ " for AI.", ++ }, ++ { ++ .ctrnum = 272, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_INST_ONCHIP", ++ .desc = "A NEURAL NETWORK PROCESSING ASSIST (NNPA)" ++ " instruction has used the Local On-Chip IBM Z" ++ " Integrated Accelerator for AI during its execution", ++ }, ++ { ++ .ctrnum = 273, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_INST_OFFCHIP", ++ .desc = "A NEURAL NETWORK PROCESSING ASSIST (NNPA)" ++ " instruction has used an Off-Chip IBM Z Integrated" ++ " Accelerator for AI during its execution.", ++ }, ++ { ++ .ctrnum = 274, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_INST_DIFF", ++ .desc = "A NEURAL NETWORK PROCESSING ASSIST (NNPA)" ++ " instruction has used a different IBM Z Integrated" ++ " Accelerator for AI since it was last executed.", ++ }, ++ { ++ .ctrnum = 276, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_4K_PREFETCH", ++ .desc = "Number of 4K prefetches done for a remote IBM Z" ++ " Integated Accelerator for AI.", ++ }, ++ { ++ .ctrnum = 277, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_COMPL_LOCK", ++ .desc = "A PERFORM LOCKED OPERATION (PLO) has completed.", ++ }, ++ { ++ .ctrnum = 278, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_RETRY_LOCK", ++ .desc = "A PERFORM LOCKED OPERATION (PLO) has been retried and" ++ " the CPU did not use any special logic to allow the" ++ " PLO to complete.", ++ }, ++ { ++ .ctrnum = 279, ++ .ctrset = CPUMF_CTRSET_EXTENDED, ++ .name = "NNPA_RETRY_LOCK_WITH_PLO", ++ .desc = "A PERFORM LOCKED OPERATION (PLO) has been retried and" ++ " the CPU is using special logic to allow PLO to" ++ " complete.", ++ }, ++ { ++ .ctrnum = 448, ++ .ctrset = CPUMF_CTRSET_MT_DIAG, ++ .name = "MT_DIAG_CYCLES_ONE_THR_ACTIVE", ++ .desc = "Cycle count with one thread active", ++ }, ++ { ++ .ctrnum = 449, ++ .ctrset = CPUMF_CTRSET_MT_DIAG, ++ .name = "MT_DIAG_CYCLES_TWO_THR_ACTIVE", ++ .desc = "Cycle count with two threads active", ++ }, ++}; ++ + static const pme_cpumf_ctr_t cpumsf_counters[] = { + { + .ctrnum = 720896, +diff --git a/lib/pfmlib_s390x_cpumf.c b/lib/pfmlib_s390x_cpumf.c +index 718f5f8..35c1853 100644 +--- a/lib/pfmlib_s390x_cpumf.c ++++ b/lib/pfmlib_s390x_cpumf.c +@@ -168,7 +168,7 @@ static int pfm_cpumcf_init(void *this) + /* counters based on second version number */ + csvn_set = cpumcf_svn_generic_counters; + csvn_set_count = LIBPFM_ARRAY_SIZE(cpumcf_svn_generic_counters); +- if (csvn < 6) /* Crypto counter set enlarged for SVN == 6 */ ++ if (csvn < 6) /* Crypto counter set enlarged for SVN == 6 7 and 8 */ + csvn_set_count -= CPUMF_SVN6_ECC; + + /* check and assign a machine-specific extended counter set */ +@@ -208,6 +208,11 @@ static int pfm_cpumcf_init(void *this) + ext_set = cpumcf_z16_counters; + ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z16_counters); + break; ++ case 9175: /* IBM Machine types 9175 and 9176 */ ++ case 9176: ++ ext_set = cpumcf_z17_counters; ++ ext_set_count = LIBPFM_ARRAY_SIZE(cpumcf_z17_counters); ++ break; + default: + /* No extended counter set for this machine type or there + * was an error retrieving the machine type */ +-- +2.52.0 + diff --git a/libpfm-monaka-v1.1.patch b/libpfm-monaka-v1.1.patch new file mode 100644 index 0000000..b1cebf0 --- /dev/null +++ b/libpfm-monaka-v1.1.patch @@ -0,0 +1,1271 @@ +From 861ce2a29b214ce182e105f428f55cdc2ed51af1 Mon Sep 17 00:00:00 2001 +From: "Kotaro, Tokai" +Date: Wed, 18 Jun 2025 12:01:43 +0900 +Subject: [PATCH] The FUJITSU-MONAKA PMU events have been changed to match the + v1.1 specification and v1.0 errata. + +FUJITSU-MONAKA Specification URL: +https://github.com/fujitsu/FUJITSU-MONAKA + +The changed events are as follows: + +Removed events: + +- L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT + +Added events: + +- ASE_FP_VREDUCE_SPEC +- SVE_FP_PREDUCE_SPEC +- ASE_FP_BF16_MIN_SPEC +- ASE_FP_FP8_MIN_SPEC +- ASE_SVE_FP_BF16_MIN_SPEC +- ASE_SVE_FP_FP8_MIN_SPEC +- SVE_FP_BF16_MIN_SPEC +- SVE_FP_FP8_MIN_SPEC +- FP_BF16_MIN_SPEC +- FP_FP8_MIN_SPEC +- FP_BF16_FIXED_MIN_OPS_SPEC +- FP_FP8_FIXED_MIN_OPS_SPEC +- FP_BF16_SCALE_MIN_OPS_SPEC +- FP_FP8_SCALE_MIN_OPS_SPEC + +Renamed events: + +- L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM => L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT +- L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_RD => L2D_CACHE_REFILL_L3D_MISS_DM_RD_PFTGT_HIT +- L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_WR => L2D_CACHE_REFILL_L3D_MISS_DM_WR_PFTGT_HIT +- L2D_CACHE_REFILL_L3D_MISS_L_MEM => L2D_CACHE_REFILL_L3D_MISS_DM_L_MEM +- L2D_CACHE_REFILL_L3D_MISS_FR_MEM => L2D_CACHE_REFILL_L3D_MISS_DM_FR_MEM +- L2D_CACHE_REFILL_L3D_MISS_L_L2 => L2D_CACHE_REFILL_L3D_MISS_DM_L_L2 +- L2D_CACHE_REFILL_L3D_MISS_NR_L2 => L2D_CACHE_REFILL_L3D_MISS_DM_NR_L2 +- L2D_CACHE_REFILL_L3D_MISS_NR_L3 => L2D_CACHE_REFILL_L3D_MISS_DM_NR_L3 +- L2D_CACHE_REFILL_L3D_MISS_FR_L2 => L2D_CACHE_REFILL_L3D_MISS_DM_FR_L2 +- L2D_CACHE_REFILL_L3D_MISS_FR_L3 => L2D_CACHE_REFILL_L3D_MISS_DM_FR_L3 + +Description changed events: + +- STALL_BACKEND +- LL_CACHE_MISS_RD +- L2D_CACHE_RD +- L2D_CACHE_WR +- L2D_CACHE_REFILL_RD +- L2D_CACHE_REFILL_WR +- CSDB_SPEC +- EXC_SMC +- FP_MV_SPEC +- IEL_SPEC +- IREG_SPEC +- BC_LD_SPEC +- LD_COMP_WAIT +- LD_COMP_WAIT_EX +- L1_PIPE_COMP_GATHER_2FLOW +- L1_PIPE_COMP_GATHER_1FLOW +- L1_PIPE_COMP_GATHER_0FLOW +- L2D_CACHE_HWPRF_ADJACENT +- L2D_CACHE_REFILL_L3D_CACHE_PRF +- L2D_CACHE_REFILL_L3D_CACHE_HWPRF +- L2D_CACHE_REFILL_L3D_MISS_PRF +- L2D_CACHE_REFILL_L3D_MISS_HWPRF +- L2D_CACHE_REFILL_L3D_HIT_PRF +- L2D_CACHE_REFILL_L3D_HIT_HWPRF +- L1I_TLB_REFILL_4K +- L1I_TLB_REFILL_64K +- L1I_TLB_REFILL_2M +- L1I_TLB_REFILL_32M +- L1I_TLB_REFILL_512M +- L1I_TLB_REFILL_1G +- L1I_TLB_REFILL_16G +- L1D_TLB_REFILL_4K +- L1D_TLB_REFILL_64K +- L1D_TLB_REFILL_2M +- L1D_TLB_REFILL_32M +- L1D_TLB_REFILL_512M +- L1D_TLB_REFILL_1G +- L1D_TLB_REFILL_16G +- L2I_TLB_REFILL_4K +- L2I_TLB_REFILL_64K +- L2I_TLB_REFILL_2M +- L2I_TLB_REFILL_32M +- L2I_TLB_REFILL_512M +- L2I_TLB_REFILL_1G +- L2I_TLB_REFILL_16G +- L2D_TLB_REFILL_4K +- L2D_TLB_REFILL_64K +- L2D_TLB_REFILL_2M +- L2D_TLB_REFILL_32M +- L2D_TLB_REFILL_512M +- L2D_TLB_REFILL_1G +- L2D_TLB_REFILL_16G +- L2D_CACHE_LMISS_RD +- L3D_CACHE_LMISS_RD +- ASE_INST_SPEC +- ASE_SVE_INST_SPEC +- UOP_SPEC +- ASE_SVE_FP_SPEC +- ASE_SVE_FP_HP_SPEC +- ASE_SVE_FP_SP_SPEC +- ASE_SVE_FP_DP_SPEC +- ASE_SVE_FP_DIV_SPEC +- ASE_SVE_FP_SQRT_SPEC +- FP_FMA_SPEC +- ASE_SVE_FP_FMA_SPEC +- FP_MUL_SPEC +- ASE_SVE_FP_MUL_SPEC +- FP_ADDSUB_SPEC +- ASE_SVE_FP_ADDSUB_SPEC +- ASE_FP_RECPE_SPEC +- SVE_FP_RECPE_SPEC +- ASE_SVE_FP_RECPE_SPEC +- ASE_SVE_FP_CVT_SPEC +- SVE_FP_AREDUCE_SPEC +- ASE_FP_PREDUCE_SPEC +- ASE_SVE_FP_VREDUCE_SPEC +- ASE_INT_SPEC +- SVE_INT_SPEC +- ASE_SVE_INT_SPEC +- ASE_SVE_INT_MUL_SPEC +- SVE_INT_MULH64_SPEC +- NONFP_SPEC +- ASE_NONFP_SPEC +- SVE_NONFP_SPEC +- ASE_SVE_NONFP_SPEC +- ASE_SVE_INT_VREDUCE_SPEC +- ASE_SVE_LD_SPEC +- ASE_SVE_ST_SPEC +- ASE_SVE_LD_MULTI_SPEC +- ASE_SVE_ST_MULTI_SPEC +- FP_SCALE_OPS_SPEC +- FP_FIXED_OPS_SPEC +- FP_HP_SCALE_OPS_SPEC +- FP_HP_FIXED_OPS_SPEC +- FP_SP_SCALE_OPS_SPEC +- FP_SP_FIXED_OPS_SPEC +- FP_DP_SCALE_OPS_SPEC +- FP_DP_FIXED_OPS_SPEC +- L1I_CACHE_HWPRF +- L1D_CACHE_HWPRF +- L2D_CACHE_HWPRF +- STALL_BACKEND_L2D +- L1I_CACHE_REFILL_HWPRF +- L1D_CACHE_REFILL_HWPRF +- L2D_CACHE_REFILL_HWPRF +- L2D_CACHE_HIT_RD +- L2D_CACHE_HIT_WR +- L2D_CACHE_HIT +- L1I_CACHE_PRF +- L1D_CACHE_PRF +- L2D_CACHE_PRF +- L1I_CACHE_REFILL_PRF +- L1D_CACHE_REFILL_PRF +- L2D_CACHE_REFILL_PRF +- L1D_CACHE_REFILL_PERCYC +- L2D_CACHE_REFILL_PERCYC +- L1I_CACHE_REFILL_PERCYC + +Signed-off-by: Kotaro, Tokai +--- + lib/events/arm_fujitsu_monaka_events.h | 368 +++++++++++++++---------- + 1 file changed, 223 insertions(+), 145 deletions(-) + +diff --git a/lib/events/arm_fujitsu_monaka_events.h b/lib/events/arm_fujitsu_monaka_events.h +index 00c3e4f..4a97e7d 100644 +--- a/lib/events/arm_fujitsu_monaka_events.h ++++ b/lib/events/arm_fujitsu_monaka_events.h +@@ -153,7 +153,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "STALL_BACKEND", + .modmsk = ARMV9_ATTRS, + .code = 0x0024, +- .desc = "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because the backend is unable to accept any operations.", ++ .desc = "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because the backend is unable to accept any operation.", + }, + { + .name = "L1D_TLB", +@@ -219,7 +219,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "LL_CACHE_MISS_RD", + .modmsk = ARMV9_ATTRS, + .code = 0x0037, +- .desc = "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events.", ++ .desc = "This event counts access counted by L3D_CACHE that is not completed by the L3 cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events. Note: This event may count inaccurately.", + }, + { + .name = "L1D_CACHE_LMISS_RD", +@@ -291,25 +291,25 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L2D_CACHE_RD", + .modmsk = ARMV9_ATTRS, + .code = 0x0050, +- .desc = "This event counts L2D CACHE caused by read access.", ++ .desc = "This event counts L2D_CACHE caused by read access.", + }, + { + .name = "L2D_CACHE_WR", + .modmsk = ARMV9_ATTRS, + .code = 0x0051, +- .desc = "This event counts L2D CACHE caused by write access.", ++ .desc = "This event counts L2D_CACHE caused by write access.", + }, + { + .name = "L2D_CACHE_REFILL_RD", + .modmsk = ARMV9_ATTRS, + .code = 0x0052, +- .desc = "This event counts L2D CACHE_REFILL caused by read access.", ++ .desc = "This event counts L2D_CACHE_REFILL caused by read access.", + }, + { + .name = "L2D_CACHE_REFILL_WR", + .modmsk = ARMV9_ATTRS, + .code = 0x0053, +- .desc = "This event counts L2D CACHE_REFILL caused by write access.", ++ .desc = "This event counts L2D_CACHE_REFILL caused by write access.", + }, + { + .name = "L2D_CACHE_WB_VICTIM", +@@ -423,7 +423,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "CSDB_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x007f, +- .desc = "This event counts speculatively executed control speculation barrier instructions.", ++ .desc = "This event counts architecturally executed control speculation barrier instructions.", + }, + { + .name = "EXC_UNDEF", +@@ -465,7 +465,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "EXC_SMC", + .modmsk = ARMV9_ATTRS, + .code = 0x0088, +- .desc = "This event counts only Secure Monitor Call exceptions. The counter does not increment on SMC instructions trapped as a Hyp Trap exception.", ++ .desc = "This event counts only Secure Monitor Call exceptions. This event does not increment on SMC instructions trapped as a Hyp Trap exception.", + }, + { + .name = "EXC_HVC", +@@ -483,7 +483,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "FP_MV_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x0105, +- .desc = "This event counts architecturally executed floating-point move operations.", ++ .desc = "This event counts architecturally executed floating-point move operation.", + }, + { + .name = "PRD_SPEC", +@@ -495,13 +495,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "IEL_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x0109, +- .desc = "This event counts architecturally executed inter-element manipulation operations.", ++ .desc = "This event counts architecturally executed inter-element manipulation operation.", + }, + { + .name = "IREG_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x010a, +- .desc = "This event counts architecturally executed inter-register manipulation operations.", ++ .desc = "This event counts architecturally executed inter-register manipulation operation.", + }, + { + .name = "FP_LD_SPEC", +@@ -519,7 +519,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "BC_LD_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x011a, +- .desc = "This event counts architecturally executed SIMD broadcast floating-point load operations.", ++ .desc = "This event counts architecturally executed SIMD broadcast floating-point load operation.", + }, + { + .name = "DCZVA_SPEC", +@@ -567,13 +567,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "LD_COMP_WAIT", + .modmsk = ARMV9_ATTRS, + .code = 0x0184, +- .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access.", ++ .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache, L3 cache and memory access.", + }, + { + .name = "LD_COMP_WAIT_EX", + .modmsk = ARMV9_ATTRS, + .code = 0x0185, +- .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access.", ++ .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache, L3 cache and memory access.", + }, + { + .name = "LD_COMP_WAIT_PFP_BUSY", +@@ -993,19 +993,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L1_PIPE_COMP_GATHER_2FLOW", + .modmsk = ARMV9_ATTRS, + .code = 0x02b0, +- .desc = "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined.", ++ .desc = "This event counts the number of times where 2 elements of the gather instructions became 2-flows because 2 elements could not be combined.", + }, + { + .name = "L1_PIPE_COMP_GATHER_1FLOW", + .modmsk = ARMV9_ATTRS, + .code = 0x02b1, +- .desc = "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined.", ++ .desc = "This event counts the number of times where 2 elements of the gather instructions became 1-flow because 2 elements could be combined.", + }, + { + .name = "L1_PIPE_COMP_GATHER_0FLOW", + .modmsk = ARMV9_ATTRS, + .code = 0x02b2, +- .desc = "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0.", ++ .desc = "This event counts the number of times where 2 elements of the gather instructions became 0-flow because both predicate values are 0.", + }, + { + .name = "L1_PIPE_COMP_SCATTER_1FLOW", +@@ -1047,7 +1047,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L2D_CACHE_HWPRF_ADJACENT", + .modmsk = ARMV9_ATTRS, + .code = 0x0305, +- .desc = "This event counts L2D_CACHE caused by hardware adjacent prefetch access.", ++ .desc = "This event counts L2D_CACHE caused by hardware adjacent prefetch.", + }, + { + .name = "L2D_CACHE_REFILL_DM", +@@ -1131,19 +1131,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L2D_CACHE_REFILL_L3D_CACHE_PRF", + .modmsk = ARMV9_ATTRS, + .code = 0x0394, +- .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by prefetch access.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch or software prefetch.", + }, + { + .name = "L2D_CACHE_REFILL_L3D_CACHE_HWPRF", + .modmsk = ARMV9_ATTRS, + .code = 0x0395, +- .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch access.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch.", + }, + { + .name = "L2D_CACHE_REFILL_L3D_MISS", + .modmsk = ARMV9_ATTRS, + .code = 0x0396, +- .desc = "This event counts operations that cause a miss of the L3 cache.", ++ .desc = "This event counts operations that cause a miss of the L3 cache. Note: This event may count inaccurately.", + }, + { + .name = "L2D_CACHE_REFILL_L3D_MISS_DM", +@@ -1167,19 +1167,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L2D_CACHE_REFILL_L3D_MISS_PRF", + .modmsk = ARMV9_ATTRS, + .code = 0x039a, +- .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by prefetch access.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch or software prefetch. Note: This event may count inaccurately.", + }, + { + .name = "L2D_CACHE_REFILL_L3D_MISS_HWPRF", + .modmsk = ARMV9_ATTRS, + .code = 0x039b, +- .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch access.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch. Note: This event may count inaccurately.", + }, + { + .name = "L2D_CACHE_REFILL_L3D_HIT", + .modmsk = ARMV9_ATTRS, + .code = 0x039c, +- .desc = "This event counts operations that cause a hit of the L3 cache.", ++ .desc = "This event counts operations that cause a hit of the L3 cache. Note: This event may count inaccurately.", + }, + { + .name = "L2D_CACHE_REFILL_L3D_HIT_DM", +@@ -1203,79 +1203,73 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L2D_CACHE_REFILL_L3D_HIT_PRF", + .modmsk = ARMV9_ATTRS, + .code = 0x03a0, +- .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by prefetch access.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch or software prefetch. Note: This event may count inaccurately.", + }, + { + .name = "L2D_CACHE_REFILL_L3D_HIT_HWPRF", + .modmsk = ARMV9_ATTRS, + .code = 0x03a1, +- .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch access.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch. Note: This event may count inaccurately.", + }, + { +- .name = "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT", +- .modmsk = ARMV9_ATTRS, +- .code = 0x03a2, +- .desc = "This event counts the number of L3 cache misses where the requests hit the PFTGT buffer.", +- }, +- { +- .name = "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM", ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT", + .modmsk = ARMV9_ATTRS, + .code = 0x03a3, +- .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand access.", ++ .desc = "This event counts the number of L3 cache misses caused by demand access where the requests hit the PFTGT buffer.", + }, + { +- .name = "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_RD", ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM_RD_PFTGT_HIT", + .modmsk = ARMV9_ATTRS, + .code = 0x03a4, +- .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand read access.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT caused by read access.", + }, + { +- .name = "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_WR", ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM_WR_PFTGT_HIT", + .modmsk = ARMV9_ATTRS, + .code = 0x03a5, +- .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand write access.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM_PFTGT_HIT caused by write access.", + }, + { +- .name = "L2D_CACHE_REFILL_L3D_MISS_L_MEM", ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM_L_MEM", + .modmsk = ARMV9_ATTRS, + .code = 0x03a6, +- .desc = "This event counts the number of L3 cache misses where the requests access the memory in the same socket as the requests.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access the memory in the same socket as the requests.", + }, + { +- .name = "L2D_CACHE_REFILL_L3D_MISS_FR_MEM", ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM_FR_MEM", + .modmsk = ARMV9_ATTRS, + .code = 0x03a7, +- .desc = "This event counts the number of L3 cache misses where the requests access the memory in the different socket from the requests.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access the memory in the different socket from the requests.", + }, + { +- .name = "L2D_CACHE_REFILL_L3D_MISS_L_L2", ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM_L_L2", + .modmsk = ARMV9_ATTRS, + .code = 0x03a8, +- .desc = "This event counts the number of L3 cache misses where the requests access the different L2 cache from the requests in the same Numa nodes as the requests.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access the different L2 cache from the requests in the same Numa nodes as the requests.", + }, + { +- .name = "L2D_CACHE_REFILL_L3D_MISS_NR_L2", ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM_NR_L2", + .modmsk = ARMV9_ATTRS, + .code = 0x03a9, +- .desc = "This event counts the number of L3 cache misses where the requests access L2 cache in the different Numa nodes from the requests in the same socket as the requests.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L2 cache in the different Numa nodes from the requests in the same socket as the requests.", + }, + { +- .name = "L2D_CACHE_REFILL_L3D_MISS_NR_L3", ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM_NR_L3", + .modmsk = ARMV9_ATTRS, + .code = 0x03aa, +- .desc = "This event counts the number of L3 cache misses where the requests access L3 cache in the different Numa nodes from the requests in the same socket as the requests.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L3 cache in the different Numa nodes from the requests in the same socket as the requests.", + }, + { +- .name = "L2D_CACHE_REFILL_L3D_MISS_FR_L2", ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM_FR_L2", + .modmsk = ARMV9_ATTRS, + .code = 0x03ab, +- .desc = "This event counts the number of L3 cache misses where the requests access L2 cache in the different socket from the requests.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L2 cache in the different socket from the requests.", + }, + { +- .name = "L2D_CACHE_REFILL_L3D_MISS_FR_L3", ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM_FR_L3", + .modmsk = ARMV9_ATTRS, + .code = 0x03ac, +- .desc = "This event counts the number of L3 cache misses where the requests access L3 cache in the different socket from the requests.", ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_DM where the requests access L3 cache in the different socket from the requests.", + }, + { + .name = "L2D_CACHE_WB_VICTIM_CLEAN", +@@ -1515,85 +1509,85 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L1I_TLB_REFILL_4K", + .modmsk = ARMV9_ATTRS, + .code = 0x0c10, +- .desc = "This event counts operations that cause a TLB refill to the L1I in 4KB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1I in 4KB page.", + }, + { + .name = "L1I_TLB_REFILL_64K", + .modmsk = ARMV9_ATTRS, + .code = 0x0c11, +- .desc = "This event counts operations that cause a TLB refill to the L1I in 64KB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1I in 64KB page.", + }, + { + .name = "L1I_TLB_REFILL_2M", + .modmsk = ARMV9_ATTRS, + .code = 0x0c12, +- .desc = "This event counts operations that cause a TLB refill to the L1I in 2MB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1I in 2MB page.", + }, + { + .name = "L1I_TLB_REFILL_32M", + .modmsk = ARMV9_ATTRS, + .code = 0x0c13, +- .desc = "This event counts operations that cause a TLB refill to the L1I in 32MB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1I in 32MB page.", + }, + { + .name = "L1I_TLB_REFILL_512M", + .modmsk = ARMV9_ATTRS, + .code = 0x0c14, +- .desc = "This event counts operations that cause a TLB refill to the L1I in 512MB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1I in 512MB page.", + }, + { + .name = "L1I_TLB_REFILL_1G", + .modmsk = ARMV9_ATTRS, + .code = 0x0c15, +- .desc = "This event counts operations that cause a TLB refill to the L1I in 1GB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1I in 1GB page.", + }, + { + .name = "L1I_TLB_REFILL_16G", + .modmsk = ARMV9_ATTRS, + .code = 0x0c16, +- .desc = "This event counts operations that cause a TLB refill to the L1I in 16GB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1I in 16GB page.", + }, + { + .name = "L1D_TLB_REFILL_4K", + .modmsk = ARMV9_ATTRS, + .code = 0x0c18, +- .desc = "This event counts operations that cause a TLB refill to the L1D in 4KB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1D in 4KB page.", + }, + { + .name = "L1D_TLB_REFILL_64K", + .modmsk = ARMV9_ATTRS, + .code = 0x0c19, +- .desc = "This event counts operations that cause a TLB refill to the L1D in 64KB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1D in 64KB page.", + }, + { + .name = "L1D_TLB_REFILL_2M", + .modmsk = ARMV9_ATTRS, + .code = 0x0c1a, +- .desc = "This event counts operations that cause a TLB refill to the L1D in 2MB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1D in 2MB page.", + }, + { + .name = "L1D_TLB_REFILL_32M", + .modmsk = ARMV9_ATTRS, + .code = 0x0c1b, +- .desc = "This event counts operations that cause a TLB refill to the L1D in 32MB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1D in 32MB page.", + }, + { + .name = "L1D_TLB_REFILL_512M", + .modmsk = ARMV9_ATTRS, + .code = 0x0c1c, +- .desc = "This event counts operations that cause a TLB refill to the L1D in 512MB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1D in 512MB page.", + }, + { + .name = "L1D_TLB_REFILL_1G", + .modmsk = ARMV9_ATTRS, + .code = 0x0c1d, +- .desc = "This event counts operations that cause a TLB refill to the L1D in 1GB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1D in 1GB page.", + }, + { + .name = "L1D_TLB_REFILL_16G", + .modmsk = ARMV9_ATTRS, + .code = 0x0c1e, +- .desc = "This event counts operations that cause a TLB refill to the L1D in 16GB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L1D in 16GB page.", + }, + { + .name = "L2I_TLB_4K", +@@ -1683,85 +1677,85 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L2I_TLB_REFILL_4K", + .modmsk = ARMV9_ATTRS, + .code = 0x0c30, +- .desc = "This event counts operations that cause a TLB refill to the L2Iin 4KB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2I in 4KB page.", + }, + { + .name = "L2I_TLB_REFILL_64K", + .modmsk = ARMV9_ATTRS, + .code = 0x0c31, +- .desc = "This event counts operations that cause a TLB refill to the L2I in 64KB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2I in 64KB page.", + }, + { + .name = "L2I_TLB_REFILL_2M", + .modmsk = ARMV9_ATTRS, + .code = 0x0c32, +- .desc = "This event counts operations that cause a TLB refill to the L2I in 2MB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2I in 2MB page.", + }, + { + .name = "L2I_TLB_REFILL_32M", + .modmsk = ARMV9_ATTRS, + .code = 0x0c33, +- .desc = "This event counts operations that cause a TLB refill to the L2I in 32MB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2I in 32MB page.", + }, + { + .name = "L2I_TLB_REFILL_512M", + .modmsk = ARMV9_ATTRS, + .code = 0x0c34, +- .desc = "This event counts operations that cause a TLB refill to the L2I in 512MB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2I in 512MB page.", + }, + { + .name = "L2I_TLB_REFILL_1G", + .modmsk = ARMV9_ATTRS, + .code = 0x0c35, +- .desc = "This event counts operations that cause a TLB refill to the L2I in 1GB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2I in 1GB page.", + }, + { + .name = "L2I_TLB_REFILL_16G", + .modmsk = ARMV9_ATTRS, + .code = 0x0c36, +- .desc = "This event counts operations that cause a TLB refill to the L2I in 16GB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2I in 16GB page.", + }, + { + .name = "L2D_TLB_REFILL_4K", + .modmsk = ARMV9_ATTRS, + .code = 0x0c38, +- .desc = "This event counts operations that cause a TLB refill to the L2D in 4KB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2D in 4KB page.", + }, + { + .name = "L2D_TLB_REFILL_64K", + .modmsk = ARMV9_ATTRS, + .code = 0x0c39, +- .desc = "This event counts operations that cause a TLB refill to the L2D in 64KB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2D in 64KB page.", + }, + { + .name = "L2D_TLB_REFILL_2M", + .modmsk = ARMV9_ATTRS, + .code = 0x0c3a, +- .desc = "This event counts operations that cause a TLB refill to the L2D in 2MB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2D in 2MB page.", + }, + { + .name = "L2D_TLB_REFILL_32M", + .modmsk = ARMV9_ATTRS, + .code = 0x0c3b, +- .desc = "This event counts operations that cause a TLB refill to the L2D in 32MB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2D in 32MB page.", + }, + { + .name = "L2D_TLB_REFILL_512M", + .modmsk = ARMV9_ATTRS, + .code = 0x0c3c, +- .desc = "This event counts operations that cause a TLB refill to the L2D in 512MB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2D in 512MB page.", + }, + { + .name = "L2D_TLB_REFILL_1G", + .modmsk = ARMV9_ATTRS, + .code = 0x0c3d, +- .desc = "This event counts operations that cause a TLB refill to the L2D in 1GB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2D in 1GB page.", + }, + { + .name = "L2D_TLB_REFILL_16G", + .modmsk = ARMV9_ATTRS, + .code = 0x0c3e, +- .desc = "This event counts operations that cause a TLB refill to the L2D in 16GB page.", ++ .desc = "This event counts operations that cause a TLB refill of the L2D in 16GB page.", + }, + { + .name = "CNT_CYCLES", +@@ -1785,13 +1779,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L2D_CACHE_LMISS_RD", + .modmsk = ARMV9_ATTRS, + .code = 0x4009, +- .desc = "This event counts operations that cause a refill of the L2D cache that incurs additional latency.", ++ .desc = "This event counts operations that cause a refill of the L2 cache that incurs additional latency.", + }, + { + .name = "L3D_CACHE_LMISS_RD", + .modmsk = ARMV9_ATTRS, + .code = 0x400b, +- .desc = "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events.", ++ .desc = "This event counts access counted by L3D_CACHE that is not completed by the L3 cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events. Note: This event may count inaccurately.", + }, + { + .name = "TRB_WRAP", +@@ -1845,7 +1839,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_INST_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8005, +- .desc = "This event counts architecturally executed Advanced SIMD operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD operation.", + }, + { + .name = "SVE_INST_SPEC", +@@ -1857,13 +1851,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_INST_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8007, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE operation.", + }, + { + .name = "UOP_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8008, +- .desc = "This event counts all architecturally executed micro-operations.", ++ .desc = "This event counts all architecturally executed micro-operation.", + }, + { + .name = "SVE_MATH_SPEC", +@@ -1893,7 +1887,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_FP_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8013, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point operation.", + }, + { + .name = "FP_HP_SPEC", +@@ -1917,7 +1911,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_FP_HP_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8017, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE half-precision floating-point operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE half-precision floating-point operation.", + }, + { + .name = "FP_SP_SPEC", +@@ -1941,7 +1935,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_FP_SP_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x801b, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE single-precision floating-point operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE single-precision floating-point operation.", + }, + { + .name = "FP_DP_SPEC", +@@ -1965,7 +1959,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_FP_DP_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x801f, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE double-precision floating-point operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE double-precision floating-point operation.", + }, + { + .name = "FP_DIV_SPEC", +@@ -1989,7 +1983,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_FP_DIV_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8023, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point divide operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point divide operation.", + }, + { + .name = "FP_SQRT_SPEC", +@@ -2013,13 +2007,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_FP_SQRT_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8027, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point square root operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point square root operation.", + }, + { + .name = "FP_FMA_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8028, +- .desc = "This event counts architecturally executed floating-point fused multiply-add and multiply-subtract operations.", ++ .desc = "This event counts architecturally executed floating-point fused multiply-add and multiply-subtract operation.", + }, + { + .name = "ASE_FP_FMA_SPEC", +@@ -2037,13 +2031,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_FP_FMA_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x802b, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point FMA operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point FMA operation.", + }, + { + .name = "FP_MUL_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x802c, +- .desc = "This event counts architecturally executed floating-point multiply operations.", ++ .desc = "This event counts architecturally executed floating-point multiply operation.", + }, + { + .name = "ASE_FP_MUL_SPEC", +@@ -2061,13 +2055,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_FP_MUL_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x802f, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point multiply operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point multiply operation.", + }, + { + .name = "FP_ADDSUB_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8030, +- .desc = "This event counts architecturally executed floating-point add or subtract operations.", ++ .desc = "This event counts architecturally executed floating-point add or subtract operation.", + }, + { + .name = "ASE_FP_ADDSUB_SPEC", +@@ -2085,7 +2079,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_FP_ADDSUB_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8033, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point add or subtract operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point add or subtract operation.", + }, + { + .name = "FP_RECPE_SPEC", +@@ -2097,19 +2091,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_FP_RECPE_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8035, +- .desc = "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operation.", + }, + { + .name = "SVE_FP_RECPE_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8036, +- .desc = "This event counts architecturally executed SVE floating-point reciprocal estimate operations.", ++ .desc = "This event counts architecturally executed SVE floating-point reciprocal estimate operation.", + }, + { + .name = "ASE_SVE_FP_RECPE_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8037, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point reciprocal estimate operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point reciprocal estimate operation.", + }, + { + .name = "FP_CVT_SPEC", +@@ -2133,19 +2127,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_FP_CVT_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x803b, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point convert operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point convert operation.", + }, + { + .name = "SVE_FP_AREDUCE_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x803c, +- .desc = "This event counts architecturally executed SVE floating-point accumulating reduction operations.", ++ .desc = "This event counts architecturally executed SVE floating-point accumulating reduction operation.", + }, + { + .name = "ASE_FP_PREDUCE_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x803d, +- .desc = "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operation.", + }, + { + .name = "SVE_FP_VREDUCE_SPEC", +@@ -2157,7 +2151,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_FP_VREDUCE_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x803f, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point vector reduction operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE floating-point vector reduction operation.", + }, + { + .name = "INT_SPEC", +@@ -2169,19 +2163,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_INT_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8041, +- .desc = "This event counts architecturally executed Advanced SIMD integer operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD integer operation.", + }, + { + .name = "SVE_INT_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8042, +- .desc = "This event counts architecturally executed SVE integer operations.", ++ .desc = "This event counts architecturally executed SVE integer operation.", + }, + { + .name = "ASE_SVE_INT_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8043, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE integer operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE integer operation.", + }, + { + .name = "INT_DIV_SPEC", +@@ -2229,7 +2223,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_INT_MUL_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x804b, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE integer multiply operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE integer multiply operation.", + }, + { + .name = "INT_MUL64_SPEC", +@@ -2253,31 +2247,31 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "SVE_INT_MULH64_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x804f, +- .desc = "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply returning high part operations.", ++ .desc = "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply returning high part operation.", + }, + { + .name = "NONFP_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8058, +- .desc = "This event counts architecturally executed non-floating-point operations.", ++ .desc = "This event counts architecturally executed non-floating-point operation.", + }, + { + .name = "ASE_NONFP_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8059, +- .desc = "This event counts architecturally executed Advanced SIMD non-floating-point operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD non-floating-point operation.", + }, + { + .name = "SVE_NONFP_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x805a, +- .desc = "This event counts architecturally executed SVE non-floating-point operations.", ++ .desc = "This event counts architecturally executed SVE non-floating-point operation.", + }, + { + .name = "ASE_SVE_NONFP_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x805b, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE non-floating-point operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE non-floating-point operation.", + }, + { + .name = "ASE_INT_VREDUCE_SPEC", +@@ -2295,7 +2289,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_INT_VREDUCE_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x805f, +- .desc = "This event counts architecturally executed Advanced SIMD and SVE integer reduction operations.", ++ .desc = "This event counts architecturally executed Advanced SIMD or SVE integer reduction operation.", + }, + { + .name = "SVE_PERM_SPEC", +@@ -2367,13 +2361,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_LD_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8085, +- .desc = "This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD load instructions.", ++ .desc = "This event counts architecturally executed operations that read from memory due to Advanced SIMD or SVE load instructions.", + }, + { + .name = "ASE_SVE_ST_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x8086, +- .desc = "This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD store instructions.", ++ .desc = "This event counts architecturally executed operations that write to memory due to Advanced SIMD or SVE store instructions.", + }, + { + .name = "PRF_SPEC", +@@ -2439,13 +2433,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "ASE_SVE_LD_MULTI_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x80a5, +- .desc = "This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD multiple vector contiguous structure load instructions.", ++ .desc = "This event counts architecturally executed operations that read from memory due to Advanced SIMD or SVE multiple vector contiguous structure load instructions.", + }, + { + .name = "ASE_SVE_ST_MULTI_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x80a6, +- .desc = "This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD multiple vector contiguous structure store instructions.", ++ .desc = "This event counts architecturally executed operations that write to memory due to Advanced SIMD or SVE multiple vector contiguous structure store instructions.", + }, + { + .name = "SVE_LD_GATHER_SPEC", +@@ -2475,49 +2469,49 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "FP_SCALE_OPS_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x80c0, +- .desc = "This event counts architecturally executed SVE arithmetic operations. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC.", ++ .desc = "This event counts architecturally executed SVE arithmetic operation. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC.", + }, + { + .name = "FP_FIXED_OPS_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x80c1, +- .desc = "This event counts architecturally executed v8SIMD&FP arithmetic operations. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. The event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", ++ .desc = "This event counts architecturally executed v8SIMD&FP arithmetic operation. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", + }, + { + .name = "FP_HP_SCALE_OPS_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x80c2, +- .desc = "This event counts architecturally executed SVE half-precision arithmetic operations. See FP_HP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 8, or by 16 for operations that would also be counted by SVE_FP_FMA_SPEC.", ++ .desc = "This event counts architecturally executed SVE half-precision arithmetic operation. See FP_HP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 8, or by 16 for operations that would also be counted by SVE_FP_FMA_SPEC.", + }, + { + .name = "FP_HP_FIXED_OPS_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x80c3, +- .desc = "This event counts architecturally executed v8SIMD&FP half-precision arithmetic operations. See FP_HP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 16-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", ++ .desc = "This event counts architecturally executed v8SIMD&FP half-precision arithmetic operation. See FP_HP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 16-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", + }, + { + .name = "FP_SP_SCALE_OPS_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x80c4, +- .desc = "This event counts architecturally executed SVE single-precision arithmetic operations. See FP_SP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 4, or by 8 for operations that would also be counted by SVE_FP_FMA_SPEC.", ++ .desc = "This event counts architecturally executed SVE single-precision arithmetic operation. See FP_SP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 4, or by 8 for operations that would also be counted by SVE_FP_FMA_SPEC.", + }, + { + .name = "FP_SP_FIXED_OPS_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x80c5, +- .desc = "This event counts architecturally executed v8SIMD&FP single-precision arithmetic operations. See FP_SP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 32-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", ++ .desc = "This event counts architecturally executed v8SIMD&FP single-precision arithmetic operation. See FP_SP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 32-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", + }, + { + .name = "FP_DP_SCALE_OPS_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x80c6, +- .desc = "This event counts architecturally executed SVE double-precision arithmetic operations. See FP_DP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2, or by 4 for operations that would also be counted by SVE_FP_FMA_SPEC.", ++ .desc = "This event counts architecturally executed SVE double-precision arithmetic operation. See FP_DP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2, or by 4 for operations that would also be counted by SVE_FP_FMA_SPEC.", + }, + { + .name = "FP_DP_FIXED_OPS_SPEC", + .modmsk = ARMV9_ATTRS, + .code = 0x80c7, +- .desc = "This event counts architecturally executed v8SIMD&FP double-precision arithmetic operations. See FP_DP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2 for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", ++ .desc = "This event counts architecturally executed v8SIMD&FP double-precision arithmetic operation. See FP_DP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2 for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", + }, + { + .name = "INT_SCALE_OPS_SPEC", +@@ -2613,7 +2607,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L1I_CACHE_HWPRF", + .modmsk = ARMV9_ATTRS, + .code = 0x8145, +- .desc = "This event counts access counted by L1I_CACHE that is due to a hardware prefetch.", ++ .desc = "This event counts L1I_CACHE caused by hardware prefetch.", + }, + { + .name = "L2D_CACHE_MISS", +@@ -2625,13 +2619,13 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L1D_CACHE_HWPRF", + .modmsk = ARMV9_ATTRS, + .code = 0x8154, +- .desc = "This event counts access counted by L1D_CACHE that is due to a hardware prefetch.", ++ .desc = "This event counts L1D_CACHE caused by hardware prefetch.", + }, + { + .name = "L2D_CACHE_HWPRF", + .modmsk = ARMV9_ATTRS, + .code = 0x8155, +- .desc = "This event counts access counted by L2D_CACHE that is due to a hardware prefetch.", ++ .desc = "This event counts L2D_CACHE caused by hardware prefetch.", + }, + { + .name = "STALL_FRONTEND_MEMBOUND", +@@ -2703,7 +2697,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "STALL_BACKEND_L2D", + .modmsk = ARMV9_ATTRS, + .code = 0x8166, +- .desc = "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L2D cache.", ++ .desc = "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L2 cache.", + }, + { + .name = "STALL_BACKEND_TLB", +@@ -2787,19 +2781,19 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L1I_CACHE_REFILL_HWPRF", + .modmsk = ARMV9_ATTRS, + .code = 0x81b8, +- .desc = "This event counts hardware prefetch counted by L1I_CACHE_HWPRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache.", ++ .desc = "This event counts L1I_CACHE_REFILL caused by hardware prefetch.", + }, + { + .name = "L1D_CACHE_REFILL_HWPRF", + .modmsk = ARMV9_ATTRS, + .code = 0x81bc, +- .desc = "This event counts hardware prefetch counted by L1D_CACHE_HWPRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache.", ++ .desc = "This event counts L1D_CACHE_REFILL caused by hardware prefetch.", + }, + { + .name = "L2D_CACHE_REFILL_HWPRF", + .modmsk = ARMV9_ATTRS, + .code = 0x81bd, +- .desc = "This event counts hardware prefetch counted by L2D_CACHE_HWPRF that causes a refill of the Level 2 cache, or any Level 1 data and instruction cache of this PE, from outside of those caches.", ++ .desc = "This event counts L2D_CACHE_REFILL caused by hardware prefetch.", + }, + { + .name = "L1I_CACHE_HIT_RD", +@@ -2817,7 +2811,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L2D_CACHE_HIT_RD", + .modmsk = ARMV9_ATTRS, + .code = 0x81c5, +- .desc = "This event counts demand read counted by L2D_CACHE_RD that hits in the Level 2 data cache.", ++ .desc = "This event counts demand read counted by L2D_CACHE_RD that hits in the Level 2 cache.", + }, + { + .name = "L1D_CACHE_HIT_WR", +@@ -2829,7 +2823,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L2D_CACHE_HIT_WR", + .modmsk = ARMV9_ATTRS, + .code = 0x81c9, +- .desc = "This event counts demand write counted by L2D_CACHE_WR that hits in the Level 2 data cache.", ++ .desc = "This event counts demand write counted by L2D_CACHE_WR that hits in the Level 2 cache.", + }, + { + .name = "L1I_CACHE_HIT", +@@ -2847,7 +2841,7 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L2D_CACHE_HIT", + .modmsk = ARMV9_ATTRS, + .code = 0x8205, +- .desc = "This event counts access counted by L2D_CACHE that hits in the Level 2 data cache.", ++ .desc = "This event counts access counted by L2D_CACHE that hits in the Level 2 cache.", + }, + { + .name = "L1I_LFB_HIT_RD", +@@ -2883,54 +2877,138 @@ static const arm_entry_t arm_monaka_pe[ ] = { + .name = "L1I_CACHE_PRF", + .modmsk = ARMV9_ATTRS, + .code = 0x8280, +- .desc = "This event counts fetch counted by either Level 1 instruction hardware prefetch or Level 1 instruction software prefetch.", ++ .desc = "This event counts L1I_CACHE caused by hardware prefetch or software prefetch.", + }, + { + .name = "L1D_CACHE_PRF", + .modmsk = ARMV9_ATTRS, + .code = 0x8284, +- .desc = "This event counts fetch counted by either Level 1 data hardware prefetch or Level 1 data software prefetch.", ++ .desc = "This event counts L1D_CACHE caused by hardware prefetch or software prefetch.", + }, + { + .name = "L2D_CACHE_PRF", + .modmsk = ARMV9_ATTRS, + .code = 0x8285, +- .desc = "This event counts fetch counted by either Level 2 data hardware prefetch or Level 2 data software prefetch.", ++ .desc = "This event counts L2D_CACHE caused by hardware prefetch or software prefetch.", + }, + { + .name = "L1I_CACHE_REFILL_PRF", + .modmsk = ARMV9_ATTRS, + .code = 0x8288, +- .desc = "This event counts hardware prefetch counted by L1I_CACHE_PRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache.", ++ .desc = "This event counts L1I_CACHE_REFILL caused by hardware prefetch or software prefetch.", + }, + { + .name = "L1D_CACHE_REFILL_PRF", + .modmsk = ARMV9_ATTRS, + .code = 0x828c, +- .desc = "This event counts hardware prefetch counted by L1D_CACHE_PRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache.", ++ .desc = "This event counts L1D_CACHE_REFILL caused by hardware prefetch or software prefetch.", + }, + { + .name = "L2D_CACHE_REFILL_PRF", + .modmsk = ARMV9_ATTRS, + .code = 0x828d, +- .desc = "This event counts hardware prefetch counted by L2D_CACHE_PRF that causes a refill of the Level 2 data cache from outside of the Level 1 data cache.", ++ .desc = "This event counts L2D_CACHE_REFILL caused by hardware prefetch or software prefetch.", + }, + { + .name = "L1D_CACHE_REFILL_PERCYC", + .modmsk = ARMV9_ATTRS, + .code = 0x8320, +- .desc = "The counter counts by the number of cache refills counted by L1D_CACHE_REFILL in progress on each Processor cycle.", ++ .desc = "This counter counts by the number of cache refills counted by L1D_CACHE_REFILL in progress on each Processor cycle.", + }, + { + .name = "L2D_CACHE_REFILL_PERCYC", + .modmsk = ARMV9_ATTRS, + .code = 0x8321, +- .desc = "The counter counts by the number of cache refills counted by L2D_CACHE_REFILL in progress on each Processor cycle.", ++ .desc = "This counter counts by the number of cache refills counted by L2D_CACHE_REFILL in progress on each Processor cycle.", + }, + { + .name = "L1I_CACHE_REFILL_PERCYC", + .modmsk = ARMV9_ATTRS, + .code = 0x8324, +- .desc = "The counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle.", ++ .desc = "This counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle.", ++ }, ++ { ++ .name = "ASE_FP_VREDUCE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8431, ++ .desc = "This event counts architecturally executed Advanced SIMD floating-point vector reduction operation.", ++ }, ++ { ++ .name = "SVE_FP_PREDUCE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8432, ++ .desc = "This event counts architecturally executed SVE floating-point pairwise add step operation.", ++ }, ++ { ++ .name = "ASE_FP_BF16_MIN_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8443, ++ .desc = "This event counts architecturally executed Advanced SIMD data processing operations, smallest type is BFloat16 floating-point.", ++ }, ++ { ++ .name = "ASE_FP_FP8_MIN_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8444, ++ .desc = "This event counts architecturally executed Advanced SIMD data processing operations, smallest type is 8-bit floating-point.", ++ }, ++ { ++ .name = "ASE_SVE_FP_BF16_MIN_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x844b, ++ .desc = "This event counts architecturally executed Advanced SIMD data processing or SVE data processing operations, smallest type is BFloat16 floating-point.", ++ }, ++ { ++ .name = "ASE_SVE_FP_FP8_MIN_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x844c, ++ .desc = "This event counts architecturally executed Advanced SIMD data processing or SVE data processing operations, smallest type is 8-bit floating-point.", ++ }, ++ { ++ .name = "SVE_FP_BF16_MIN_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8463, ++ .desc = "This event counts architecturally executed SVE data processing operations, smallest type is BFloat16 floating-point.", ++ }, ++ { ++ .name = "SVE_FP_FP8_MIN_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8464, ++ .desc = "This event counts architecturally executed SVE data processing operations, smallest type is 8-bit floating-point.", ++ }, ++ { ++ .name = "FP_BF16_MIN_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8473, ++ .desc = "This event counts architecturally executed data processing operations, smallest type is BFloat16 floating-point.", ++ }, ++ { ++ .name = "FP_FP8_MIN_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8474, ++ .desc = "This event counts architecturally executed data processing operations, smallest type is 8-bit floating-point.", ++ }, ++ { ++ .name = "FP_BF16_FIXED_MIN_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8483, ++ .desc = "This event counts architecturally executed non-scalable element arithmetic operations, smallest type is BFloat16 floating-point.", ++ }, ++ { ++ .name = "FP_FP8_FIXED_MIN_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8484, ++ .desc = "This event counts architecturally executed non-scalable element arithmetic operations, smallest type is 8-bit floating-point.", ++ }, ++ { ++ .name = "FP_BF16_SCALE_MIN_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x848b, ++ .desc = "This event counts architecturally executed scalable element arithmetic operations, smallest type is BFloat16 floating-point.", ++ }, ++ { ++ .name = "FP_FP8_SCALE_MIN_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x848c, ++ .desc = "This event counts architecturally executed scalable element arithmetic operations, smallest type is 8-bit floating-point.", + }, + }; +-- +2.54.0 + diff --git a/libpfm-monaka.patch b/libpfm-monaka.patch new file mode 100644 index 0000000..4677e38 --- /dev/null +++ b/libpfm-monaka.patch @@ -0,0 +1,3189 @@ +From 5e26b48b6d9b9d5f8c368c81cfe23a54a129bd24 Mon Sep 17 00:00:00 2001 +From: Yoshihiro Furudera +Date: Thu, 3 Oct 2024 16:25:55 +0900 +Subject: [PATCH] Enable support for FUJITSU-MONAKA core PMU + +This patch adds support for FUJITSU-MONAKA core PMU. This +includes ARMv9 generic core events and FUJITSU-MONAKA +specfic events. + +FUJITSU-MONAKA Specification URL: +https://github.com/fujitsu/FUJITSU-MONAKA + +Signed-off-by: Yoshihiro Furudera +--- + README | 1 + + docs/Makefile | 1 + + docs/man3/libpfm_arm_monaka.3 | 36 + + include/perfmon/pfmlib.h | 2 + + lib/Makefile | 1 + + lib/events/arm_fujitsu_monaka_events.h | 2936 ++++++++++++++++++++++++ + lib/pfmlib_arm_armv9.c | 43 + + lib/pfmlib_common.c | 1 + + lib/pfmlib_priv.h | 1 + + tests/validate_arm64.c | 28 + + 10 files changed, 3050 insertions(+) + create mode 100644 docs/man3/libpfm_arm_monaka.3 + create mode 100644 lib/events/arm_fujitsu_monaka_events.h + +diff --git a/README b/README +--- a/README ++++ b/README +@@ -76,6 +76,7 @@ The library supports many PMUs. The current version can handle: + Applied Micro X-Gene + Qualcomm Krait + Fujitsu A64FX ++ Fujitsu FUJITSU-MONAKA + Arm Neoverse V1 + Arm Neoverse V2 + Huawei HiSilicon Kunpeng 920 +diff --git a/docs/Makefile b/docs/Makefile +--- a/docs/Makefile ++++ b/docs/Makefile +@@ -141,6 +141,7 @@ ARCH_MAN += libpfm_arm_xgene.3 \ + libpfm_arm_ac57.3 \ + libpfm_arm_ac53.3 \ + libpfm_arm_a64fx.3 \ ++ libpfm_arm_monaka.3 \ + libpfm_arm_neoverse_n1.3 \ + libpfm_arm_neoverse_n2.3 \ + libpfm_arm_neoverse_v1.3 \ +diff --git a/docs/man3/libpfm_arm_monaka.3 b/docs/man3/libpfm_arm_monaka.3 +new file mode 100644 +index 0000000..c4c2388 +--- /dev/null ++++ b/docs/man3/libpfm_arm_monaka.3 +@@ -0,0 +1,36 @@ ++.TH LIBPFM 3 "October, 2024" "" "Linux Programmer's Manual" ++.SH NAME ++libpfm_arm_monaka - support for Fujitsu FUJITSU-MONAKA PMU ++.SH SYNOPSIS ++.nf ++.B #include ++.sp ++.B PMU name: arm_monaka ++.B PMU desc: Fujitsu FUJITSU-MONAKA ++.sp ++.SH DESCRIPTION ++The library supports the Fujitsu FUJITSU-MONAKA core PMU. ++ ++This PMU supports 8 counters and privilege levels filtering. ++It can operate in 64 bit mode only. ++ ++.SH MODIFIERS ++The following modifiers are supported on Fujitsu FUJITSU-MONAKA: ++.TP ++.B u ++Measure at the user level. This corresponds to \fBPFM_PLM3\fR. ++This is a boolean modifier. ++.TP ++.B k ++Measure at the kernel level. This corresponds to \fBPFM_PLM0\fR. ++This is a boolean modifier. ++.TP ++.B hv ++Measure at the hypervisor level. This corresponds to \fBPFM_PLMH\fR. ++This is a boolean modifier. ++ ++.SH AUTHORS ++.nf ++Stephane Eranian ++.if ++.PP +diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h +--- a/include/perfmon/pfmlib.h ++++ b/include/perfmon/pfmlib.h +@@ -638,6 +638,8 @@ typedef enum { + PFM_PMU_AMD64_FAM19H_ZEN4, /* AMD AMD64 Fam19h Zen4 */ + PFM_PMU_ARM_V1, /* ARM Neoverse V1 */ + PFM_PMU_ARM_V2, /* Arm Neoverse V2 */ ++ ++ PFM_PMU_ARM_MONAKA, /* Fujitsu FUJITSU-MONAKA processor */ + + /* MUST ADD NEW PMU MODELS HERE */ + +diff --git a/lib/Makefile b/lib/Makefile +index d39f789..c92fd72 100644 +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -438,6 +438,7 @@ INC_ARM64=pfmlib_arm_priv.h \ + events/arm_cavium_tx2_events.h \ + events/arm_marvell_tx2_unc_events.h \ + events/arm_fujitsu_a64fx_events.h \ ++ events/arm_fujitsu_monaka_events.h \ + events/arm_neoverse_n1_events.h \ + events/arm_neoverse_n2_events.h \ + events/arm_neoverse_v1_events.h \ +diff --git a/lib/events/arm_fujitsu_monaka_events.h b/lib/events/arm_fujitsu_monaka_events.h +new file mode 100644 +index 0000000..00c3e4f +--- /dev/null ++++ b/lib/events/arm_fujitsu_monaka_events.h +@@ -0,0 +1,2936 @@ ++/* ++ * Copyright (c) 2024 Fujitsu Limited. All rights reserved. ++ */ ++ ++/* ++ * Fujitsu FUJITSU-MONAKA processor ++ * ++ * FUJITSU-MONAKA Specification ++ * Fujitsu Limited ++ * 1.0, 30 September 2024 ++ */ ++ ++static const arm_entry_t arm_monaka_pe[ ] = { ++ { ++ .name = "SW_INCR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0000, ++ .desc = "This event counts on writes to the PMSWINC register.", ++ }, ++ { ++ .name = "L1I_CACHE_REFILL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0001, ++ .desc = "This event counts operations that cause a refill of the L1I cache. See L1I_CACHE_REFILL of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L1I_TLB_REFILL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0002, ++ .desc = "This event counts operations that cause a TLB refill of the L1I TLB. See L1I_TLB_REFILL of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L1D_CACHE_REFILL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0003, ++ .desc = "This event counts operations that cause a refill of the L1D cache. See L1D_CACHE_REFILL of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L1D_CACHE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0004, ++ .desc = "This event counts operations that cause a cache access to the L1D cache. See L1D_CACHE of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L1D_TLB_REFILL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0005, ++ .desc = "This event counts operations that cause a TLB refill of the L1D TLB. See L1D_TLB_REFILL of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "INST_RETIRED", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0008, ++ .desc = "This event counts every architecturally executed instruction.", ++ }, ++ { ++ .name = "EXC_TAKEN", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0009, ++ .desc = "This event counts each exception taken.", ++ }, ++ { ++ .name = "EXC_RETURN", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x000a, ++ .desc = "This event counts each executed exception return instruction.", ++ }, ++ { ++ .name = "CID_WRITE_RETIRED", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x000b, ++ .desc = "This event counts every write to CONTEXTIDR.", ++ }, ++ { ++ .name = "BR_MIS_PRED", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0010, ++ .desc = "This event counts each correction to the predicted program flow that occurs because of a misprediction from, or no prediction from, the branch prediction resources and that relates to instructions that the branch prediction resources are capable of predicting.", ++ }, ++ { ++ .name = "CPU_CYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0011, ++ .desc = "This event counts every cycle.", ++ }, ++ { ++ .name = "BR_PRED", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0012, ++ .desc = "This event counts every branch or other change in the program flow that the branch prediction resources are capable of predicting.", ++ }, ++ { ++ .name = "MEM_ACCESS", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0013, ++ .desc = "This event counts architecturally executed memory-reading instructions and memory-writing instructions, as defined by the LDST_SPEC events.", ++ }, ++ { ++ .name = "L1I_CACHE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0014, ++ .desc = "This event counts operations that cause a cache access to the L1I cache. See L1I_CACHE of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L1D_CACHE_WB", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0015, ++ .desc = "This event counts every write-back of data from the L1D cache. See L1D_CACHE_WB of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L2D_CACHE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0016, ++ .desc = "This event counts operations that cause a cache access to the L2 cache. See L2D_CACHE of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0017, ++ .desc = "This event counts operations that cause a refill of the L2 cache. See L2D_CACHE_REFILL of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L2D_CACHE_WB", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0018, ++ .desc = "This event counts every write-back of data from the L2 cache caused by L2 replace, non-temporal-store and DC ZVA.", ++ }, ++ { ++ .name = "INST_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x001b, ++ .desc = "This event counts every architecturally executed instruction.", ++ }, ++ { ++ .name = "BR_RETIRED", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0021, ++ .desc = "This event counts architecturally executed branch instruction.", ++ }, ++ { ++ .name = "BR_MIS_PRED_RETIRED", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0022, ++ .desc = "This event counts architecturally executed branch instruction which was mispredicted.", ++ }, ++ { ++ .name = "STALL_FRONTEND", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0023, ++ .desc = "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because there are no operations available to issue for this PE from the frontend.", ++ }, ++ { ++ .name = "STALL_BACKEND", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0024, ++ .desc = "This event counts every cycle counted by the CPU_CYCLES event on that no operation was issued because the backend is unable to accept any operations.", ++ }, ++ { ++ .name = "L1D_TLB", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0025, ++ .desc = "This event counts operations that cause a TLB access to the L1D TLB. See L1D_TLB of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L1I_TLB", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0026, ++ .desc = "This event counts operations that cause a TLB access to the L1I TLB. See L1I_TLB of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L3D_CACHE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x002b, ++ .desc = "This event counts operations that cause a cache access to the L3 cache, as defined by the sum of L2D_CACHE_REFILL_L3D_CACHE and L2D_CACHE_WB_VICTIM_CLEAN events.", ++ }, ++ { ++ .name = "L2D_TLB_REFILL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x002d, ++ .desc = "This event counts operations that cause a TLB refill of the L2D TLB. See L2D_TLB_REFILL of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L2I_TLB_REFILL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x002e, ++ .desc = "This event counts operations that cause a TLB refill of the L2I TLB. See L2I_TLB_REFILL of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L2D_TLB", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x002f, ++ .desc = "This event counts operations that cause a TLB access to the L2D TLB. See L2D_TLB of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "L2I_TLB", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0030, ++ .desc = "This event counts operations that cause a TLB access to the L2I TLB. See L2I_TLB of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "DTLB_WALK", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0034, ++ .desc = "This event counts data TLB access with at least one translation table walk.", ++ }, ++ { ++ .name = "ITLB_WALK", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0035, ++ .desc = "This event counts instruction TLB access with at least one translation table walk.", ++ }, ++ { ++ .name = "LL_CACHE_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0036, ++ .desc = "This event counts access counted by L3D_CACHE that is a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_CACHE events.", ++ }, ++ { ++ .name = "LL_CACHE_MISS_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0037, ++ .desc = "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events.", ++ }, ++ { ++ .name = "L1D_CACHE_LMISS_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0039, ++ .desc = "This event counts operations that cause a refill of the L1D cache that incurs additional latency.", ++ }, ++ { ++ .name = "OP_RETIRED", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x003a, ++ .desc = "This event counts every architecturally executed micro-operation.", ++ }, ++ { ++ .name = "OP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x003b, ++ .desc = "This event counts every speculatively executed micro-operation.", ++ }, ++ { ++ .name = "STALL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x003c, ++ .desc = "This event counts every cycle that no instruction was dispatched from decode unit.", ++ }, ++ { ++ .name = "STALL_SLOT_BACKEND", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x003d, ++ .desc = "This event counts every cycle that no instruction was dispatched from decode unit due to the backend.", ++ }, ++ { ++ .name = "STALL_SLOT_FRONTEND", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x003e, ++ .desc = "This event counts every cycle that no instruction was dispatched from decode unit due to the frontend.", ++ }, ++ { ++ .name = "STALL_SLOT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x003f, ++ .desc = "This event counts every cycle that no instruction or operation Slot was dispatched from decode unit.", ++ }, ++ { ++ .name = "L1D_CACHE_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0040, ++ .desc = "This event counts L1D CACHE caused by read access.", ++ }, ++ { ++ .name = "L1D_CACHE_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0041, ++ .desc = "This event counts L1D CACHE caused by write access.", ++ }, ++ { ++ .name = "L1D_CACHE_REFILL_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0042, ++ .desc = "This event counts L1D_CACHE_REFILL caused by read access.", ++ }, ++ { ++ .name = "L1D_CACHE_REFILL_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0043, ++ .desc = "This event counts L1D_CACHE_REFILL caused by write access.", ++ }, ++ { ++ .name = "L2D_CACHE_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0050, ++ .desc = "This event counts L2D CACHE caused by read access.", ++ }, ++ { ++ .name = "L2D_CACHE_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0051, ++ .desc = "This event counts L2D CACHE caused by write access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0052, ++ .desc = "This event counts L2D CACHE_REFILL caused by read access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0053, ++ .desc = "This event counts L2D CACHE_REFILL caused by write access.", ++ }, ++ { ++ .name = "L2D_CACHE_WB_VICTIM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0056, ++ .desc = "This event counts every write-back of data from the L2 cache caused by L2 replace.", ++ }, ++ { ++ .name = "MEM_ACCESS_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0066, ++ .desc = "This event counts architecturally executed memory-reading instructions, as defined by the LD_SPEC events.", ++ }, ++ { ++ .name = "LDREX_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x006c, ++ .desc = "This event counts architecturally executed load-exclusive instructions.", ++ }, ++ { ++ .name = "STREX_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x006f, ++ .desc = "This event counts architecturally executed store-exclusive instructions.", ++ }, ++ { ++ .name = "LD_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0070, ++ .desc = "This event counts architecturally executed memory-reading instructions, as defined by the LD_RETIRED event.", ++ }, ++ { ++ .name = "ST_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0071, ++ .desc = "This event counts architecturally executed memory-writing instructions, as defined by the ST_RETIRED event. This event counts DCZVA as a store operation.", ++ }, ++ { ++ .name = "LDST_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0072, ++ .desc = "This event counts architecturally executed memory-reading instructions and memory-writing instructions, as defined by the LD_RETIRED and ST_RETIRED events.", ++ }, ++ { ++ .name = "DP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0073, ++ .desc = "This event counts architecturally executed integer data-processing instructions. See DP_SPEC of ARMv9 Reference Manual for more information.", ++ }, ++ { ++ .name = "ASE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0074, ++ .desc = "This event counts architecturally executed Advanced SIMD data-processing instructions.", ++ }, ++ { ++ .name = "VFP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0075, ++ .desc = "This event counts architecturally executed floating-point data-processing instructions.", ++ }, ++ { ++ .name = "PC_WRITE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0076, ++ .desc = "This event counts only software changes of the PC that defined by the instruction architecturally executed, condition code check pass, software change of the PC event.", ++ }, ++ { ++ .name = "CRYPTO_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0077, ++ .desc = "This event counts architecturally executed cryptographic instructions, except PMULL and VMULL.", ++ }, ++ { ++ .name = "BR_IMMED_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0078, ++ .desc = "This event counts architecturally executed immediate branch instructions.", ++ }, ++ { ++ .name = "BR_RETURN_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0079, ++ .desc = "This event counts architecturally executed procedure return operations that defined by the BR_RETURN_RETIRED event.", ++ }, ++ { ++ .name = "BR_INDIRECT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x007a, ++ .desc = "This event counts architecturally executed indirect branch instructions that includes software change of the PC other than exception-generating instructions and immediate branch instructions.", ++ }, ++ { ++ .name = "ISB_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x007c, ++ .desc = "This event counts architecturally executed Instruction Synchronization Barrier instructions.", ++ }, ++ { ++ .name = "DSB_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x007d, ++ .desc = "This event counts architecturally executed Data Synchronization Barrier instructions.", ++ }, ++ { ++ .name = "DMB_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x007e, ++ .desc = "This event counts architecturally executed Data Memory Barrier instructions, excluding the implied barrier operations of load/store operations with release consistency semantics.", ++ }, ++ { ++ .name = "CSDB_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x007f, ++ .desc = "This event counts speculatively executed control speculation barrier instructions.", ++ }, ++ { ++ .name = "EXC_UNDEF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0081, ++ .desc = "This event counts only other synchronous exceptions that are taken locally.", ++ }, ++ { ++ .name = "EXC_SVC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0082, ++ .desc = "This event counts only Supervisor Call exceptions that are taken locally.", ++ }, ++ { ++ .name = "EXC_PABORT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0083, ++ .desc = "This event counts only Instruction Abort exceptions that are taken locally.", ++ }, ++ { ++ .name = "EXC_DABORT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0084, ++ .desc = "This event counts only Data Abort or SError interrupt exceptions that are taken locally.", ++ }, ++ { ++ .name = "EXC_IRQ", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0086, ++ .desc = "This event counts only IRQ exceptions that are taken locally, including Virtual IRQ exceptions.", ++ }, ++ { ++ .name = "EXC_FIQ", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0087, ++ .desc = "This event counts only FIQ exceptions that are taken locally, including Virtual FIQ exceptions.", ++ }, ++ { ++ .name = "EXC_SMC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0088, ++ .desc = "This event counts only Secure Monitor Call exceptions. The counter does not increment on SMC instructions trapped as a Hyp Trap exception.", ++ }, ++ { ++ .name = "EXC_HVC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x008a, ++ .desc = "This event counts for both Hypervisor Call exceptions taken locally in the hypervisor and those taken as an exception from Non-secure EL1.", ++ }, ++ { ++ .name = "L3D_CACHE_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x00a0, ++ .desc = "This event counts access counted by L3D_CACHE that is a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_CACHE events.", ++ }, ++ { ++ .name = "FP_MV_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0105, ++ .desc = "This event counts architecturally executed floating-point move operations.", ++ }, ++ { ++ .name = "PRD_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0108, ++ .desc = "This event counts architecturally executed operations that using predicate register.", ++ }, ++ { ++ .name = "IEL_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0109, ++ .desc = "This event counts architecturally executed inter-element manipulation operations.", ++ }, ++ { ++ .name = "IREG_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x010a, ++ .desc = "This event counts architecturally executed inter-register manipulation operations.", ++ }, ++ { ++ .name = "FP_LD_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0112, ++ .desc = "This event counts architecturally executed NOSIMD load operations that using SIMD&FP registers.", ++ }, ++ { ++ .name = "FP_ST_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0113, ++ .desc = "This event counts architecturally executed NOSIMD store operations that using SIMD&FP registers.", ++ }, ++ { ++ .name = "BC_LD_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x011a, ++ .desc = "This event counts architecturally executed SIMD broadcast floating-point load operations.", ++ }, ++ { ++ .name = "DCZVA_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x011b, ++ .desc = "This event counts architecturally executed zero blocking operations due to the DC ZVA instruction.", ++ }, ++ { ++ .name = "EFFECTIVE_INST_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0121, ++ .desc = "This event counts architecturally executed instructions, excluding the MOVPRFX instruction.", ++ }, ++ { ++ .name = "PRE_INDEX_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0123, ++ .desc = "This event counts architecturally executed operations that uses pre-index as its addressing mode.", ++ }, ++ { ++ .name = "POST_INDEX_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0124, ++ .desc = "This event counts architecturally executed operations that uses post-index as its addressing mode.", ++ }, ++ { ++ .name = "UOP_SPLIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0139, ++ .desc = "This event counts the occurrence count of the micro-operation split.", ++ }, ++ { ++ .name = "LD_COMP_WAIT_L1_MISS", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0182, ++ .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache access.", ++ }, ++ { ++ .name = "LD_COMP_WAIT_L1_MISS_EX", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0183, ++ .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache access.", ++ }, ++ { ++ .name = "LD_COMP_WAIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0184, ++ .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access.", ++ }, ++ { ++ .name = "LD_COMP_WAIT_EX", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0185, ++ .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access.", ++ }, ++ { ++ .name = "LD_COMP_WAIT_PFP_BUSY", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0186, ++ .desc = "This event counts every cycle that no instruction was committed due to the lack of an available prefetch port.", ++ }, ++ { ++ .name = "LD_COMP_WAIT_PFP_BUSY_EX", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0187, ++ .desc = "This event counts the LD_COMP_WAIT_PFP_BUSY caused by an integer load operation.", ++ }, ++ { ++ .name = "LD_COMP_WAIT_PFP_BUSY_SWPF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0188, ++ .desc = "This event counts the LD_COMP_WAIT_PFP_BUSY caused by a software prefetch instruction.", ++ }, ++ { ++ .name = "EU_COMP_WAIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0189, ++ .desc = "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is an integer or floating-point/SIMD instruction. ", ++ }, ++ { ++ .name = "FL_COMP_WAIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x018a, ++ .desc = "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a floating-point/SIMD instruction.", ++ }, ++ { ++ .name = "BR_COMP_WAIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x018b, ++ .desc = "This event counts every cycle that no instruction was committed and the oldest and uncommitted instruction is a branch instruction.", ++ }, ++ { ++ .name = "ROB_EMPTY", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x018c, ++ .desc = "This event counts every cycle that no instruction was committed because the CSE is empty.", ++ }, ++ { ++ .name = "ROB_EMPTY_STQ_BUSY", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x018d, ++ .desc = "This event counts every cycle that no instruction was committed because the CSE is empty and the store port (SP) is full.", ++ }, ++ { ++ .name = "WFE_WFI_CYCLE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x018e, ++ .desc = "This event counts every cycle that the instruction unit is halted by the WFE/WFI instruction.", ++ }, ++ { ++ .name = "RETENTION_CYCLE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x018f, ++ .desc = "This event counts every cycle that the instruction unit is halted by the RETENTION state.", ++ }, ++ { ++ .name = "_0INST_COMMIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0190, ++ .desc = "This event counts every cycle that no instruction was committed, but counts at the time when commits MOVPRFX only. ", ++ }, ++ { ++ .name = "_1INST_COMMIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0191, ++ .desc = "This event counts every cycle that one instruction is committed.", ++ }, ++ { ++ .name = "_2INST_COMMIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0192, ++ .desc = "This event counts every cycle that two instructions are committed.", ++ }, ++ { ++ .name = "_3INST_COMMIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0193, ++ .desc = "This event counts every cycle that three instructions are committed.", ++ }, ++ { ++ .name = "_4INST_COMMIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0194, ++ .desc = "This event counts every cycle that four instructions are committed.", ++ }, ++ { ++ .name = "_5INST_COMMIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0195, ++ .desc = "This event counts every cycle that five instructions are committed.", ++ }, ++ { ++ .name = "UOP_ONLY_COMMIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0198, ++ .desc = "This event counts every cycle that only any micro-operations are committed.", ++ }, ++ { ++ .name = "SINGLE_MOVPRFX_COMMIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0199, ++ .desc = "This event counts every cycle that only the MOVPRFX instruction is committed.", ++ }, ++ { ++ .name = "LD_COMP_WAIT_L2_MISS", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x019c, ++ .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L2 cache miss.", ++ }, ++ { ++ .name = "LD_COMP_WAIT_L2_MISS_EX", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x019d, ++ .desc = "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L2 cache miss.", ++ }, ++ { ++ .name = "EAGA_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01a0, ++ .desc = "This event counts valid cycles of EAGA pipeline.", ++ }, ++ { ++ .name = "EAGB_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01a1, ++ .desc = "This event counts valid cycles of EAGB pipeline.", ++ }, ++ { ++ .name = "PRX_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01a3, ++ .desc = "This event counts valid cycles of PRX pipeline.", ++ }, ++ { ++ .name = "EXA_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01a4, ++ .desc = "This event counts valid cycles of EXA pipeline.", ++ }, ++ { ++ .name = "EXB_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01a5, ++ .desc = "This event counts valid cycles of EXB pipeline.", ++ }, ++ { ++ .name = "EXC_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01a6, ++ .desc = "This event counts valid cycles of EXC pipeline.", ++ }, ++ { ++ .name = "EXD_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01a7, ++ .desc = "This event counts valid cycles of EXD pipeline.", ++ }, ++ { ++ .name = "FLA_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01a8, ++ .desc = "This event counts valid cycles of FLA pipeline.", ++ }, ++ { ++ .name = "FLB_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01a9, ++ .desc = "This event counts valid cycles of FLB pipeline.", ++ }, ++ { ++ .name = "STEA_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01aa, ++ .desc = "This event counts valid cycles of STEA pipeline.", ++ }, ++ { ++ .name = "STEB_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01ab, ++ .desc = "This event counts valid cycles of STEB pipeline.", ++ }, ++ { ++ .name = "STFL_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01ac, ++ .desc = "This event counts valid cycles of STFL pipeline.", ++ }, ++ { ++ .name = "STPX_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01ad, ++ .desc = "This event counts valid cycles of STPX pipeline.", ++ }, ++ { ++ .name = "FLA_VAL_PRD_CNT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01b0, ++ .desc = "This event counts the number of 1's in the predicate bits of request in FLA pipeline, where it is corrected so that it becomes 32 when all bits are 1.", ++ }, ++ { ++ .name = "FLB_VAL_PRD_CNT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01b1, ++ .desc = "This event counts the number of 1's in the predicate bits of request in FLB pipeline, where it is corrected so that it becomes 32 when all bits are 1.", ++ }, ++ { ++ .name = "FLA_VAL_FOR_PRD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01b2, ++ .desc = "This event counts valid cycles of FLA pipeline.", ++ }, ++ { ++ .name = "FLB_VAL_FOR_PRD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01b3, ++ .desc = "This event counts valid cycles of FLB pipeline.", ++ }, ++ { ++ .name = "EA_CORE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x01f0, ++ .desc = "This event counts energy consumption of core.", ++ }, ++ { ++ .name = "L1D_CACHE_DM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0200, ++ .desc = "This event counts L1D_CACHE caused by demand access.", ++ }, ++ { ++ .name = "L1D_CACHE_DM_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0201, ++ .desc = "This event counts L1D_CACHE caused by demand read access.", ++ }, ++ { ++ .name = "L1D_CACHE_DM_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0202, ++ .desc = "This event counts L1D_CACHE caused by demand write access.", ++ }, ++ { ++ .name = "L1I_CACHE_DM_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0207, ++ .desc = "This event counts L1I_CACHE caused by demand read access.", ++ }, ++ { ++ .name = "L1D_CACHE_REFILL_DM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0208, ++ .desc = "This event counts L1D_CACHE_REFILL caused by demand access.", ++ }, ++ { ++ .name = "L1D_CACHE_REFILL_DM_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0209, ++ .desc = "This event counts L1D_CACHE_REFILL caused by demand read access.", ++ }, ++ { ++ .name = "L1D_CACHE_REFILL_DM_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x020a, ++ .desc = "This event counts L1D_CACHE_REFILL caused by demand write access.", ++ }, ++ { ++ .name = "L1D_CACHE_BTC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x020d, ++ .desc = "This event counts demand access that hits cache line with shared status and requests exclusive access in the Level 1 data cache, causing a coherence access to outside of the Level 1 caches of this PE.", ++ }, ++ { ++ .name = "L1I_CACHE_REFILL_DM_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x020f, ++ .desc = "This event counts L1I_CACHE_REFILL caused by demand read access.", ++ }, ++ { ++ .name = "L1HWPF_STREAM_PF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0230, ++ .desc = "This event counts streaming prefetch requests to L1D cache generated by hardware prefetcher.", ++ }, ++ { ++ .name = "L1HWPF_STRIDE_PF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0231, ++ .desc = "This event counts stride prefetch requests to L1D cache generated by hardware prefetcher.", ++ }, ++ { ++ .name = "L1HWPF_PFTGT_PF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0232, ++ .desc = "This event counts LDS prefetch requests to L1D cache generated by hardware prefetcher.", ++ }, ++ { ++ .name = "L2HWPF_STREAM_PF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0234, ++ .desc = "This event counts streaming prefetch requests to L2 cache generated by hardware prefetcher.", ++ }, ++ { ++ .name = "L2HWPF_STRIDE_PF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0235, ++ .desc = "This event counts stride prefetch requests to L2 cache generated by hardware prefetcher.", ++ }, ++ { ++ .name = "L2HWPF_OTHER", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0237, ++ .desc = "This event counts prefetch requests to L2 cache generated by the other causes.", ++ }, ++ { ++ .name = "L3HWPF_STREAM_PF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0238, ++ .desc = "This event counts streaming prefetch requests to L3 cache generated by hardware prefetcher.", ++ }, ++ { ++ .name = "L3HWPF_STRIDE_PF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0239, ++ .desc = "This event counts stride prefetch requests to L3 cache generated by hardware prefetcher.", ++ }, ++ { ++ .name = "L3HWPF_OTHER", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x023b, ++ .desc = "This event counts prefetch requests to L3 cache generated by the other causes.", ++ }, ++ { ++ .name = "L1IHWPF_NEXTLINE_PF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x023c, ++ .desc = "This event counts next line's prefetch requests to L1I cache generated by hardware prefetcher.", ++ }, ++ { ++ .name = "L1_PIPE0_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0240, ++ .desc = "This event counts valid cycles of L1D cache pipeline#0.", ++ }, ++ { ++ .name = "L1_PIPE1_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0241, ++ .desc = "This event counts valid cycles of L1D cache pipeline#1.", ++ }, ++ { ++ .name = "L1_PIPE2_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0242, ++ .desc = "This event counts valid cycles of L1D cache pipeline#2.", ++ }, ++ { ++ .name = "L1_PIPE0_COMP", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0250, ++ .desc = "This event counts completed requests in L1D cache pipeline#0.", ++ }, ++ { ++ .name = "L1_PIPE1_COMP", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0251, ++ .desc = "This event counts completed requests in L1D cache pipeline#1.", ++ }, ++ { ++ .name = "L1_PIPE_ABORT_STLD_INTLK", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x025a, ++ .desc = "This event counts aborted requests in L1D pipelines that due to store-load interlock.", ++ }, ++ { ++ .name = "L1I_PIPE_COMP", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x026c, ++ .desc = "This event counts completed requests in L1I cache pipeline.", ++ }, ++ { ++ .name = "L1I_PIPE_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x026d, ++ .desc = "This event counts valid cycles of L1I cache pipeline.", ++ }, ++ { ++ .name = "L1_PIPE0_VAL_IU_TAG_ADRS_SCE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0278, ++ .desc = "This event counts requests in L1D cache pipeline#0 that its sce bit of tagged address is 1.", ++ }, ++ { ++ .name = "L1_PIPE1_VAL_IU_TAG_ADRS_SCE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0279, ++ .desc = "This event counts requests in L1D cache pipeline#1 that its sce bit of tagged address is 1.", ++ }, ++ { ++ .name = "L1_PIPE0_VAL_IU_NOT_SEC0", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x02a0, ++ .desc = "This event counts requests in L1D cache pipeline#0 that its sector cache ID is not 0.", ++ }, ++ { ++ .name = "L1_PIPE1_VAL_IU_NOT_SEC0", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x02a1, ++ .desc = "This event counts requests in L1D cache pipeline#1 that its sector cache ID is not 0.", ++ }, ++ { ++ .name = "L1_PIPE_COMP_GATHER_2FLOW", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x02b0, ++ .desc = "This event counts the number of times where 2 elements of the gather instructions became 2 flows because 2 elements could not be combined.", ++ }, ++ { ++ .name = "L1_PIPE_COMP_GATHER_1FLOW", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x02b1, ++ .desc = "This event counts the number of times where 2 elements of the gather instructions became 1 flow because 2 elements could be combined.", ++ }, ++ { ++ .name = "L1_PIPE_COMP_GATHER_0FLOW", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x02b2, ++ .desc = "This event counts the number of times where 2 elements of the gather instructions became 0 flow because both predicate values are 0.", ++ }, ++ { ++ .name = "L1_PIPE_COMP_SCATTER_1FLOW", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x02b3, ++ .desc = "This event counts the number of flows of the scatter instructions.", ++ }, ++ { ++ .name = "L1_PIPE0_COMP_PRD_CNT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x02b8, ++ .desc = "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#0, where it is corrected so that it becomes 64 when all bits are 1.", ++ }, ++ { ++ .name = "L1_PIPE1_COMP_PRD_CNT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x02b9, ++ .desc = "This event counts the number of 1's in the predicate bits of request in L1D cache pipeline#1, where it is corrected so that it becomes 64 when all bits are 1.", ++ }, ++ { ++ .name = "L2D_CACHE_DM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0300, ++ .desc = "This event counts L2D_CACHE caused by demand access.", ++ }, ++ { ++ .name = "L2D_CACHE_DM_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0301, ++ .desc = "This event counts L2D_CACHE caused by demand read access.", ++ }, ++ { ++ .name = "L2D_CACHE_DM_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0302, ++ .desc = "This event counts L2D_CACHE caused by demand write access.", ++ }, ++ { ++ .name = "L2D_CACHE_HWPRF_ADJACENT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0305, ++ .desc = "This event counts L2D_CACHE caused by hardware adjacent prefetch access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_DM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0308, ++ .desc = "This event counts L2D_CACHE_REFILL caused by demand access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_DM_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0309, ++ .desc = "This event counts L2D_CACHE_REFILL caused by demand read access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_DM_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x030a, ++ .desc = "This event counts L2D_CACHE_REFILL caused by demand write access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_DM_WR_EXCL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x030b, ++ .desc = "This event counts L2D_CACHE_REFILL caused by demand write exclusive access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_DM_WR_ATOM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x030c, ++ .desc = "This event counts L2D_CACHE_REFILL caused by demand write atomic access.", ++ }, ++ { ++ .name = "L2D_CACHE_BTC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x030d, ++ .desc = "This event counts demand access that hits cache line with shared status and requests exclusive access in the Level 1 data and Level 2 caches, causing a coherence access to outside of the Level 1 and Level 2 caches of this PE.", ++ }, ++ { ++ .name = "L2_PIPE_VAL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0330, ++ .desc = "This event counts valid cycles of L2 cache pipeline.", ++ }, ++ { ++ .name = "L2_PIPE_COMP_ALL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0350, ++ .desc = "This event counts completed requests in L2 cache pipeline.", ++ }, ++ { ++ .name = "L2_PIPE_COMP_PF_L2MIB_MCH", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0370, ++ .desc = "This event counts operations where software or hardware prefetch hits an L2 cache refill buffer allocated by demand access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_CACHE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0390, ++ .desc = "This event counts operations that cause a cache access to the L3 cache.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_CACHE_DM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0391, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_CACHE_DM_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0392, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand read access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_CACHE_DM_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0393, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by demand write access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_CACHE_PRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0394, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by prefetch access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_CACHE_HWPRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0395, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_CACHE caused by hardware prefetch access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0396, ++ .desc = "This event counts operations that cause a miss of the L3 cache.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0397, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0398, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand read access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_DM_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0399, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by demand write access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_PRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x039a, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by prefetch access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_HWPRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x039b, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS caused by hardware prefetch access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_HIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x039c, ++ .desc = "This event counts operations that cause a hit of the L3 cache.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_HIT_DM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x039d, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_HIT_DM_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x039e, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand read access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_HIT_DM_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x039f, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by demand write access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_HIT_PRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03a0, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by prefetch access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_HIT_HWPRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03a1, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_HIT caused by hardware prefetch access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03a2, ++ .desc = "This event counts the number of L3 cache misses where the requests hit the PFTGT buffer.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03a3, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03a4, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand read access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT_DM_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03a5, ++ .desc = "This event counts L2D_CACHE_REFILL_L3D_MISS_PFTGT_HIT caused by demand write access.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_L_MEM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03a6, ++ .desc = "This event counts the number of L3 cache misses where the requests access the memory in the same socket as the requests.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_FR_MEM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03a7, ++ .desc = "This event counts the number of L3 cache misses where the requests access the memory in the different socket from the requests.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_L_L2", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03a8, ++ .desc = "This event counts the number of L3 cache misses where the requests access the different L2 cache from the requests in the same Numa nodes as the requests.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_NR_L2", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03a9, ++ .desc = "This event counts the number of L3 cache misses where the requests access L2 cache in the different Numa nodes from the requests in the same socket as the requests.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_NR_L3", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03aa, ++ .desc = "This event counts the number of L3 cache misses where the requests access L3 cache in the different Numa nodes from the requests in the same socket as the requests.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_FR_L2", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03ab, ++ .desc = "This event counts the number of L3 cache misses where the requests access L2 cache in the different socket from the requests.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_L3D_MISS_FR_L3", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03ac, ++ .desc = "This event counts the number of L3 cache misses where the requests access L3 cache in the different socket from the requests.", ++ }, ++ { ++ .name = "L2D_CACHE_WB_VICTIM_CLEAN", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03b0, ++ .desc = "This event counts every write-back of data from the L2 cache caused by L2 replace where the data is clean. In this case, the data will usually be written to L3 cache.", ++ }, ++ { ++ .name = "L2D_CACHE_WB_NT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03b1, ++ .desc = "This event counts every write-back of data from the L2 cache caused by non-temporal-store.", ++ }, ++ { ++ .name = "L2D_CACHE_WB_DCZVA", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03b2, ++ .desc = "This event counts every write-back of data from the L2 cache caused by DC ZVA.", ++ }, ++ { ++ .name = "L2D_CACHE_FB", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03b3, ++ .desc = "This event counts every flush-back (drop) of data from the L2 cache.", ++ }, ++ { ++ .name = "EA_L3", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03f0, ++ .desc = "This event counts energy consumption of L3 cache.", ++ }, ++ { ++ .name = "EA_LDO_LOSS", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x03f1, ++ .desc = "This event counts energy consumption of LDO loss.", ++ }, ++ { ++ .name = "GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0880, ++ .desc = "This event counts the number of cycles at 100MHz.", ++ }, ++ { ++ .name = "FL0_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0890, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 0.", ++ }, ++ { ++ .name = "FL1_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0891, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 1.", ++ }, ++ { ++ .name = "FL2_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0892, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 2.", ++ }, ++ { ++ .name = "FL3_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0893, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 3.", ++ }, ++ { ++ .name = "FL4_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0894, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 4.", ++ }, ++ { ++ .name = "FL5_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0895, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 5.", ++ }, ++ { ++ .name = "FL6_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0896, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 6.", ++ }, ++ { ++ .name = "FL7_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0897, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 7.", ++ }, ++ { ++ .name = "FL8_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0898, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 8.", ++ }, ++ { ++ .name = "FL9_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0899, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 9.", ++ }, ++ { ++ .name = "FL10_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x089a, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 10.", ++ }, ++ { ++ .name = "FL11_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x089b, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 11.", ++ }, ++ { ++ .name = "FL12_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x089c, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 12.", ++ }, ++ { ++ .name = "FL13_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x089d, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 13.", ++ }, ++ { ++ .name = "FL14_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x089e, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 14.", ++ }, ++ { ++ .name = "FL15_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x089f, ++ .desc = "This event counts the number of cycles where the measured core is staying in the Frequency Level 15.", ++ }, ++ { ++ .name = "RETENTION_GCYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x08a0, ++ .desc = "This event counts the number of cycles where the measured core is staying in the RETENTION state.", ++ }, ++ { ++ .name = "RETENTION_COUNT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x08a1, ++ .desc = "This event counts the number of changes from the normal state to the RETENTION state.", ++ }, ++ { ++ .name = "L1I_TLB_4K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c00, ++ .desc = "This event counts operations that cause a TLB access to the L1I in 4KB page.", ++ }, ++ { ++ .name = "L1I_TLB_64K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c01, ++ .desc = "This event counts operations that cause a TLB access to the L1I in 64KB page.", ++ }, ++ { ++ .name = "L1I_TLB_2M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c02, ++ .desc = "This event counts operations that cause a TLB access to the L1I in 2MB page.", ++ }, ++ { ++ .name = "L1I_TLB_32M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c03, ++ .desc = "This event counts operations that cause a TLB access to the L1I in 32MB page.", ++ }, ++ { ++ .name = "L1I_TLB_512M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c04, ++ .desc = "This event counts operations that cause a TLB access to the L1I in 512MB page.", ++ }, ++ { ++ .name = "L1I_TLB_1G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c05, ++ .desc = "This event counts operations that cause a TLB access to the L1I in 1GB page.", ++ }, ++ { ++ .name = "L1I_TLB_16G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c06, ++ .desc = "This event counts operations that cause a TLB access to the L1I in 16GB page.", ++ }, ++ { ++ .name = "L1D_TLB_4K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c08, ++ .desc = "This event counts operations that cause a TLB access to the L1D in 4KB page.", ++ }, ++ { ++ .name = "L1D_TLB_64K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c09, ++ .desc = "This event counts operations that cause a TLB access to the L1D in 64KB page.", ++ }, ++ { ++ .name = "L1D_TLB_2M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c0a, ++ .desc = "This event counts operations that cause a TLB access to the L1D in 2MB page.", ++ }, ++ { ++ .name = "L1D_TLB_32M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c0b, ++ .desc = "This event counts operations that cause a TLB access to the L1D in 32MB page.", ++ }, ++ { ++ .name = "L1D_TLB_512M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c0c, ++ .desc = "This event counts operations that cause a TLB access to the L1D in 512MB page.", ++ }, ++ { ++ .name = "L1D_TLB_1G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c0d, ++ .desc = "This event counts operations that cause a TLB access to the L1D in 1GB page.", ++ }, ++ { ++ .name = "L1D_TLB_16G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c0e, ++ .desc = "This event counts operations that cause a TLB access to the L1D in 16GB page.", ++ }, ++ { ++ .name = "L1I_TLB_REFILL_4K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c10, ++ .desc = "This event counts operations that cause a TLB refill to the L1I in 4KB page.", ++ }, ++ { ++ .name = "L1I_TLB_REFILL_64K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c11, ++ .desc = "This event counts operations that cause a TLB refill to the L1I in 64KB page.", ++ }, ++ { ++ .name = "L1I_TLB_REFILL_2M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c12, ++ .desc = "This event counts operations that cause a TLB refill to the L1I in 2MB page.", ++ }, ++ { ++ .name = "L1I_TLB_REFILL_32M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c13, ++ .desc = "This event counts operations that cause a TLB refill to the L1I in 32MB page.", ++ }, ++ { ++ .name = "L1I_TLB_REFILL_512M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c14, ++ .desc = "This event counts operations that cause a TLB refill to the L1I in 512MB page.", ++ }, ++ { ++ .name = "L1I_TLB_REFILL_1G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c15, ++ .desc = "This event counts operations that cause a TLB refill to the L1I in 1GB page.", ++ }, ++ { ++ .name = "L1I_TLB_REFILL_16G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c16, ++ .desc = "This event counts operations that cause a TLB refill to the L1I in 16GB page.", ++ }, ++ { ++ .name = "L1D_TLB_REFILL_4K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c18, ++ .desc = "This event counts operations that cause a TLB refill to the L1D in 4KB page.", ++ }, ++ { ++ .name = "L1D_TLB_REFILL_64K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c19, ++ .desc = "This event counts operations that cause a TLB refill to the L1D in 64KB page.", ++ }, ++ { ++ .name = "L1D_TLB_REFILL_2M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c1a, ++ .desc = "This event counts operations that cause a TLB refill to the L1D in 2MB page.", ++ }, ++ { ++ .name = "L1D_TLB_REFILL_32M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c1b, ++ .desc = "This event counts operations that cause a TLB refill to the L1D in 32MB page.", ++ }, ++ { ++ .name = "L1D_TLB_REFILL_512M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c1c, ++ .desc = "This event counts operations that cause a TLB refill to the L1D in 512MB page.", ++ }, ++ { ++ .name = "L1D_TLB_REFILL_1G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c1d, ++ .desc = "This event counts operations that cause a TLB refill to the L1D in 1GB page.", ++ }, ++ { ++ .name = "L1D_TLB_REFILL_16G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c1e, ++ .desc = "This event counts operations that cause a TLB refill to the L1D in 16GB page.", ++ }, ++ { ++ .name = "L2I_TLB_4K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c20, ++ .desc = "This event counts operations that cause a TLB access to the L2I in 4KB page.", ++ }, ++ { ++ .name = "L2I_TLB_64K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c21, ++ .desc = "This event counts operations that cause a TLB access to the L2I in 64KB page.", ++ }, ++ { ++ .name = "L2I_TLB_2M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c22, ++ .desc = "This event counts operations that cause a TLB access to the L2I in 2MB page.", ++ }, ++ { ++ .name = "L2I_TLB_32M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c23, ++ .desc = "This event counts operations that cause a TLB access to the L2I in 32MB page.", ++ }, ++ { ++ .name = "L2I_TLB_512M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c24, ++ .desc = "This event counts operations that cause a TLB access to the L2I in 512MB page.", ++ }, ++ { ++ .name = "L2I_TLB_1G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c25, ++ .desc = "This event counts operations that cause a TLB access to the L2I in 1GB page.", ++ }, ++ { ++ .name = "L2I_TLB_16G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c26, ++ .desc = "This event counts operations that cause a TLB access to the L2I in 16GB page.", ++ }, ++ { ++ .name = "L2D_TLB_4K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c28, ++ .desc = "This event counts operations that cause a TLB access to the L2D in 4KB page.", ++ }, ++ { ++ .name = "L2D_TLB_64K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c29, ++ .desc = "This event counts operations that cause a TLB access to the L2D in 64KB page.", ++ }, ++ { ++ .name = "L2D_TLB_2M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c2a, ++ .desc = "This event counts operations that cause a TLB access to the L2D in 2MB page.", ++ }, ++ { ++ .name = "L2D_TLB_32M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c2b, ++ .desc = "This event counts operations that cause a TLB access to the L2D in 32MB page.", ++ }, ++ { ++ .name = "L2D_TLB_512M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c2c, ++ .desc = "This event counts operations that cause a TLB access to the L2D in 512MB page.", ++ }, ++ { ++ .name = "L2D_TLB_1G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c2d, ++ .desc = "This event counts operations that cause a TLB access to the L2D in 1GB page.", ++ }, ++ { ++ .name = "L2D_TLB_16G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c2e, ++ .desc = "This event counts operations that cause a TLB access to the L2D in 16GB page.", ++ }, ++ { ++ .name = "L2I_TLB_REFILL_4K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c30, ++ .desc = "This event counts operations that cause a TLB refill to the L2Iin 4KB page.", ++ }, ++ { ++ .name = "L2I_TLB_REFILL_64K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c31, ++ .desc = "This event counts operations that cause a TLB refill to the L2I in 64KB page.", ++ }, ++ { ++ .name = "L2I_TLB_REFILL_2M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c32, ++ .desc = "This event counts operations that cause a TLB refill to the L2I in 2MB page.", ++ }, ++ { ++ .name = "L2I_TLB_REFILL_32M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c33, ++ .desc = "This event counts operations that cause a TLB refill to the L2I in 32MB page.", ++ }, ++ { ++ .name = "L2I_TLB_REFILL_512M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c34, ++ .desc = "This event counts operations that cause a TLB refill to the L2I in 512MB page.", ++ }, ++ { ++ .name = "L2I_TLB_REFILL_1G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c35, ++ .desc = "This event counts operations that cause a TLB refill to the L2I in 1GB page.", ++ }, ++ { ++ .name = "L2I_TLB_REFILL_16G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c36, ++ .desc = "This event counts operations that cause a TLB refill to the L2I in 16GB page.", ++ }, ++ { ++ .name = "L2D_TLB_REFILL_4K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c38, ++ .desc = "This event counts operations that cause a TLB refill to the L2D in 4KB page.", ++ }, ++ { ++ .name = "L2D_TLB_REFILL_64K", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c39, ++ .desc = "This event counts operations that cause a TLB refill to the L2D in 64KB page.", ++ }, ++ { ++ .name = "L2D_TLB_REFILL_2M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c3a, ++ .desc = "This event counts operations that cause a TLB refill to the L2D in 2MB page.", ++ }, ++ { ++ .name = "L2D_TLB_REFILL_32M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c3b, ++ .desc = "This event counts operations that cause a TLB refill to the L2D in 32MB page.", ++ }, ++ { ++ .name = "L2D_TLB_REFILL_512M", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c3c, ++ .desc = "This event counts operations that cause a TLB refill to the L2D in 512MB page.", ++ }, ++ { ++ .name = "L2D_TLB_REFILL_1G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c3d, ++ .desc = "This event counts operations that cause a TLB refill to the L2D in 1GB page.", ++ }, ++ { ++ .name = "L2D_TLB_REFILL_16G", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x0c3e, ++ .desc = "This event counts operations that cause a TLB refill to the L2D in 16GB page.", ++ }, ++ { ++ .name = "CNT_CYCLES", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x4004, ++ .desc = "This event counts the constant frequency cycles counter increments at a constant frequency equal to the rate of increment of the System counter.", ++ }, ++ { ++ .name = "STALL_BACKEND_MEM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x4005, ++ .desc = "This event counts every cycle that no instruction was dispatched from decode unit due to memory stall.", ++ }, ++ { ++ .name = "L1I_CACHE_LMISS", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x4006, ++ .desc = "This event counts operations that cause a refill of the L1I cache that incurs additional latency.", ++ }, ++ { ++ .name = "L2D_CACHE_LMISS_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x4009, ++ .desc = "This event counts operations that cause a refill of the L2D cache that incurs additional latency.", ++ }, ++ { ++ .name = "L3D_CACHE_LMISS_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x400b, ++ .desc = "This event counts access counted by L3D_CACHE that is not completed by the L3D cache, and a Memory-read operation, as defined by the L2D_CACHE_REFILL_L3D_MISS events.", ++ }, ++ { ++ .name = "TRB_WRAP", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x400c, ++ .desc = "This event counts the event generated each time the current write pointer is wrapped to the base pointer.", ++ }, ++ { ++ .name = "PMU_OVFS", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x400d, ++ .desc = "This event counts the event generated each time one of the condition occurs described in Arm Architecture Reference Manual for A-profile architecture. This event is only for output to the trace unit.", ++ }, ++ { ++ .name = "TRB_TRIG", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x400e, ++ .desc = "This event counts the event generated when a Trace Buffer Extension Trigger Event occurs.", ++ }, ++ { ++ .name = "PMU_HOVFS", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x400f, ++ .desc = "This event counts the event generated each time an event is counted by an event counter and all of the condition occur described in Arm Architecture Reference Manual for A-profile architecture. This event is only for output to the trace unit.", ++ }, ++ { ++ .name = "TRCEXTOUT0", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x4010, ++ .desc = "This event counts the event generated each time an event is signaled by the trace unit external event 0.", ++ }, ++ { ++ .name = "CTI_TRIGOUT4", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x4018, ++ .desc = "This event counts the event generated each time an event is signaled on CTI output trigger 4.", ++ }, ++ { ++ .name = "SIMD_INST_RETIRED", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8000, ++ .desc = "This event counts architecturally executed SIMD instructions, excluding the Advanced SIMD scalar instructions and the instructions listed in Non-SIMD SVE instructions section of ARMv9 Reference Manual.", ++ }, ++ { ++ .name = "SVE_INST_RETIRED", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8002, ++ .desc = "This event counts architecturally executed SVE instructions, including the instructions listed in Non-SIMD SVE instructions section of ARMv9 Reference Manual.", ++ }, ++ { ++ .name = "ASE_INST_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8005, ++ .desc = "This event counts architecturally executed Advanced SIMD operations.", ++ }, ++ { ++ .name = "SVE_INST_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8006, ++ .desc = "This event counts architecturally executed SVE instructions, including the instructions listed in Non-SIMD SVE instructions section of ARMv9 Reference Manual.", ++ }, ++ { ++ .name = "ASE_SVE_INST_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8007, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE operations.", ++ }, ++ { ++ .name = "UOP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8008, ++ .desc = "This event counts all architecturally executed micro-operations.", ++ }, ++ { ++ .name = "SVE_MATH_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x800e, ++ .desc = "This event counts architecturally executed math function operations due to the SVE FTSMUL, FTMAD, FTSSEL, and FEXPA instructions.", ++ }, ++ { ++ .name = "FP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8010, ++ .desc = "This event counts architecturally executed operations due to scalar, Advanced SIMD, and SVE instructions listed in Floating-point instructions section of ARMv9 Reference Manual.", ++ }, ++ { ++ .name = "ASE_FP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8011, ++ .desc = "This event counts architecturally executed Advanced SIMD floating-point operation.", ++ }, ++ { ++ .name = "SVE_FP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8012, ++ .desc = "This event counts architecturally executed SVE floating-point operation.", ++ }, ++ { ++ .name = "ASE_SVE_FP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8013, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point operations.", ++ }, ++ { ++ .name = "FP_HP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8014, ++ .desc = "This event counts architecturally executed half-precision floating-point operation.", ++ }, ++ { ++ .name = "ASE_FP_HP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8015, ++ .desc = "This event counts architecturally executed Advanced SIMD half-precision floating-point operation.", ++ }, ++ { ++ .name = "SVE_FP_HP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8016, ++ .desc = "This event counts architecturally executed SVE half-precision floating-point operation.", ++ }, ++ { ++ .name = "ASE_SVE_FP_HP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8017, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE half-precision floating-point operations.", ++ }, ++ { ++ .name = "FP_SP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8018, ++ .desc = "This event counts architecturally executed single-precision floating-point operation.", ++ }, ++ { ++ .name = "ASE_FP_SP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8019, ++ .desc = "This event counts architecturally executed Advanced SIMD single-precision floating-point operation.", ++ }, ++ { ++ .name = "SVE_FP_SP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x801a, ++ .desc = "This event counts architecturally executed SVE single-precision floating-point operation.", ++ }, ++ { ++ .name = "ASE_SVE_FP_SP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x801b, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE single-precision floating-point operations.", ++ }, ++ { ++ .name = "FP_DP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x801c, ++ .desc = "This event counts architecturally executed double-precision floating-point operation.", ++ }, ++ { ++ .name = "ASE_FP_DP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x801d, ++ .desc = "This event counts architecturally executed Advanced SIMD double-precision floating-point operation.", ++ }, ++ { ++ .name = "SVE_FP_DP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x801e, ++ .desc = "This event counts architecturally executed SVE double-precision floating-point operation.", ++ }, ++ { ++ .name = "ASE_SVE_FP_DP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x801f, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE double-precision floating-point operations.", ++ }, ++ { ++ .name = "FP_DIV_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8020, ++ .desc = "This event counts architecturally executed floating-point divide operation.", ++ }, ++ { ++ .name = "ASE_FP_DIV_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8021, ++ .desc = "This event counts architecturally executed Advanced SIMD floating-point divide operation.", ++ }, ++ { ++ .name = "SVE_FP_DIV_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8022, ++ .desc = "This event counts architecturally executed SVE floating-point divide operation.", ++ }, ++ { ++ .name = "ASE_SVE_FP_DIV_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8023, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point divide operations.", ++ }, ++ { ++ .name = "FP_SQRT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8024, ++ .desc = "This event counts architecturally executed floating-point square root operation.", ++ }, ++ { ++ .name = "ASE_FP_SQRT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8025, ++ .desc = "This event counts architecturally executed Advanced SIMD floating-point square root operation.", ++ }, ++ { ++ .name = "SVE_FP_SQRT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8026, ++ .desc = "This event counts architecturally executed SVE floating-point square root operation.", ++ }, ++ { ++ .name = "ASE_SVE_FP_SQRT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8027, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point square root operations.", ++ }, ++ { ++ .name = "FP_FMA_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8028, ++ .desc = "This event counts architecturally executed floating-point fused multiply-add and multiply-subtract operations.", ++ }, ++ { ++ .name = "ASE_FP_FMA_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8029, ++ .desc = "This event counts architecturally executed Advanced SIMD floating-point FMA operation.", ++ }, ++ { ++ .name = "SVE_FP_FMA_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x802a, ++ .desc = "This event counts architecturally executed SVE floating-point FMA operation.", ++ }, ++ { ++ .name = "ASE_SVE_FP_FMA_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x802b, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point FMA operations.", ++ }, ++ { ++ .name = "FP_MUL_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x802c, ++ .desc = "This event counts architecturally executed floating-point multiply operations.", ++ }, ++ { ++ .name = "ASE_FP_MUL_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x802d, ++ .desc = "This event counts architecturally executed Advanced SIMD floating-point multiply operation.", ++ }, ++ { ++ .name = "SVE_FP_MUL_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x802e, ++ .desc = "This event counts architecturally executed SVE floating-point multiply operation.", ++ }, ++ { ++ .name = "ASE_SVE_FP_MUL_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x802f, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point multiply operations.", ++ }, ++ { ++ .name = "FP_ADDSUB_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8030, ++ .desc = "This event counts architecturally executed floating-point add or subtract operations.", ++ }, ++ { ++ .name = "ASE_FP_ADDSUB_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8031, ++ .desc = "This event counts architecturally executed Advanced SIMD floating-point add or subtract operation.", ++ }, ++ { ++ .name = "SVE_FP_ADDSUB_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8032, ++ .desc = "This event counts architecturally executed SVE floating-point add or subtract operation.", ++ }, ++ { ++ .name = "ASE_SVE_FP_ADDSUB_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8033, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point add or subtract operations.", ++ }, ++ { ++ .name = "FP_RECPE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8034, ++ .desc = "This event counts architecturally executed floating-point reciprocal estimate operations due to the Advanced SIMD scalar, Advanced SIMD vector, and SVE FRECPE and FRSQRTE instructions.", ++ }, ++ { ++ .name = "ASE_FP_RECPE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8035, ++ .desc = "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operations.", ++ }, ++ { ++ .name = "SVE_FP_RECPE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8036, ++ .desc = "This event counts architecturally executed SVE floating-point reciprocal estimate operations.", ++ }, ++ { ++ .name = "ASE_SVE_FP_RECPE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8037, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point reciprocal estimate operations.", ++ }, ++ { ++ .name = "FP_CVT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8038, ++ .desc = "This event counts architecturally executed floating-point convert operations due to the scalar, Advanced SIMD, and SVE floating-point conversion instructions listed in Floating-point conversions section of ARMv9 Reference Manual.", ++ }, ++ { ++ .name = "ASE_FP_CVT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8039, ++ .desc = "This event counts architecturally executed Advanced SIMD floating-point convert operation.", ++ }, ++ { ++ .name = "SVE_FP_CVT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x803a, ++ .desc = "This event counts architecturally executed SVE floating-point convert operation.", ++ }, ++ { ++ .name = "ASE_SVE_FP_CVT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x803b, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point convert operations.", ++ }, ++ { ++ .name = "SVE_FP_AREDUCE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x803c, ++ .desc = "This event counts architecturally executed SVE floating-point accumulating reduction operations.", ++ }, ++ { ++ .name = "ASE_FP_PREDUCE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x803d, ++ .desc = "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operations.", ++ }, ++ { ++ .name = "SVE_FP_VREDUCE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x803e, ++ .desc = "This event counts architecturally executed SVE floating-point vector reduction operation.", ++ }, ++ { ++ .name = "ASE_SVE_FP_VREDUCE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x803f, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE floating-point vector reduction operations.", ++ }, ++ { ++ .name = "INT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8040, ++ .desc = "This event counts architecturally executed operations due to scalar, Advanced SIMD, and SVE instructions listed in Integer instructions section of ARMv9 Reference Manual.", ++ }, ++ { ++ .name = "ASE_INT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8041, ++ .desc = "This event counts architecturally executed Advanced SIMD integer operations.", ++ }, ++ { ++ .name = "SVE_INT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8042, ++ .desc = "This event counts architecturally executed SVE integer operations.", ++ }, ++ { ++ .name = "ASE_SVE_INT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8043, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE integer operations.", ++ }, ++ { ++ .name = "INT_DIV_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8044, ++ .desc = "This event counts architecturally executed integer divide operation.", ++ }, ++ { ++ .name = "INT_DIV64_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8045, ++ .desc = "This event counts architecturally executed 64-bit integer divide operation.", ++ }, ++ { ++ .name = "SVE_INT_DIV_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8046, ++ .desc = "This event counts architecturally executed SVE integer divide operation.", ++ }, ++ { ++ .name = "SVE_INT_DIV64_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8047, ++ .desc = "This event counts architecturally executed SVE 64-bit integer divide operation.", ++ }, ++ { ++ .name = "INT_MUL_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8048, ++ .desc = "This event counts architecturally executed integer multiply operation.", ++ }, ++ { ++ .name = "ASE_INT_MUL_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8049, ++ .desc = "This event counts architecturally executed Advanced SIMD integer multiply operation.", ++ }, ++ { ++ .name = "SVE_INT_MUL_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x804a, ++ .desc = "This event counts architecturally executed SVE integer multiply operation.", ++ }, ++ { ++ .name = "ASE_SVE_INT_MUL_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x804b, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE integer multiply operations.", ++ }, ++ { ++ .name = "INT_MUL64_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x804c, ++ .desc = "This event counts architecturally executed integer 64-bit x 64-bit multiply operation.", ++ }, ++ { ++ .name = "SVE_INT_MUL64_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x804d, ++ .desc = "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply operation.", ++ }, ++ { ++ .name = "INT_MULH64_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x804e, ++ .desc = "This event counts architecturally executed integer 64-bit x 64-bit multiply returning high part operation.", ++ }, ++ { ++ .name = "SVE_INT_MULH64_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x804f, ++ .desc = "This event counts architecturally executed SVE integer 64-bit x 64-bit multiply returning high part operations.", ++ }, ++ { ++ .name = "NONFP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8058, ++ .desc = "This event counts architecturally executed non-floating-point operations.", ++ }, ++ { ++ .name = "ASE_NONFP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8059, ++ .desc = "This event counts architecturally executed Advanced SIMD non-floating-point operations.", ++ }, ++ { ++ .name = "SVE_NONFP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x805a, ++ .desc = "This event counts architecturally executed SVE non-floating-point operations.", ++ }, ++ { ++ .name = "ASE_SVE_NONFP_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x805b, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE non-floating-point operations.", ++ }, ++ { ++ .name = "ASE_INT_VREDUCE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x805d, ++ .desc = "This event counts architecturally executed Advanced SIMD integer reduction operation.", ++ }, ++ { ++ .name = "SVE_INT_VREDUCE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x805e, ++ .desc = "This event counts architecturally executed SVE integer reduction operation.", ++ }, ++ { ++ .name = "ASE_SVE_INT_VREDUCE_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x805f, ++ .desc = "This event counts architecturally executed Advanced SIMD and SVE integer reduction operations.", ++ }, ++ { ++ .name = "SVE_PERM_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8060, ++ .desc = "This event counts architecturally executed vector or predicate permute operation.", ++ }, ++ { ++ .name = "SVE_XPIPE_Z2R_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8065, ++ .desc = "This event counts architecturally executed vector to general-purpose scalar cross-pipeline transfer operation.", ++ }, ++ { ++ .name = "SVE_XPIPE_R2Z_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8066, ++ .desc = "This event counts architecturally executed general-purpose scalar to vector cross-pipeline transfer operation.", ++ }, ++ { ++ .name = "SVE_PGEN_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8068, ++ .desc = "This event counts architecturally executed predicate-generating operation.", ++ }, ++ { ++ .name = "SVE_PGEN_FLG_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8069, ++ .desc = "This event counts architecturally executed predicate-generating operation that sets condition flags.", ++ }, ++ { ++ .name = "SVE_PPERM_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x806d, ++ .desc = "This event counts architecturally executed predicate permute operation.", ++ }, ++ { ++ .name = "SVE_PRED_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8074, ++ .desc = "This event counts architecturally executed SIMD data-processing and load/store operations due to SVE instructions with a Governing predicate operand that determines the Active elements.", ++ }, ++ { ++ .name = "SVE_MOVPRFX_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x807c, ++ .desc = "This event counts architecturally executed operations due to MOVPRFX instructions, whether or not they were fused with the prefixed instruction.", ++ }, ++ { ++ .name = "SVE_MOVPRFX_Z_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x807d, ++ .desc = "This event counts architecturally executed operation counted by SVE_MOVPRFX_SPEC where the operation uses zeroing predication.", ++ }, ++ { ++ .name = "SVE_MOVPRFX_M_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x807e, ++ .desc = "This event counts architecturally executed operation counted by SVE_MOVPRFX_SPEC where the operation uses merging predication.", ++ }, ++ { ++ .name = "SVE_MOVPRFX_U_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x807f, ++ .desc = "This event counts architecturally executed operations due to MOVPRFX instructions that were not fused with the prefixed instruction.", ++ }, ++ { ++ .name = "ASE_SVE_LD_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8085, ++ .desc = "This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD load instructions.", ++ }, ++ { ++ .name = "ASE_SVE_ST_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8086, ++ .desc = "This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD store instructions.", ++ }, ++ { ++ .name = "PRF_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8087, ++ .desc = "This event counts architecturally executed prefetch operations due to scalar PRFM, PRFUM and SVE PRF instructions.", ++ }, ++ { ++ .name = "BASE_LD_REG_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8089, ++ .desc = "This event counts architecturally executed operations that read from memory due to an instruction that loads a general-purpose register.", ++ }, ++ { ++ .name = "BASE_ST_REG_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x808a, ++ .desc = "This event counts architecturally executed operations that write to memory due to an instruction that stores a general-purpose register, excluding the DC ZVA instruction.", ++ }, ++ { ++ .name = "SVE_LDR_REG_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8091, ++ .desc = "This event counts architecturally executed operations that read from memory due to an SVE LDR instruction.", ++ }, ++ { ++ .name = "SVE_STR_REG_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8092, ++ .desc = "This event counts architecturally executed operations that write to memory due to an SVE STR instruction.", ++ }, ++ { ++ .name = "SVE_LDR_PREG_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8095, ++ .desc = "This event counts architecturally executed operations that read from memory due to an SVE LDR (predicate) instruction.", ++ }, ++ { ++ .name = "SVE_STR_PREG_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8096, ++ .desc = "This event counts architecturally executed operations that write to memory due to an SVE STR (predicate) instruction.", ++ }, ++ { ++ .name = "SVE_PRF_CONTIG_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x809f, ++ .desc = "This event counts architecturally executed operations that prefetch memory due to an SVE predicated single contiguous element prefetch instruction.", ++ }, ++ { ++ .name = "SVE_LDNT_CONTIG_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80a1, ++ .desc = "This event counts architecturally executed operation that reads from memory with a non-temporal hint due to an SVE non-temporal contiguous element load instruction.", ++ }, ++ { ++ .name = "SVE_STNT_CONTIG_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80a2, ++ .desc = "This event counts architecturally executed operation that writes to memory with a non-temporal hint due to an SVE non-temporal contiguous element store instruction.", ++ }, ++ { ++ .name = "ASE_SVE_LD_MULTI_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80a5, ++ .desc = "This event counts architecturally executed operations that read from memory due to SVE and Advanced SIMD multiple vector contiguous structure load instructions.", ++ }, ++ { ++ .name = "ASE_SVE_ST_MULTI_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80a6, ++ .desc = "This event counts architecturally executed operations that write to memory due to SVE and Advanced SIMD multiple vector contiguous structure store instructions.", ++ }, ++ { ++ .name = "SVE_LD_GATHER_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80ad, ++ .desc = "This event counts architecturally executed operations that read from memory due to SVE non-contiguous gather-load instructions.", ++ }, ++ { ++ .name = "SVE_ST_SCATTER_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80ae, ++ .desc = "This event counts architecturally executed operations that write to memory due to SVE non-contiguous scatter-store instructions.", ++ }, ++ { ++ .name = "SVE_PRF_GATHER_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80af, ++ .desc = "This event counts architecturally executed operations that prefetch memory due to SVE non-contiguous gather-prefetch instructions.", ++ }, ++ { ++ .name = "SVE_LDFF_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80bc, ++ .desc = "This event counts architecturally executed memory read operations due to SVE First-fault and Non-fault load instructions.", ++ }, ++ { ++ .name = "FP_SCALE_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80c0, ++ .desc = "This event counts architecturally executed SVE arithmetic operations. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC.", ++ }, ++ { ++ .name = "FP_FIXED_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80c1, ++ .desc = "This event counts architecturally executed v8SIMD&FP arithmetic operations. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. The event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", ++ }, ++ { ++ .name = "FP_HP_SCALE_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80c2, ++ .desc = "This event counts architecturally executed SVE half-precision arithmetic operations. See FP_HP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 8, or by 16 for operations that would also be counted by SVE_FP_FMA_SPEC.", ++ }, ++ { ++ .name = "FP_HP_FIXED_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80c3, ++ .desc = "This event counts architecturally executed v8SIMD&FP half-precision arithmetic operations. See FP_HP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 16-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", ++ }, ++ { ++ .name = "FP_SP_SCALE_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80c4, ++ .desc = "This event counts architecturally executed SVE single-precision arithmetic operations. See FP_SP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 4, or by 8 for operations that would also be counted by SVE_FP_FMA_SPEC.", ++ }, ++ { ++ .name = "FP_SP_FIXED_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80c5, ++ .desc = "This event counts architecturally executed v8SIMD&FP single-precision arithmetic operations. See FP_SP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the number of 32-bit elements for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", ++ }, ++ { ++ .name = "FP_DP_SCALE_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80c6, ++ .desc = "This event counts architecturally executed SVE double-precision arithmetic operations. See FP_DP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2, or by 4 for operations that would also be counted by SVE_FP_FMA_SPEC.", ++ }, ++ { ++ .name = "FP_DP_FIXED_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80c7, ++ .desc = "This event counts architecturally executed v8SIMD&FP double-precision arithmetic operations. See FP_DP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by 2 for Advanced SIMD operations, or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC.", ++ }, ++ { ++ .name = "INT_SCALE_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80c8, ++ .desc = "This event counts each integer ALU operation counted by SVE_INT_SPEC. See ALU operation counts section of ARMv9 Reference Manual for information on the counter increment for different types of instruction.", ++ }, ++ { ++ .name = "INT_FIXED_OPS_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80c9, ++ .desc = "This event counts each integer ALU operation counted by INT_SPEC that is not counted by SVE_INT_SPEC. See ALU operation counts section of ARMv9 Reference Manual for information on the counter increment for different types of instruction.", ++ }, ++ { ++ .name = "ASE_SVE_FP_DOT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80f3, ++ .desc = "This event counts architecturally executed microarchitectural Advanced SIMD or SVE floating-point dot-product operation.", ++ }, ++ { ++ .name = "ASE_SVE_FP_MMLA_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80f7, ++ .desc = "This event counts architecturally executed microarchitectural Advanced SIMD or SVE floating-point matrix multiply operation.", ++ }, ++ { ++ .name = "ASE_SVE_INT_DOT_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80fb, ++ .desc = "This event counts architecturally executed microarchitectural Advanced SIMD or SVE integer dot-product operation.", ++ }, ++ { ++ .name = "ASE_SVE_INT_MMLA_SPEC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x80ff, ++ .desc = "This event counts architecturally executed microarchitectural Advanced SIMD or SVE integer matrix multiply operation.", ++ }, ++ { ++ .name = "DTLB_WALK_PERCYC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8128, ++ .desc = "This event counts the number of DTLB_WALK events in progress on each Processor cycle.", ++ }, ++ { ++ .name = "ITLB_WALK_PERCYC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8129, ++ .desc = "This event counts the number of ITLB_WALK events in progress on each Processor cycle.", ++ }, ++ { ++ .name = "DTLB_STEP", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8136, ++ .desc = "This event counts translation table walk access made by a refill of the data TLB.", ++ }, ++ { ++ .name = "ITLB_STEP", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8137, ++ .desc = "This event counts translation table walk access made by a refill of the instruction TLB.", ++ }, ++ { ++ .name = "DTLB_WALK_LARGE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8138, ++ .desc = "This event counts translation table walk counted by DTLB_WALK where the result of the walk yields a large page size.", ++ }, ++ { ++ .name = "ITLB_WALK_LARGE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8139, ++ .desc = "This event counts translation table walk counted by ITLB_WALK where the result of the walk yields a large page size.", ++ }, ++ { ++ .name = "DTLB_WALK_SMALL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x813a, ++ .desc = "This event counts translation table walk counted by DTLB_WALK where the result of the walk yields a small page size.", ++ }, ++ { ++ .name = "ITLB_WALK_SMALL", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x813b, ++ .desc = "This event counts translation table walk counted by ITLB_WALK where the result of the walk yields a small page size.", ++ }, ++ { ++ .name = "L1D_CACHE_MISS", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8144, ++ .desc = "This event counts demand access that misses in the Level 1 data cache, causing an access to outside of the Level 1 caches of this PE.", ++ }, ++ { ++ .name = "L1I_CACHE_HWPRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8145, ++ .desc = "This event counts access counted by L1I_CACHE that is due to a hardware prefetch.", ++ }, ++ { ++ .name = "L2D_CACHE_MISS", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x814c, ++ .desc = "This event counts demand access that misses in the Level 1 data and Level 2 caches, causing an access to outside of the Level 1 and Level 2 caches of this PE.", ++ }, ++ { ++ .name = "L1D_CACHE_HWPRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8154, ++ .desc = "This event counts access counted by L1D_CACHE that is due to a hardware prefetch.", ++ }, ++ { ++ .name = "L2D_CACHE_HWPRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8155, ++ .desc = "This event counts access counted by L2D_CACHE that is due to a hardware prefetch.", ++ }, ++ { ++ .name = "STALL_FRONTEND_MEMBOUND", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8158, ++ .desc = "This event counts every cycle counted by STALL_FRONTEND when no instructions are delivered from the memory system.", ++ }, ++ { ++ .name = "STALL_FRONTEND_L1I", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8159, ++ .desc = "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the first level of instruction cache.", ++ }, ++ { ++ .name = "STALL_FRONTEND_L2I", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x815a, ++ .desc = "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the second level of instruction cache.", ++ }, ++ { ++ .name = "STALL_FRONTEND_MEM", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x815b, ++ .desc = "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the last level of instruction cache within the PE clock domain or a non-cacheable instruction fetch in progress.", ++ }, ++ { ++ .name = "STALL_FRONTEND_TLB", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x815c, ++ .desc = "This event counts every cycle counted by STALL_FRONTEND_MEMBOUND when there is a demand instruction miss in the instruction TLB.", ++ }, ++ { ++ .name = "STALL_FRONTEND_CPUBOUND", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8160, ++ .desc = "This event counts every cycle counted by STALL_FRONTEND when the frontend is stalled on a frontend processor resource, not including memory.", ++ }, ++ { ++ .name = "STALL_FRONTEND_FLOW", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8161, ++ .desc = "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when the frontend is stalled on unavailability of prediction flow resources.", ++ }, ++ { ++ .name = "STALL_FRONTEND_FLUSH", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8162, ++ .desc = "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when the frontend is recovering from a pipeline flush.", ++ }, ++ { ++ .name = "STALL_FRONTEND_RENAME", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8163, ++ .desc = "This event counts every cycle counted by STALL_FRONTEND_CPUBOUND when operations are available from the frontend but at least one is not ready to be sent to the backend because no rename register is available.", ++ }, ++ { ++ .name = "STALL_BACKEND_MEMBOUND", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8164, ++ .desc = "This event counts every cycle counted by STALL_BACKEND when the backend is waiting for a memory access to complete.", ++ }, ++ { ++ .name = "STALL_BACKEND_L1D", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8165, ++ .desc = "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L1D cache.", ++ }, ++ { ++ .name = "STALL_BACKEND_L2D", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8166, ++ .desc = "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in L2D cache.", ++ }, ++ { ++ .name = "STALL_BACKEND_TLB", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8167, ++ .desc = "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when there is a demand data miss in the data TLB.", ++ }, ++ { ++ .name = "STALL_BACKEND_ST", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8168, ++ .desc = "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when the backend is stalled waiting for a store.", ++ }, ++ { ++ .name = "STALL_BACKEND_CPUBOUND", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x816a, ++ .desc = "This event counts every cycle counted by STALL_BACKEND when the backend is stalled on a processor resource, not including memory.", ++ }, ++ { ++ .name = "STALL_BACKEND_BUSY", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x816b, ++ .desc = "This event counts every cycle counted by STALL_BACKEND when operations are available from the frontend but the backend is not able to accept an operation because an execution unit is busy.", ++ }, ++ { ++ .name = "STALL_BACKEND_ILOCK", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x816c, ++ .desc = "This event counts every cycle counted by STALL_BACKEND when operations are available from the frontend but at least one is not ready to be sent to the backend because of an input dependency.", ++ }, ++ { ++ .name = "STALL_BACKEND_RENAME", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x816d, ++ .desc = "This event counts every cycle counted by STALL_BACKEND_CPUBOUND when operations are available from the frontend but at least one is not ready to be sent to the backend because no rename register is available.", ++ }, ++ { ++ .name = "STALL_BACKEND_ATOMIC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x816e, ++ .desc = "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when the backend is processing an Atomic operation.", ++ }, ++ { ++ .name = "STALL_BACKEND_MEMCPYSET", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x816f, ++ .desc = "This event counts every cycle counted by STALL_BACKEND_MEMBOUND when the backend is processing a Memory Copy or Set instruction.", ++ }, ++ { ++ .name = "UOP_RETIRED", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8186, ++ .desc = "This event counts micro-operation that would be executed in a Simple sequential execution of the program.", ++ }, ++ { ++ .name = "DTLB_WALK_BLOCK", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8188, ++ .desc = "This event counts translation table walk counted by DTLB_WALK where the result of the walk yields a Block.", ++ }, ++ { ++ .name = "ITLB_WALK_BLOCK", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8189, ++ .desc = "This event counts translation table walk counted by ITLB_WALK where the result of the walk yields a Block.", ++ }, ++ { ++ .name = "DTLB_WALK_PAGE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x818a, ++ .desc = "This event counts translation table walk counted by DTLB_WALK where the result of the walk yields a Page.", ++ }, ++ { ++ .name = "ITLB_WALK_PAGE", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x818b, ++ .desc = "This event counts translation table walk counted by ITLB_WALK where the result of the walk yields a Page.", ++ }, ++ { ++ .name = "L1I_CACHE_REFILL_HWPRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x81b8, ++ .desc = "This event counts hardware prefetch counted by L1I_CACHE_HWPRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache.", ++ }, ++ { ++ .name = "L1D_CACHE_REFILL_HWPRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x81bc, ++ .desc = "This event counts hardware prefetch counted by L1D_CACHE_HWPRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_HWPRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x81bd, ++ .desc = "This event counts hardware prefetch counted by L2D_CACHE_HWPRF that causes a refill of the Level 2 cache, or any Level 1 data and instruction cache of this PE, from outside of those caches.", ++ }, ++ { ++ .name = "L1I_CACHE_HIT_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x81c0, ++ .desc = "This event counts demand fetch counted by L1I_CACHE_DM_RD that hits in the Level 1 instruction cache.", ++ }, ++ { ++ .name = "L1D_CACHE_HIT_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x81c4, ++ .desc = "This event counts demand read counted by L1D_CACHE_RD that hits in the Level 1 data cache.", ++ }, ++ { ++ .name = "L2D_CACHE_HIT_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x81c5, ++ .desc = "This event counts demand read counted by L2D_CACHE_RD that hits in the Level 2 data cache.", ++ }, ++ { ++ .name = "L1D_CACHE_HIT_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x81c8, ++ .desc = "This event counts demand write counted by L1D_CACHE_WR that hits in the Level 1 data cache.", ++ }, ++ { ++ .name = "L2D_CACHE_HIT_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x81c9, ++ .desc = "This event counts demand write counted by L2D_CACHE_WR that hits in the Level 2 data cache.", ++ }, ++ { ++ .name = "L1I_CACHE_HIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8200, ++ .desc = "This event counts access counted by L1I_CACHE that hits in the Level 1 instruction cache.", ++ }, ++ { ++ .name = "L1D_CACHE_HIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8204, ++ .desc = "This event counts access counted by L1D_CACHE that hits in the Level 1 data cache.", ++ }, ++ { ++ .name = "L2D_CACHE_HIT", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8205, ++ .desc = "This event counts access counted by L2D_CACHE that hits in the Level 2 data cache.", ++ }, ++ { ++ .name = "L1I_LFB_HIT_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8240, ++ .desc = "This event counts demand access counted by L1I_CACHE_HIT_RD that hits a cache line that is in the process of being loaded into the Level 1 instruction cache.", ++ }, ++ { ++ .name = "L1D_LFB_HIT_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8244, ++ .desc = "This event counts demand access counted by L1D_CACHE_HIT_RD that hits a cache line that is in the process of being loaded into the Level 1 data cache.", ++ }, ++ { ++ .name = "L2D_LFB_HIT_RD", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8245, ++ .desc = "This event counts demand access counted by L2D_CACHE_HIT_RD that hits a recently fetched line in the Level 2 cache.", ++ }, ++ { ++ .name = "L1D_LFB_HIT_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8248, ++ .desc = "This event counts demand access counted by L1D_CACHE_HIT_WR that hits a cache line that is in the process of being loaded into the Level 1 data cache.", ++ }, ++ { ++ .name = "L2D_LFB_HIT_WR", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8249, ++ .desc = "This event counts demand access counted by L2D_CACHE_HIT_WR that hits a recently fetched line in the Level 2 cache.", ++ }, ++ { ++ .name = "L1I_CACHE_PRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8280, ++ .desc = "This event counts fetch counted by either Level 1 instruction hardware prefetch or Level 1 instruction software prefetch.", ++ }, ++ { ++ .name = "L1D_CACHE_PRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8284, ++ .desc = "This event counts fetch counted by either Level 1 data hardware prefetch or Level 1 data software prefetch.", ++ }, ++ { ++ .name = "L2D_CACHE_PRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8285, ++ .desc = "This event counts fetch counted by either Level 2 data hardware prefetch or Level 2 data software prefetch.", ++ }, ++ { ++ .name = "L1I_CACHE_REFILL_PRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8288, ++ .desc = "This event counts hardware prefetch counted by L1I_CACHE_PRF that causes a refill of the Level 1 instruction cache from outside of the Level 1 instruction cache.", ++ }, ++ { ++ .name = "L1D_CACHE_REFILL_PRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x828c, ++ .desc = "This event counts hardware prefetch counted by L1D_CACHE_PRF that causes a refill of the Level 1 data cache from outside of the Level 1 data cache.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_PRF", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x828d, ++ .desc = "This event counts hardware prefetch counted by L2D_CACHE_PRF that causes a refill of the Level 2 data cache from outside of the Level 1 data cache.", ++ }, ++ { ++ .name = "L1D_CACHE_REFILL_PERCYC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8320, ++ .desc = "The counter counts by the number of cache refills counted by L1D_CACHE_REFILL in progress on each Processor cycle.", ++ }, ++ { ++ .name = "L2D_CACHE_REFILL_PERCYC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8321, ++ .desc = "The counter counts by the number of cache refills counted by L2D_CACHE_REFILL in progress on each Processor cycle.", ++ }, ++ { ++ .name = "L1I_CACHE_REFILL_PERCYC", ++ .modmsk = ARMV9_ATTRS, ++ .code = 0x8324, ++ .desc = "The counter counts by the number of cache refills counted by L1I_CACHE_REFILL in progress on each Processor cycle.", ++ }, ++}; +diff --git a/lib/pfmlib_arm_armv9.c b/lib/pfmlib_arm_armv9.c +--- a/lib/pfmlib_arm_armv9.c ++++ b/lib/pfmlib_arm_armv9.c +@@ -34,6 +34,7 @@ + + #include "events/arm_neoverse_n2_events.h" /* Arm Neoverse N2 table */ + #include "events/arm_neoverse_v2_events.h" /* Arm Neoverse V2 table */ ++#include "events/arm_fujitsu_monaka_events.h" /* Fujitsu FUJITSU-MONAKA PMU tables */ + + static int + pfm_arm_detect_n2(void *this) +@@ -69,7 +69,23 @@ pfm_arm_detect_v2(void *this) + return PFM_ERR_NOTSUPP; + } + ++ ++static int ++pfm_arm_detect_monaka(void *this) ++{ ++ int ret; ++ ++ ret = pfm_arm_detect(this); ++ if (ret != PFM_SUCCESS) ++ return PFM_ERR_NOTSUPP; ++ ++ if ((pfm_arm_cfg.implementer == 0x46) && /* Fujitsu */ ++ (pfm_arm_cfg.part == 0x003)) { /* monaka */ ++ return PFM_SUCCESS; ++ } ++ return PFM_ERR_NOTSUPP; ++} + + pfmlib_pmu_t arm_n2_support={ + .desc = "Arm Neoverse N2", + .name = "arm_n2", +@@ -201,3 +218,29 @@ pfmlib_pmu_t arm_v3_support={ + PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), + .get_event_nattrs = pfm_arm_get_event_nattrs, + }; ++ ++/* Fujitsu FUJITSU-MONAKA support */ ++pfmlib_pmu_t arm_fujitsu_monaka_support={ ++ .desc = "Fujitsu FUJITSU-MONAKA", ++ .name = "arm_monaka", ++ .pmu = PFM_PMU_ARM_MONAKA, ++ .pme_count = LIBPFM_ARRAY_SIZE(arm_monaka_pe), ++ .type = PFM_PMU_TYPE_CORE, ++ .supported_plm = ARMV9_PLM, ++ .pe = arm_monaka_pe, ++ ++ .pmu_detect = pfm_arm_detect_monaka, ++ .max_encoding = 1, ++ .num_cntrs = 8, ++ ++ .get_event_encoding[PFM_OS_NONE] = pfm_arm_get_encoding, ++ PFMLIB_ENCODE_PERF(pfm_arm_get_perf_encoding), ++ .get_event_first = pfm_arm_get_event_first, ++ .get_event_next = pfm_arm_get_event_next, ++ .event_is_valid = pfm_arm_event_is_valid, ++ .validate_table = pfm_arm_validate_table, ++ .get_event_info = pfm_arm_get_event_info, ++ .get_event_attr_info = pfm_arm_get_event_attr_info, ++ PFMLIB_VALID_PERF_PATTRS(pfm_arm_perf_validate_pattrs), ++ .get_event_nattrs = pfm_arm_get_event_nattrs, ++}; +diff --git a/lib/pfmlib_common.c b/lib/pfmlib_common.c +index d614b23..8c2a827 100644 +--- a/lib/pfmlib_common.c ++++ b/lib/pfmlib_common.c +@@ -748,6 +748,7 @@ static pfmlib_pmu_t *pfmlib_pmus[]= + &arm_thunderx2_ccpi0_support, + &arm_thunderx2_ccpi1_support, + &arm_fujitsu_a64fx_support, ++ &arm_fujitsu_monaka_support, + &arm_hisilicon_kunpeng_sccl1_ddrc0_support, + &arm_hisilicon_kunpeng_sccl1_ddrc1_support, + &arm_hisilicon_kunpeng_sccl1_ddrc2_support, +diff --git a/lib/pfmlib_priv.h b/lib/pfmlib_priv.h +index 3221805..942ec2b 100644 +--- a/lib/pfmlib_priv.h ++++ b/lib/pfmlib_priv.h +@@ -855,6 +855,7 @@ extern pfmlib_pmu_t arm_thunderx2_ccpi0_support; + extern pfmlib_pmu_t arm_thunderx2_ccpi1_support; + + extern pfmlib_pmu_t arm_fujitsu_a64fx_support; ++extern pfmlib_pmu_t arm_fujitsu_monaka_support; + + extern pfmlib_pmu_t arm_hisilicon_kunpeng_support; + extern pfmlib_pmu_t arm_hisilicon_kunpeng_sccl1_ddrc0_support; +diff --git a/tests/validate_arm64.c b/tests/validate_arm64.c +index 330c18c..624f794 100644 +--- a/tests/validate_arm64.c ++++ b/tests/validate_arm64.c +@@ -222,6 +222,34 @@ static const test_event_t arm64_test_events[]={ + .codes[0] = 0x8000008, + .fstr = "arm_a64fx::INST_RETIRED:k=1:u=1:hv=0", + }, ++ { SRC_LINE, ++ .name = "arm_monaka::CPU_CYCLES", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000011, ++ .fstr = "arm_monaka::CPU_CYCLES:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_monaka::CPU_CYCLES:k", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x88000011, ++ .fstr = "arm_monaka::CPU_CYCLES:k=1:u=0:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_monaka::INST_RETIRED", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000008, ++ .fstr = "arm_monaka::INST_RETIRED:k=1:u=1:hv=0", ++ }, ++ { SRC_LINE, ++ .name = "arm_monaka::_1INST_COMMIT", ++ .ret = PFM_SUCCESS, ++ .count = 1, ++ .codes[0] = 0x8000191, ++ .fstr = "arm_monaka::_1INST_COMMIT:k=1:u=1:hv=0", ++ }, + { SRC_LINE, + .name = "arm_n1::INST_RETIRED", + .ret = PFM_SUCCESS, +-- +2.54.0 + diff --git a/SOURCES/libpfm-python3-setup.patch b/libpfm-python3-setup.patch similarity index 100% rename from SOURCES/libpfm-python3-setup.patch rename to libpfm-python3-setup.patch diff --git a/SPECS/libpfm.spec b/libpfm.spec similarity index 57% rename from SPECS/libpfm.spec rename to libpfm.spec index 6a9b4a6..6053100 100644 --- a/SPECS/libpfm.spec +++ b/libpfm.spec @@ -1,27 +1,32 @@ +# Default to no static libraries +%{!?with_static: %global with_static 1} %bcond_without python %if %{with python} %define python_sitearch %(python3 -c "from distutils.sysconfig import get_python_lib; print (get_python_lib(1))") %define python_prefix %(python3 -c "import sys; print (sys.prefix)") %{?filter_setup: -%filter_provides_in %{python_sitearch}/perfmon/.*\.so$ +%filter_provides_in %{python3_sitearch}/perfmon/.*\.so$ %filter_setup } %endif Name: libpfm Version: 4.13.0 -Release: 4%{?dist} +Release: 11%{?dist}.1 Summary: Library to encode performance events for use by perf tool -Group: System Environment/Libraries License: MIT URL: http://perfmon2.sourceforge.net/ Source0: http://sourceforge.net/projects/perfmon2/files/libpfm4/%{name}-%{version}.tar.gz +Patch1: libpfm-ibm-counters.patch Patch2: libpfm-python3-setup.patch -Patch3: libpfm-initp.patch -Patch4: libpfm-zen4.patch +Patch3: libpfm-gcc14.patch +Patch4: libpfm-monaka.patch +Patch5: libpfm-monaka-v1.1.patch +BuildRequires: make +BuildRequires: gcc %if %{with python} BuildRequires: python3 BuildRequires: python3-devel @@ -36,32 +41,34 @@ kernels performance monitoring interfaces. The current version provides support for the perf_events interface available in upstream Linux kernels since v2.6.31. %package devel +License: MIT Summary: Development library to encode performance events for perf_events based tools -Group: Development/Libraries Requires: %{name}%{?_isa} = %{version}-%{release} %description devel Development library and header files to create performance monitoring applications for the perf_events interface. +%if %{with_static} %package static +License: MIT Summary: Static library to encode performance events for perf_events based tools -Group: Development/Libraries Requires: %{name}%{?_isa} = %{version}-%{release} %description static Static version of the libpfm library for performance monitoring applications for the perf_events interface. +%endif %if %{with python} %package -n python3-libpfm +License: MIT AND LicenseRef-Fedora-UltraPermissive %{?python_provide:%python_provide python3-libpfm} # Remove before F30 Provides: %{name}-python = %{version}-%{release} Provides: %{name}-python%{?_isa} = %{version}-%{release} Obsoletes: %{name}-python < %{version}-%{release} Summary: Python bindings for libpfm and perf_event_open system call -Group: Development/Languages Requires: %{name}%{?_isa} = %{version}-%{release} %description -n python3-libpfm @@ -70,9 +77,16 @@ Python bindings for libpfm4 and perf_event_open system call. %prep %setup -q -%patch2 -p1 -b .python3 -%patch3 -p1 -b .test -%patch4 -p1 -b .zen4 +%patch -P1 -p1 -b .ibm +%patch -P2 -p1 -b .python3 +%patch -P3 -p1 -b .gcc14 +%patch -P4 -p1 -b .monaka +%patch -P5 -p1 -b .monaka-v1.1 + +# to prevent setuptools from installing an .egg, we need to pass --root to setup.py install +# see https://github.com/pypa/setuptools/issues/3143 +# and https://github.com/pypa/pip/issues/11501 +sed -i 's/--prefix=$(DESTDIR)$(PYTHON_PREFIX)/--root=$(DESTDIR) --prefix=$(PYTHON_PREFIX)/' python/Makefile %build %if %{with python} @@ -80,7 +94,7 @@ Python bindings for libpfm4 and perf_event_open system call. %else %global python_config CONFIG_PFMLIB_NOPYTHON=y %endif -make %{python_config} %{?_smp_mflags} \ +%make_build %{python_config} \ OPTIM="%{optflags}" LDFLAGS="%{build_ldflags}" @@ -88,20 +102,24 @@ make %{python_config} %{?_smp_mflags} \ rm -rf $RPM_BUILD_ROOT %if %{with python} -%global python_config CONFIG_PFMLIB_NOPYTHON=n PYTHON_PREFIX=$RPM_BUILD_ROOT/%{python_prefix} +%global python_config CONFIG_PFMLIB_NOPYTHON=n PYTHON_PREFIX=%{python_prefix} %else %global python_config CONFIG_PFMLIB_NOPYTHON=y %endif make \ - PREFIX=$RPM_BUILD_ROOT%{_prefix} \ - LIBDIR=$RPM_BUILD_ROOT%{_libdir} \ + DESTDIR=$RPM_BUILD_ROOT \ + PREFIX=%{_prefix} \ + LIBDIR=%{_libdir} \ %{python_config} \ LDCONFIG=/bin/true \ install -%post -p /sbin/ldconfig -%postun -p /sbin/ldconfig +%if !%{with_static} +rm $RPM_BUILD_ROOT%{_libdir}/lib*.a +%endif + +%ldconfig_scriptlets %files %doc README @@ -112,35 +130,129 @@ make \ %{_mandir}/man3/* %{_libdir}/lib*.so +%if %{with_static} %files static %{_libdir}/lib*.a +%endif %if %{with python} %files -n python3-libpfm -%{python_sitearch}/* +%{python3_sitearch}/perfmon-*.egg-info/ +%{python3_sitearch}/perfmon/ %endif %changelog -* Mon Jun 12 2023 William cohen - 4.13.0-4 -- Identify AMD Bergamo processors. +* Thu May 21 2026 Aaron Merey - 4.13.0-11.1 +- Add libpfm-monaka.patch +- Add libpfm-monaka-v1.1.patch -* Wed May 3 2023 William cohen - 4.13.0-3 -- Rebuild for rhbz #2161146. +* Mon Jan 19 2026 Aaron Merey - 4.13.0-11 +- Add libpfm-ibm-counters.patch -* Fri Apr 14 2023 William Cohen - 4.13.0-1 -- Rebase to libpfm-4.13.0 (RHBZ #2185653) +* Tue Oct 29 2024 Troy Dawson - 4.13.0-10 +- Bump release for October 2024 mass rebuild: + Resolves: RHEL-64018 -* Sun May 8 2022 William Cohen - 4.10.1-5 -- Add AMD Zen 2/3 support (RHBZ #2067218) +* Mon Jun 24 2024 Troy Dawson - 4.13.0-9 +- Bump release for June 2024 mass rebuild -* Thu May 20 2021 William Cohen - 4.10.1-4 -- Add Fujitsu A64FX support (RHBZ #1908126) - -* Wed May 27 2020 William Cohen - 4.10.1-3 -- Add Marvell TunderX2 UNC support. (RHBZ #1726070) +* Mon Jan 29 2024 William Cohen - 4.13.0-8 +- Fix gcc-14 -Werror=calloc-transposed-args compatibility -* Tue Oct 15 2019 William Cohen - 4.10.1-2 -- Add IBM zseries support. (RHBZ #1731019) +* Thu Jan 25 2024 Fedora Release Engineering - 4.13.0-7 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_40_Mass_Rebuild + +* Sun Jan 21 2024 Fedora Release Engineering - 4.13.0-6 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_40_Mass_Rebuild + +* Tue Aug 1 2023 William Cohen - 4.13.0-5 +- migrated to SPDX license + +* Thu Jul 20 2023 Fedora Release Engineering - 4.13.0-4 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_39_Mass_Rebuild + +* Tue Jun 13 2023 Python Maint - 4.13.0-3 +- Rebuilt for Python 3.12 + +* Tue Apr 25 2023 Miro Hrončok - 4.13.0-2 +- Don't install a Python .egg + +* Tue Mar 28 2023 William Cohen - 4.13.0-1 +- Rebase on libpfm-4.13.0. + +* Tue Mar 14 2023 William Cohen - 4.11.0-12 +- Add libpfm upstream patch to allow papi-7.0.1 to build. + +* Thu Jan 19 2023 Fedora Release Engineering - 4.11.0-11 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_38_Mass_Rebuild + +* Thu Jul 21 2022 Fedora Release Engineering - 4.11.0-10 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_37_Mass_Rebuild + +* Tue Jun 21 2022 Python Maint - 4.11.0-9 +- Fix FTBFS due to gcc12. (rhbz2045823) + +* Mon Jun 13 2022 Python Maint - 4.11.0-8 +- Rebuilt for Python 3.11 + +* Thu Jan 20 2022 Fedora Release Engineering - 4.11.0-7 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_36_Mass_Rebuild + +* Thu Jul 22 2021 Fedora Release Engineering - 4.11.0-6 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_35_Mass_Rebuild + +* Fri Jun 04 2021 Python Maint - 4.11.0-5 +- Rebuilt for Python 3.10 + +* Tue Jan 26 2021 Fedora Release Engineering - 4.11.0-4 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_34_Mass_Rebuild + +* Sat Jan 23 2021 William Cohen - 4.11.0-3 +- Reenable generation of static libraries for time being. + +* Fri Jan 22 2021 William Cohen - 4.11.0-2 +- By default disable generation of static libraries + +* Tue Sep 08 2020 William Cohen - 4.11.0-1 +- Rebase on libpfm-4.11.0. + +* Tue Jul 28 2020 Fedora Release Engineering - 4.10.1-13 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_33_Mass_Rebuild + +* Mon Jul 13 2020 Tom Stellard - 4.10.1-12 +- Use make macros +- https://fedoraproject.org/wiki/Changes/UseMakeBuildInstallMacro + +* Tue May 26 2020 Miro Hrončok - 4.10.1-11 +- Rebuilt for Python 3.9 + +* Wed Jan 29 2020 Fedora Release Engineering - 4.10.1-10 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_32_Mass_Rebuild + +* Thu Oct 03 2019 Miro Hrončok - 4.10.1-9 +- Rebuilt for Python 3.8.0rc1 (#1748018) + +* Mon Aug 19 2019 Miro Hrončok - 4.10.1-8 +- Rebuilt for Python 3.8 + +* Thu Jul 25 2019 Fedora Release Engineering - 4.10.1-7 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_31_Mass_Rebuild + +* Fri Feb 01 2019 Fedora Release Engineering - 4.10.1-6 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_30_Mass_Rebuild + +* Tue Jul 17 2018 Miro Hrončok - 4.10.1-5 +- Update Python macros to new packaging standards + (See https://fedoraproject.org/wiki/Changes/Move_usr_bin_python_into_separate_package) + +* Sun Jul 15 2018 William Cohen - 4.10.1-4 +- Add gcc Buildrequires. + +* Fri Jul 13 2018 Fedora Release Engineering - 4.10.1-3 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_29_Mass_Rebuild + +* Tue Jun 19 2018 Miro Hrončok - 4.10.1-2 +- Rebuilt for Python 3.7 * Fri Jun 15 2018 William Cohen - 4.10.1-1 - Rebase on libpfm-4.10.1. diff --git a/sources b/sources new file mode 100644 index 0000000..b2d4ea3 --- /dev/null +++ b/sources @@ -0,0 +1 @@ +SHA512 (libpfm-4.13.0.tar.gz) = e61b210aa2ce80f0e47603c88eee2e4f2fe30ca2c0e194a5472b6a8de3bf9dc1085e5261bbb9ddbe5b6531c4b391fb34f20d038e5ebd8e6f4c14c2112aee508f