From 81ecf3ca4cb3dc37a338b57ce6203fe9059645df Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 3 Jul 2013 14:29:07 +1000 Subject: [PATCH] libdrm: update to libdrm 2.4.46 for cursor hotspot --- .gitignore | 1 + 0001-intel-Fix-Haswell-GT3-names.patch | 115 -------------- ...ng-more-reserved-PCI-IDs-for-Haswell.patch | 141 ------------------ libdrm.spec | 13 +- sources | 2 +- 5 files changed, 7 insertions(+), 265 deletions(-) delete mode 100644 0001-intel-Fix-Haswell-GT3-names.patch delete mode 100644 0002-intel-Adding-more-reserved-PCI-IDs-for-Haswell.patch diff --git a/.gitignore b/.gitignore index 33de5be..53397a7 100644 --- a/.gitignore +++ b/.gitignore @@ -28,3 +28,4 @@ libdrm-20100612.tar.bz2 /libdrm-2.4.43.tar.bz2 /libdrm-2.4.44.tar.bz2 /libdrm-2.4.45.tar.bz2 +/libdrm-2.4.46.tar.bz2 diff --git a/0001-intel-Fix-Haswell-GT3-names.patch b/0001-intel-Fix-Haswell-GT3-names.patch deleted file mode 100644 index 29efa30..0000000 --- a/0001-intel-Fix-Haswell-GT3-names.patch +++ /dev/null @@ -1,115 +0,0 @@ -From 150c3555e7ba53f6ad2d3970cca8e4d5970410aa Mon Sep 17 00:00:00 2001 -From: Rodrigo Vivi -Date: Mon, 13 May 2013 17:48:39 -0300 -Subject: [PATCH 1/3] intel: Fix Haswell GT3 names. - -When publishing first HSW ids we weren't allowed to use "GT3" codname. -But this is the correct codname and Mesa is using it already. -So to avoid people getting confused why in Mesa it is called GT3 and here -it is called GT2_PLUS let's fix this name in a standard and correct way. - -Signed-off-by: Rodrigo Vivi -Reviewed-by: Chad Versace -Reviewed-by: Kenneth Graunke ---- - intel/intel_chipset.h | 53 ++++++++++++++++++++++++++------------------------- - 1 file changed, 27 insertions(+), 26 deletions(-) - -diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h -index 5aea3f2..3350def 100644 ---- a/intel/intel_chipset.h -+++ b/intel/intel_chipset.h -@@ -90,40 +90,40 @@ - - #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ - #define PCI_CHIP_HASWELL_GT2 0x0412 --#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 -+#define PCI_CHIP_HASWELL_GT3 0x0422 - #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ - #define PCI_CHIP_HASWELL_M_GT2 0x0416 --#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 -+#define PCI_CHIP_HASWELL_M_GT3 0x0426 - #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ - #define PCI_CHIP_HASWELL_S_GT2 0x041A --#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A -+#define PCI_CHIP_HASWELL_S_GT3 0x042A - #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ - #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 --#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22 -+#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22 - #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ - #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 --#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 -+#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26 - #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ - #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A --#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A -+#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A - #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ - #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 --#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22 -+#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 - #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ - #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 --#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 -+#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 - #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ - #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A --#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A -+#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A - #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ - #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 --#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22 -+#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 - #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ - #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 --#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26 -+#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 - #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ - #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A --#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A -+#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A - - #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */ - #define PCI_CHIP_VALLEYVIEW_1 0x0f31 -@@ -230,22 +230,23 @@ - (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \ -- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \ -- (devid) == PCI_CHIP_HASWELL_GT2_PLUS || \ -- (devid) == PCI_CHIP_HASWELL_M_GT2_PLUS || \ -- (devid) == PCI_CHIP_HASWELL_S_GT2_PLUS || \ -- (devid) == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \ -- (devid) == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \ -- (devid) == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \ -- (devid) == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \ -- (devid) == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \ -- (devid) == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \ -- (devid) == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \ -- (devid) == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \ -- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS) -+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2) -+#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_M_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_S_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT3) - - #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ -- IS_HSW_GT2(devid)) -+ IS_HSW_GT2(devid) || \ -+ IS_HSW_GT3(devid)) - - #define IS_9XX(dev) (IS_GEN3(dev) || \ - IS_GEN4(dev) || \ --- -1.8.2.1 - diff --git a/0002-intel-Adding-more-reserved-PCI-IDs-for-Haswell.patch b/0002-intel-Adding-more-reserved-PCI-IDs-for-Haswell.patch deleted file mode 100644 index 58e6ce1..0000000 --- a/0002-intel-Adding-more-reserved-PCI-IDs-for-Haswell.patch +++ /dev/null @@ -1,141 +0,0 @@ -From 1669a67d063e82a58dae4d906015172d471e9a2a Mon Sep 17 00:00:00 2001 -From: Rodrigo Vivi -Date: Mon, 13 May 2013 17:48:40 -0300 -Subject: [PATCH 2/3] intel: Adding more reserved PCI IDs for Haswell. - -At DDX commit Chris mentioned the tendency we have of finding out more -PCI IDs only when users report. So Let's add all new reserved Haswell IDs. - -Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701 -Signed-off-by: Rodrigo Vivi -Acked-by: Kenneth Graunke ---- - intel/intel_chipset.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++++--- - 1 file changed, 51 insertions(+), 3 deletions(-) - -diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h -index 3350def..aeb439e 100644 ---- a/intel/intel_chipset.h -+++ b/intel/intel_chipset.h -@@ -97,6 +97,12 @@ - #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ - #define PCI_CHIP_HASWELL_S_GT2 0x041A - #define PCI_CHIP_HASWELL_S_GT3 0x042A -+#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */ -+#define PCI_CHIP_HASWELL_B_GT2 0x041B -+#define PCI_CHIP_HASWELL_B_GT3 0x042B -+#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */ -+#define PCI_CHIP_HASWELL_E_GT2 0x041E -+#define PCI_CHIP_HASWELL_E_GT3 0x042E - #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ - #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 - #define PCI_CHIP_HASWELL_SDV_GT3 0x0C22 -@@ -106,6 +112,12 @@ - #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ - #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A - #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A -+#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */ -+#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B -+#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B -+#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */ -+#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E -+#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E - #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ - #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 - #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 -@@ -115,6 +127,12 @@ - #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ - #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A - #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A -+#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */ -+#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B -+#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B -+#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */ -+#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E -+#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E - #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ - #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 - #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 -@@ -124,6 +142,12 @@ - #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ - #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A - #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A -+#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */ -+#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B -+#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B -+#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */ -+#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E -+#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E - - #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */ - #define PCI_CHIP_VALLEYVIEW_1 0x0f31 -@@ -210,39 +234,63 @@ - #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ - (devid) == PCI_CHIP_HASWELL_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_S_GT1 || \ -+ (devid) == PCI_CHIP_HASWELL_B_GT1 || \ -+ (devid) == PCI_CHIP_HASWELL_E_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \ -+ (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \ -+ (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \ - (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \ -+ (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \ -+ (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \ - (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \ -- (devid) == PCI_CHIP_HASWELL_CRW_S_GT1) -+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \ -+ (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \ -+ (devid) == PCI_CHIP_HASWELL_CRW_E_GT1) - #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \ - (devid) == PCI_CHIP_HASWELL_M_GT2 || \ - (devid) == PCI_CHIP_HASWELL_S_GT2 || \ -+ (devid) == PCI_CHIP_HASWELL_B_GT2 || \ -+ (devid) == PCI_CHIP_HASWELL_E_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \ - (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \ -+ (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \ -+ (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \ - (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \ -+ (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \ -+ (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \ - (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \ -- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2) -+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \ -+ (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \ -+ (devid) == PCI_CHIP_HASWELL_CRW_E_GT2) - #define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \ - (devid) == PCI_CHIP_HASWELL_M_GT3 || \ - (devid) == PCI_CHIP_HASWELL_S_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_B_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_E_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \ - (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \ - (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \ - (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \ -- (devid) == PCI_CHIP_HASWELL_CRW_S_GT3) -+ (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \ -+ (devid) == PCI_CHIP_HASWELL_CRW_E_GT3) - - #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ - IS_HSW_GT2(devid) || \ --- -1.8.2.1 - diff --git a/libdrm.spec b/libdrm.spec index 631f97f..abd5b49 100644 --- a/libdrm.spec +++ b/libdrm.spec @@ -2,8 +2,8 @@ Summary: Direct Rendering Manager runtime library Name: libdrm -Version: 2.4.45 -Release: 2%{?dist} +Version: 2.4.46 +Release: 1%{?dist} License: MIT Group: System Environment/Libraries URL: http://dri.sourceforge.net @@ -30,10 +30,6 @@ BuildRequires: libxslt docbook-style-xsl Source2: 91-drm-modeset.rules -# from git -Patch1: 0001-intel-Fix-Haswell-GT3-names.patch -Patch2: 0002-intel-Adding-more-reserved-PCI-IDs-for-Haswell.patch - # hardcode the 666 instead of 660 for device nodes Patch3: libdrm-make-dri-perms-okay.patch # remove backwards compat not needed on Fedora @@ -63,8 +59,6 @@ Utility programs for the kernel DRM interface. Will void your warranty. %prep %setup -q %{?gitdate:-n %{name}-%{gitdate}} -%patch1 -p1 -%patch2 -p1 %patch3 -p1 -b .forceperms %patch4 -p1 -b .no-bc %patch5 -p1 -b .check @@ -209,6 +203,9 @@ done %{_mandir}/man7/drm*.7* %changelog +* Wed Jul 03 2013 Dave Airlie 2.4.46-1 +- libdrm 2.4.46 + * Tue Jun 18 2013 Adam Jackson 2.4.45-2 - Sync some Haswell updates from git diff --git a/sources b/sources index 4ce37be..5073ef9 100644 --- a/sources +++ b/sources @@ -1 +1 @@ -92ce56e7533a9b2fcb5c8f32d305328b libdrm-2.4.45.tar.bz2 +9cba217fd3daa10b1d052ec60d3aa7d5 libdrm-2.4.46.tar.bz2