- libdrm: update to upstream master + add radeon patches from
modesetting-gem
This commit is contained in:
parent
60ceb777bc
commit
35753497c3
@ -1 +1 @@
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libdrm-20080930.tar.bz2
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libdrm-2.4.3.tar.bz2
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@ -1,44 +0,0 @@
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From af2323b4b3b76070fb453531147a8956161b3718 Mon Sep 17 00:00:00 2001
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From: Jesse Barnes <jbarnes@virtuousgeek.org>
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Date: Tue, 30 Sep 2008 16:35:26 -0700
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Subject: [PATCH] intel bufmgr: reinstate buffer handle tracking
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We need a way of getting at the underlying handle for use with mode
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setting. We can either export it in the dri_bo object or provide a new
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callback to get it.
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---
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libdrm/intel/intel_bufmgr.h | 4 ++++
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libdrm/intel/intel_bufmgr_gem.c | 2 +-
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2 files changed, 5 insertions(+), 1 deletions(-)
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diff --git a/libdrm/intel/intel_bufmgr.h b/libdrm/intel/intel_bufmgr.h
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index c44d596..67dba6a 100644
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--- a/libdrm/intel/intel_bufmgr.h
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+++ b/libdrm/intel/intel_bufmgr.h
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@@ -59,6 +59,10 @@ struct _dri_bo {
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/** Buffer manager context associated with this buffer object */
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dri_bufmgr *bufmgr;
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+ /**
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+ * MM-specific handle for accessing object
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+ */
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+ int handle;
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};
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dri_bo *dri_bo_alloc(dri_bufmgr *bufmgr, const char *name, unsigned long size,
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diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c
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index 4ca49d0..70cdca7 100644
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--- a/libdrm/intel/intel_bufmgr_gem.c
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+++ b/libdrm/intel/intel_bufmgr_gem.c
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@@ -316,7 +316,7 @@ dri_gem_bo_alloc(dri_bufmgr *bufmgr, const char *name,
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ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CREATE, &create);
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bo_gem->gem_handle = create.handle;
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- //bo_gem->bo.handle = bo_gem->gem_handle;
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+ bo_gem->bo.handle = bo_gem->gem_handle;
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if (ret != 0) {
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free(bo_gem);
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return NULL;
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--
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1.5.5.1
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@ -1,11 +0,0 @@
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diff -up libdrm-20080930/libdrm/Makefile.am.fixlink libdrm-20080930/libdrm/Makefile.am
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--- libdrm-20080930/libdrm/Makefile.am.fixlink 2008-10-01 11:18:36.000000000 +1000
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+++ libdrm-20080930/libdrm/Makefile.am 2008-10-01 11:18:44.000000000 +1000
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@@ -27,7 +27,6 @@ libdrm_la_LDFLAGS = -version-number 2:3:
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AM_CFLAGS = -I$(top_srcdir)/shared-core
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libdrm_la_SOURCES = xf86drm.c xf86drmHash.c xf86drmRandom.c xf86drmSL.c \
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xf86drmMode.c
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-libdrm_la_LIBADD = intel/libdrm_intel.la
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libdrmincludedir = ${includedir}
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libdrminclude_HEADERS = xf86drm.h xf86drmMode.h
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@ -1,252 +0,0 @@
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diff -up libdrm-20080930/libdrm/intel/intel_bufmgr_gem.c.gttmap libdrm-20080930/libdrm/intel/intel_bufmgr_gem.c
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--- libdrm-20080930/libdrm/intel/intel_bufmgr_gem.c.gttmap 2008-09-30 14:17:27.000000000 +1000
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+++ libdrm-20080930/libdrm/intel/intel_bufmgr_gem.c 2008-09-30 17:35:51.000000000 +1000
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@@ -39,6 +39,7 @@
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#endif
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#include <xf86drm.h>
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+#include <fcntl.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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@@ -46,6 +47,8 @@
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#include <assert.h>
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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+#include <sys/stat.h>
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+#include <sys/types.h>
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#include "errno.h"
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#include "intel_bufmgr.h"
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@@ -518,6 +521,90 @@ dri_gem_bo_map(dri_bo *bo, int write_ena
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return 0;
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}
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+int
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+dri_gem_bo_map_gtt(dri_bo *bo)
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+{
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+ dri_bufmgr_gem *bufmgr_gem;
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+ dri_bo_gem *bo_gem = (dri_bo_gem *)bo;
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+ struct drm_i915_gem_set_domain set_domain;
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+ int ret;
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+ int fd;
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+
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+ bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
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+
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+ /* Allow recursive mapping. Mesa may recursively map buffers with
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+ * nested display loops.
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+ */
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+ if (!bo_gem->mapped) {
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+
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+ assert(bo->virtual == NULL);
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+
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+ DBG("bo_map_gtt: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
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+
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+ if (bo_gem->virtual == NULL) {
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+ struct drm_i915_gem_mmap_gtt mmap_arg;
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+
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+ memset(&mmap_arg, 0, sizeof(mmap_arg));
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+ mmap_arg.handle = bo_gem->gem_handle;
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+ mmap_arg.offset = 0;
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+ mmap_arg.size = bo->size;
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+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MMAP_GTT,
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+ &mmap_arg);
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+ if (ret != 0) {
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+ fprintf(stderr,
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+ "%s:%d: Error mapping buffer %d (%s): %s .\n",
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+ __FILE__, __LINE__,
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+ bo_gem->gem_handle, bo_gem->name,
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+ strerror(errno));
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+ return ret;
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+ }
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+ bo_gem->virtual = (void *)(uintptr_t)mmap_arg.addr_ptr;
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+ }
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+#if 0
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+ if (bo_gem->virtual == NULL) {
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+ fd = open("/sys/devices/pci0000:00/0000:00:02.0/resource2_wc",
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+ O_RDWR);
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+ if (fd == -1) {
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+ fprintf(stderr, "failed to open GTT: %s\n",
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+ strerror(errno));
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+ return errno;
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+ }
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+
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+ bo_gem->virtual = mmap(NULL, bo->size, PROT_READ | PROT_WRITE,
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+ MAP_SHARED, fd, bo->offset);
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+ if (bo_gem->virtual == MAP_FAILED) {
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+ fprintf(stderr, "failed to map GTT: %s\n",
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+ strerror(errno));
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+ return errno;
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+ }
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+ close(fd);
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+ }
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+#endif
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+ bo->virtual = bo_gem->virtual;
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+ bo_gem->swrast = 0;
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+ bo_gem->mapped = 1;
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+ DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
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+ bo_gem->virtual);
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+ }
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+
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+ if (!bo_gem->swrast) {
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+ set_domain.handle = bo_gem->gem_handle;
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+ set_domain.read_domains = I915_GEM_DOMAIN_GTT;
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+ set_domain.write_domain = I915_GEM_DOMAIN_GTT;
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+ do {
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+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
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+ &set_domain);
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+ } while (ret == -1 && errno == EINTR);
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+ if (ret != 0) {
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+ fprintf (stderr, "%s:%d: Error setting swrast %d: %s\n",
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+ __FILE__, __LINE__, bo_gem->gem_handle, strerror (errno));
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+ }
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+ bo_gem->swrast = 1;
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+ }
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+
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+ return 0;
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+}
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+
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static int
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dri_gem_bo_unmap(dri_bo *bo)
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{
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@@ -594,7 +681,7 @@ dri_gem_bo_get_subdata (dri_bo *bo, unsi
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return 0;
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}
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-static void
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+void
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dri_gem_bo_wait_rendering(dri_bo *bo)
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{
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dri_bufmgr_gem *bufmgr_gem = (dri_bufmgr_gem *)bo->bufmgr;
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diff -up libdrm-20080930/libdrm/intel/intel_bufmgr.h.gttmap libdrm-20080930/libdrm/intel/intel_bufmgr.h
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--- libdrm-20080930/libdrm/intel/intel_bufmgr.h.gttmap 2008-09-30 14:17:27.000000000 +1000
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+++ libdrm-20080930/libdrm/intel/intel_bufmgr.h 2008-09-30 17:34:10.000000000 +1000
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@@ -89,6 +89,8 @@ int dri_bo_unpin(dri_bo *buf);
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int dri_bo_set_tiling(dri_bo *buf, uint32_t *tiling_mode);
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int dri_bo_flink(dri_bo *buf, uint32_t *name);
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+int dri_gem_bo_map_gtt(dri_bo *bo);
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+
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/* intel_bufmgr_gem.c */
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dri_bufmgr *intel_bufmgr_gem_init(int fd, int batch_size);
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dri_bo *intel_bo_gem_create_from_name(dri_bufmgr *bufmgr, const char *name,
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diff -up libdrm-20080930/shared-core/i915_drm.h.gttmap libdrm-20080930/shared-core/i915_drm.h
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--- libdrm-20080930/shared-core/i915_drm.h.gttmap 2008-09-30 14:17:27.000000000 +1000
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+++ libdrm-20080930/shared-core/i915_drm.h 2008-09-30 17:01:13.000000000 +1000
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@@ -99,7 +99,7 @@ typedef struct drm_i915_sarea {
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int tex_size;
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int log_tex_granularity;
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int pitch;
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- int rotation; /* 0, 90, 180 or 270 */
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+ int rotation; /* 0, 90, 180 or 270 */
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int rotated_offset;
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int rotated_size;
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int rotated_pitch;
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@@ -149,8 +149,8 @@ typedef struct drm_i915_sarea {
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/* Flags for perf_boxes
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*/
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#define I915_BOX_RING_EMPTY 0x1
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-#define I915_BOX_FLIP 0x2
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-#define I915_BOX_WAIT 0x4
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+#define I915_BOX_FLIP 0x2
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+#define I915_BOX_WAIT 0x4
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#define I915_BOX_TEXTURE_LOAD 0x8
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#define I915_BOX_LOST_CONTEXT 0x10
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@@ -192,24 +192,25 @@ typedef struct drm_i915_sarea {
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#define DRM_I915_GEM_SW_FINISH 0x20
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#define DRM_I915_GEM_SET_TILING 0x21
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#define DRM_I915_GEM_GET_TILING 0x22
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+#define DRM_I915_GEM_MMAP_GTT 0x23
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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#define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)
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#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
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-#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
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-#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
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-#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
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-#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
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-#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
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-#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
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-#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
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+#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
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+#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
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+#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
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+#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
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+#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
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+#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
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+#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
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#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
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#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
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#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
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-#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
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+#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
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#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
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#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
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@@ -223,6 +224,7 @@ typedef struct drm_i915_sarea {
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#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
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#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
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#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
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+#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
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#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
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#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
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#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
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@@ -276,11 +278,11 @@ typedef struct drm_i915_irq_wait {
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/* Ioctl to query kernel params:
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*/
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-#define I915_PARAM_IRQ_ACTIVE 1
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+#define I915_PARAM_IRQ_ACTIVE 1
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#define I915_PARAM_ALLOW_BATCHBUFFER 2
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-#define I915_PARAM_LAST_DISPATCH 3
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-#define I915_PARAM_CHIPSET_ID 4
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-#define I915_PARAM_HAS_GEM 5
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+#define I915_PARAM_LAST_DISPATCH 3
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+#define I915_PARAM_CHIPSET_ID 4
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+#define I915_PARAM_HAS_GEM 5
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typedef struct drm_i915_getparam {
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int param;
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@@ -289,9 +291,9 @@ typedef struct drm_i915_getparam {
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/* Ioctl to set kernel params:
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*/
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-#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
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-#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
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-#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
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+#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
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+#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
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+#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
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typedef struct drm_i915_setparam {
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int param;
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@@ -460,6 +462,25 @@ struct drm_i915_gem_set_domain {
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uint32_t write_domain;
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};
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+struct drm_i915_gem_mmap_gtt {
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+ /** Handle for the object being mapped. */
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+ uint32_t handle;
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+ uint32_t pad;
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+ /** Offset in the object to map. */
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+ uint64_t offset;
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+ /**
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+ * Length of data to map.
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+ *
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+ * The value will be page-aligned.
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+ */
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+ uint64_t size;
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+ /** Returned pointer the data was mapped at */
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+ uint64_t addr_ptr; /* void *, but pointers are not 32/64 compatible
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+ */
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+ uint32_t flags;
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+};
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+
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+
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struct drm_i915_gem_sw_finish {
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/** Handle for the object */
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uint32_t handle;
|
1527
libdrm-radeon.patch
Normal file
1527
libdrm-radeon.patch
Normal file
File diff suppressed because it is too large
Load Diff
@ -16,6 +16,8 @@ BuildRequires: pkgconfig automake autoconf libtool
|
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BuildRequires: kernel-headers >= 2.6.27-0.317.rc5.git10.fc10
|
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BuildRequires: libxcb-devel
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Source2: 91-drm-modeset.rules
|
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Source3: i915modeset
|
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|
||||
|
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Block a user