- rebase to latest upstream release - drop carried patches
This commit is contained in:
Dave Airlie
parent
0a1c4cefe6
commit
2b8e977086
@ -1 +1 @@
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libdrm-20090820.tar.bz2
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libdrm-2.4.14.tar.bz2
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131
intel-busy.patch
131
intel-busy.patch
@ -1,131 +0,0 @@
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From 8214a65ad1f4ccd4966e0def0d43f0c4289e4bc6 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Thu, 27 Aug 2009 18:32:07 -0700
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Subject: [PATCH] Add drm_intel_bo_busy to query whether mapping a BO would block.
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---
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libdrm/intel/intel_bufmgr.c | 7 +++++++
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libdrm/intel/intel_bufmgr.h | 1 +
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libdrm/intel/intel_bufmgr_gem.c | 28 +++++++++++++++++++---------
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libdrm/intel/intel_bufmgr_priv.h | 8 +++++++-
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4 files changed, 34 insertions(+), 10 deletions(-)
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diff --git a/libdrm/intel/intel_bufmgr.c b/libdrm/intel/intel_bufmgr.c
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index f170e7f..219c761 100644
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--- a/libdrm/intel/intel_bufmgr.c
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+++ b/libdrm/intel/intel_bufmgr.c
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@@ -220,6 +220,13 @@ int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
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return 0;
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}
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+int drm_intel_bo_busy(drm_intel_bo *bo)
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+{
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+ if (bo->bufmgr->bo_busy)
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+ return bo->bufmgr->bo_busy(bo);
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+ return 0;
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+}
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+
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int
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drm_intel_get_pipe_from_crtc_id (drm_intel_bufmgr *bufmgr, int crtc_id)
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{
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diff --git a/libdrm/intel/intel_bufmgr.h b/libdrm/intel/intel_bufmgr.h
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index 758558d..218b759 100644
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--- a/libdrm/intel/intel_bufmgr.h
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+++ b/libdrm/intel/intel_bufmgr.h
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@@ -107,6 +107,7 @@ int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
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int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
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uint32_t *swizzle_mode);
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int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t *name);
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+int drm_intel_bo_busy(drm_intel_bo *bo);
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int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
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diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c
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index 737ceae..baa0ee6 100644
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--- a/libdrm/intel/intel_bufmgr_gem.c
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+++ b/libdrm/intel/intel_bufmgr_gem.c
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@@ -314,6 +314,22 @@ drm_intel_setup_reloc_list(drm_intel_bo *bo)
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return 0;
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}
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+static int
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+drm_intel_gem_bo_busy(drm_intel_bo *bo)
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+{
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+ drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
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+ drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
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+ struct drm_i915_gem_busy busy;
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+ int ret;
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+
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+ memset(&busy, 0, sizeof(busy));
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+ busy.handle = bo_gem->gem_handle;
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+
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+ ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
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+
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+ return (ret == 0 && busy.busy);
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+}
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+
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static drm_intel_bo *
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drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name,
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unsigned long size, unsigned int alignment,
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@@ -344,8 +360,6 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name,
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pthread_mutex_lock(&bufmgr_gem->lock);
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/* Get a buffer out of the cache if available */
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if (bucket != NULL && bucket->num_entries > 0) {
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- struct drm_i915_gem_busy busy;
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-
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if (for_render) {
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/* Allocate new render-target BOs from the tail (MRU)
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* of the list, as it will likely be hot in the GPU cache
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@@ -364,13 +378,8 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name,
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*/
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bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head);
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- memset(&busy, 0, sizeof(busy));
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- busy.handle = bo_gem->gem_handle;
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-
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- ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
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- alloc_from_cache = (ret == 0 && busy.busy == 0);
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-
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- if (alloc_from_cache) {
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+ if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
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+ alloc_from_cache = 1;
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DRMLISTDEL(&bo_gem->head);
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bucket->num_entries--;
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}
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@@ -1491,6 +1500,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
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bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
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bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
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bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
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+ bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
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bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
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bufmgr_gem->bufmgr.debug = 0;
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bufmgr_gem->bufmgr.check_aperture_space = drm_intel_gem_check_aperture_space;
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diff --git a/libdrm/intel/intel_bufmgr_priv.h b/libdrm/intel/intel_bufmgr_priv.h
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index 0098076..af17c12 100644
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--- a/libdrm/intel/intel_bufmgr_priv.h
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+++ b/libdrm/intel/intel_bufmgr_priv.h
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@@ -177,6 +177,12 @@ struct _drm_intel_bufmgr {
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*/
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int (*bo_flink)(drm_intel_bo *bo, uint32_t *name);
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+ /**
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+ * Returns 1 if mapping the buffer for write could cause the process
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+ * to block, due to the object being active in the GPU.
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+ */
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+ int (*bo_busy)(drm_intel_bo *bo);
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+
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int (*check_aperture_space)(drm_intel_bo **bo_array, int count);
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/**
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@@ -200,7 +206,7 @@ struct _drm_intel_bufmgr {
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* \param crtc_id the crtc identifier
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*/
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int (*get_pipe_from_crtc_id)(drm_intel_bufmgr *bufmgr, int crtc_id);
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-
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+
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int debug; /**< Enables verbose debugging printouts */
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};
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--
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1.6.4
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@ -22,14 +22,12 @@ BuildRequires: libudev-devel
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Source2: 91-drm-modeset.rules
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Source2: 91-drm-modeset.rules
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Patch2: radeon-busy.patch
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# hardcode the 666 instead of 660 for device nodes
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# hardcode the 666 instead of 660 for device nodes
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Patch3: libdrm-make-dri-perms-okay.patch
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Patch3: libdrm-make-dri-perms-okay.patch
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# remove backwards compat not needed on Fedora
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# remove backwards compat not needed on Fedora
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Patch4: libdrm-2.4.0-no-bc.patch
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Patch4: libdrm-2.4.0-no-bc.patch
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Patch5: libdrm-page-flip.patch
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Patch5: libdrm-page-flip.patch
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Patch6: intel-busy.patch
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%description
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%description
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@ -1,127 +0,0 @@
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diff --git a/libdrm/radeon/radeon_bo.h b/libdrm/radeon/radeon_bo.h
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index 09ad068..1e2e6c2 100644
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--- a/libdrm/radeon/radeon_bo.h
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+++ b/libdrm/radeon/radeon_bo.h
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@@ -73,6 +73,7 @@ struct radeon_bo_funcs {
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uint32_t pitch);
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int (*bo_get_tiling)(struct radeon_bo *bo, uint32_t *tiling_flags,
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uint32_t *pitch);
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+ int (*bo_is_busy)(struct radeon_bo *bo, uint32_t *domain);
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};
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struct radeon_bo_manager {
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@@ -166,6 +167,15 @@ static inline int _radeon_bo_wait(struct radeon_bo *bo,
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return bo->bom->funcs->bo_wait(bo);
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}
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+static inline int _radeon_bo_is_busy(struct radeon_bo *bo,
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+ uint32_t *domain,
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+ const char *file,
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+ const char *func,
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+ int line)
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+{
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+ return bo->bom->funcs->bo_is_busy(bo, domain);
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+}
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+
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static inline int radeon_bo_set_tiling(struct radeon_bo *bo,
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uint32_t tiling_flags, uint32_t pitch)
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{
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@@ -199,5 +209,7 @@ static inline int radeon_bo_is_static(struct radeon_bo *bo)
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_radeon_bo_debug(bo, opcode, __FILE__, __FUNCTION__, __LINE__)
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#define radeon_bo_wait(bo) \
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_radeon_bo_wait(bo, __FILE__, __func__, __LINE__)
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+#define radeon_bo_is_busy(bo, domain) \
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+ _radeon_bo_is_busy(bo, domain, __FILE__, __func__, __LINE__)
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#endif
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diff --git a/libdrm/radeon/radeon_bo_gem.c b/libdrm/radeon/radeon_bo_gem.c
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index cf59a35..76d80e7 100644
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--- a/libdrm/radeon/radeon_bo_gem.c
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+++ b/libdrm/radeon/radeon_bo_gem.c
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@@ -209,6 +209,21 @@ static int bo_wait(struct radeon_bo *bo)
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return ret;
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}
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+static int bo_is_busy(struct radeon_bo *bo, uint32_t *domain)
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+{
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+ struct drm_radeon_gem_busy args;
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+ int ret;
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+
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+ args.handle = bo->handle;
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+ args.domain = 0;
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+
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+ ret = drmCommandWriteRead(bo->bom->fd, DRM_RADEON_GEM_BUSY,
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+ &args, sizeof(args));
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+
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+ *domain = args.domain;
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+ return ret;
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+}
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+
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static int bo_set_tiling(struct radeon_bo *bo, uint32_t tiling_flags,
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uint32_t pitch)
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{
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@@ -257,6 +272,7 @@ static struct radeon_bo_funcs bo_gem_funcs = {
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NULL,
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bo_set_tiling,
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bo_get_tiling,
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+ bo_is_busy,
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};
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struct radeon_bo_manager *radeon_bo_manager_gem_ctor(int fd)
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diff --git a/shared-core/drm.h b/shared-core/drm.h
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index 42a6c23..d97844f 100644
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--- a/shared-core/drm.h
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+++ b/shared-core/drm.h
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@@ -795,7 +795,6 @@ struct drm_gem_open {
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#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
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#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
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#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, uint32_t)
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-#define DRM_IOCTL_MODE_REPLACEFB DRM_IOWR(0xB0, struct drm_mode_fb_cmd)
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/*@}*/
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diff --git a/shared-core/radeon_drm.h b/shared-core/radeon_drm.h
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index 3745ac5..47f1952 100644
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--- a/shared-core/radeon_drm.h
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+++ b/shared-core/radeon_drm.h
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@@ -505,6 +505,7 @@ typedef struct {
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#define DRM_RADEON_INFO 0x27
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#define DRM_RADEON_GEM_SET_TILING 0x28
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#define DRM_RADEON_GEM_GET_TILING 0x29
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+#define DRM_RADEON_GEM_BUSY 0x2a
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#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
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#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
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@@ -545,6 +546,7 @@ typedef struct {
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#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
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#define DRM_IOCTL_RADEON_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
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#define DRM_IOCTL_RADEON_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
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+#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
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typedef struct drm_radeon_init {
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enum {
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@@ -704,6 +706,7 @@ typedef struct drm_radeon_indirect {
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#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
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#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
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#define RADEON_PARAM_DEVICE_ID 16
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+#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */
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typedef struct drm_radeon_getparam {
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int param;
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@@ -835,7 +838,7 @@ struct drm_radeon_gem_wait_idle {
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struct drm_radeon_gem_busy {
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uint32_t handle;
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- uint32_t busy;
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+ uint32_t domain;
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};
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struct drm_radeon_gem_pread {
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@@ -892,6 +895,7 @@ struct drm_radeon_cs {
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#define RADEON_INFO_DEVICE_ID 0x00
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#define RADEON_INFO_NUM_GB_PIPES 0x01
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+#define RADEON_INFO_NUM_Z_PIPES 0x02
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struct drm_radeon_info {
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uint32_t request;
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