10247 lines
515 KiB
Diff
10247 lines
515 KiB
Diff
|
diff --git a/Makefile.am b/Makefile.am
|
||
|
index 41e5a34..ee3ccc7 100644
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||
|
--- a/Makefile.am
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||
|
+++ b/Makefile.am
|
||
|
@@ -25,6 +25,10 @@ DISTCHECK_CONFIGURE_FLAGS = --enable-nouveau-experimental-api --enable-radeon-ex
|
||
|
pkgconfigdir = @pkgconfigdir@
|
||
|
pkgconfig_DATA = libdrm.pc
|
||
|
|
||
|
+if HAVE_LIBKMS
|
||
|
+LIBKMS_SUBDIR = libkms
|
||
|
+endif
|
||
|
+
|
||
|
if HAVE_INTEL
|
||
|
INTEL_SUBDIR = intel
|
||
|
endif
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||
|
@@ -37,7 +41,7 @@ if HAVE_RADEON
|
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|
RADEON_SUBDIR = radeon
|
||
|
endif
|
||
|
|
||
|
-SUBDIRS = . $(INTEL_SUBDIR) $(NOUVEAU_SUBDIR) $(RADEON_SUBDIR) tests include
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|
+SUBDIRS = . $(LIBKMS_SUBDIR) $(INTEL_SUBDIR) $(NOUVEAU_SUBDIR) $(RADEON_SUBDIR) tests include
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||
|
|
||
|
libdrm_la_LTLIBRARIES = libdrm.la
|
||
|
libdrm_ladir = $(libdir)
|
||
|
diff --git a/configure.ac b/configure.ac
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|
index 81523c3..185579c 100644
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|
--- a/configure.ac
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|
+++ b/configure.ac
|
||
|
@@ -32,6 +32,7 @@ AC_PROG_CC
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||
|
|
||
|
AC_HEADER_STDC
|
||
|
AC_SYS_LARGEFILE
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|
+AC_FUNC_ALLOCA
|
||
|
|
||
|
PKG_CHECK_MODULES(PTHREADSTUBS, pthread-stubs)
|
||
|
AC_SUBST(PTHREADSTUBS_CFLAGS)
|
||
|
@@ -43,20 +44,31 @@ AC_ARG_ENABLE(udev, AS_HELP_STRING([--enable-udev],
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||
|
[Enable support for using udev instead of mknod (default: disabled)]),
|
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|
[UDEV=$enableval], [UDEV=no])
|
||
|
|
||
|
+AC_ARG_ENABLE(libkms,
|
||
|
+ AS_HELP_STRING([--enable-libkms],
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||
|
+ [Enable KMS mm abstraction library (default: disabled)]),
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|
+ [LIBKMS=$enableval], [LIBKMS=no])
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||
|
+
|
||
|
AC_ARG_ENABLE(intel,
|
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|
AS_HELP_STRING([--disable-intel],
|
||
|
[Enable support for intel's KMS API (default: auto)]),
|
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|
[INTEL=$enableval], [INTEL=auto])
|
||
|
|
||
|
+AC_ARG_ENABLE(radeon,
|
||
|
+ AS_HELP_STRING([--disable-radeon],
|
||
|
+ [Enable support for radeon's KMS API (default: enabled)]),
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|
+ [RADEON=$enableval], [RADEON=yes])
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||
|
+
|
||
|
+AC_ARG_ENABLE(vmwgfx-experimental-api,
|
||
|
+ AS_HELP_STRING([--enable-vmwgfx-experimental-api],
|
||
|
+ [Install vmwgfx's experimental kernel API header (default: disabled)]),
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|
+ [VMWGFX=$enableval], [VMWGFX=no])
|
||
|
+
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||
|
AC_ARG_ENABLE(nouveau-experimental-api,
|
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|
AS_HELP_STRING([--enable-nouveau-experimental-api],
|
||
|
[Enable support for nouveau's experimental API (default: disabled)]),
|
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|
[NOUVEAU=$enableval], [NOUVEAU=no])
|
||
|
|
||
|
-AC_ARG_ENABLE(radeon-experimental-api,
|
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|
- AS_HELP_STRING([--enable-radeon-experimental-api],
|
||
|
- [Enable support for radeon's KMS API (default: disabled)]),
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|
- [RADEON=$enableval], [RADEON=no])
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||
|
|
||
|
dnl ===========================================================================
|
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|
dnl check compiler flags
|
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|
@@ -134,6 +146,13 @@ if test "x$UDEV" = xyes; then
|
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|
AC_DEFINE(UDEV, 1, [Have UDEV support])
|
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|
fi
|
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|
|
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|
+AM_CONDITIONAL(HAVE_LIBKMS, [test "x$LIBKMS" = xyes])
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|
+
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|
+AM_CONDITIONAL(HAVE_VMWGFX, [test "x$VMWGFX" = xyes])
|
||
|
+if test "x$VMWGFX" = xyes; then
|
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|
+ AC_DEFINE(HAVE_VMWGFX, 1, [Have vmwgfx kernel headers])
|
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|
+fi
|
||
|
+
|
||
|
AM_CONDITIONAL(HAVE_NOUVEAU, [test "x$NOUVEAU" = xyes])
|
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|
|
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|
AM_CONDITIONAL(HAVE_RADEON, [test "x$RADEON" = xyes])
|
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|
@@ -168,6 +187,12 @@ if test "x$INTEL" != "xno"; then
|
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|
AC_CHECK_HEADER([atomic_ops.h], drm_cv_atomic_primitives="libatomic-ops")
|
||
|
fi
|
||
|
|
||
|
+ # atomic functions defined in <atomic.h> & libc on Solaris
|
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|
+ if test "x$drm_cv_atomic_primitives" = "xnone"; then
|
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|
+ AC_CHECK_FUNC([atomic_cas_uint],
|
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|
+ drm_cv_atomic_primitives="Solaris")
|
||
|
+ fi
|
||
|
+
|
||
|
])
|
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|
if test "x$drm_cv_atomic_primitives" = xIntel; then
|
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|
AC_DEFINE(HAVE_INTEL_ATOMIC_PRIMITIVES, 1,
|
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|
@@ -199,6 +224,8 @@ AC_SUBST(kernel_source)
|
||
|
AC_SUBST(WARN_CFLAGS)
|
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|
AC_OUTPUT([
|
||
|
Makefile
|
||
|
+ libkms/Makefile
|
||
|
+ libkms/libkms.pc
|
||
|
intel/Makefile
|
||
|
intel/libdrm_intel.pc
|
||
|
radeon/Makefile
|
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|
@@ -208,6 +235,7 @@ AC_OUTPUT([
|
||
|
tests/Makefile
|
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|
tests/modeprint/Makefile
|
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|
tests/modetest/Makefile
|
||
|
+ tests/kmstest/Makefile
|
||
|
include/Makefile
|
||
|
include/drm/Makefile
|
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|
libdrm.pc])
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|
@@ -215,7 +243,9 @@ AC_OUTPUT([
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|
echo ""
|
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|
echo "$PACKAGE_STRING will be compiled with:"
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|
echo ""
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|
+echo " libkms $LIBKMS"
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echo " Intel API $INTEL"
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+echo " vmwgfx API $VMWGFX"
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|
echo " Radeon API $RADEON"
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|
echo " Nouveau API $NOUVEAU"
|
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|
echo ""
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|
diff --git a/include/drm/Makefile.am b/include/drm/Makefile.am
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|
index 1db5acc..9046955 100644
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|
--- a/include/drm/Makefile.am
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|
+++ b/include/drm/Makefile.am
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|
@@ -36,3 +36,8 @@ klibdrminclude_HEADERS = \
|
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|
sis_drm.h \
|
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|
via_drm.h \
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mach64_drm.h
|
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+
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+
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+if HAVE_VMWGFX
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+klibdrminclude_HEADERS += vmwgfx_drm.h
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+endif
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diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
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index 1e67c44..f745948 100644
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|
--- a/include/drm/nouveau_drm.h
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|
+++ b/include/drm/nouveau_drm.h
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@@ -77,6 +77,7 @@ struct drm_nouveau_gpuobj_free {
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#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
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#define NOUVEAU_GETPARAM_CHIPSET_ID 11
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#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
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+#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
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struct drm_nouveau_getparam {
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uint64_t param;
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uint64_t value;
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diff --git a/include/drm/vmwgfx_drm.h b/include/drm/vmwgfx_drm.h
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|
new file mode 100644
|
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|
index 0000000..2be7e12
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|
--- /dev/null
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|
+++ b/include/drm/vmwgfx_drm.h
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|
@@ -0,0 +1,574 @@
|
||
|
+/**************************************************************************
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||
|
+ *
|
||
|
+ * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
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|
+ * All Rights Reserved.
|
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|
+ *
|
||
|
+ * Permission is hereby granted, free of charge, to any person obtaining a
|
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|
+ * copy of this software and associated documentation files (the
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|
+ * "Software"), to deal in the Software without restriction, including
|
||
|
+ * without limitation the rights to use, copy, modify, merge, publish,
|
||
|
+ * distribute, sub license, and/or sell copies of the Software, and to
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||
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+ * permit persons to whom the Software is furnished to do so, subject to
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+ * the following conditions:
|
||
|
+ *
|
||
|
+ * The above copyright notice and this permission notice (including the
|
||
|
+ * next paragraph) shall be included in all copies or substantial portions
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||
|
+ * of the Software.
|
||
|
+ *
|
||
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||
|
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||
|
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||
|
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||
|
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||
|
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
+ *
|
||
|
+ **************************************************************************/
|
||
|
+
|
||
|
+#ifndef __VMWGFX_DRM_H__
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||
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+#define __VMWGFX_DRM_H__
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|
+
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+#define DRM_VMW_MAX_SURFACE_FACES 6
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|
+#define DRM_VMW_MAX_MIP_LEVELS 24
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+
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+#define DRM_VMW_EXT_NAME_LEN 128
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+
|
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+#define DRM_VMW_GET_PARAM 0
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+#define DRM_VMW_ALLOC_DMABUF 1
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|
+#define DRM_VMW_UNREF_DMABUF 2
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|
+#define DRM_VMW_CURSOR_BYPASS 3
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||
|
+/* guarded by DRM_VMW_PARAM_NUM_STREAMS != 0*/
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||
|
+#define DRM_VMW_CONTROL_STREAM 4
|
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|
+#define DRM_VMW_CLAIM_STREAM 5
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|
+#define DRM_VMW_UNREF_STREAM 6
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+/* guarded by DRM_VMW_PARAM_3D == 1 */
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+#define DRM_VMW_CREATE_CONTEXT 7
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+#define DRM_VMW_UNREF_CONTEXT 8
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+#define DRM_VMW_CREATE_SURFACE 9
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||
|
+#define DRM_VMW_UNREF_SURFACE 10
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+#define DRM_VMW_REF_SURFACE 11
|
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|
+#define DRM_VMW_EXECBUF 12
|
||
|
+#define DRM_VMW_FIFO_DEBUG 13
|
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|
+#define DRM_VMW_FENCE_WAIT 14
|
||
|
+
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_GET_PARAM - get device information.
|
||
|
+ *
|
||
|
+ * DRM_VMW_PARAM_FIFO_OFFSET:
|
||
|
+ * Offset to use to map the first page of the FIFO read-only.
|
||
|
+ * The fifo is mapped using the mmap() system call on the drm device.
|
||
|
+ *
|
||
|
+ * DRM_VMW_PARAM_OVERLAY_IOCTL:
|
||
|
+ * Does the driver support the overlay ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+#define DRM_VMW_PARAM_NUM_STREAMS 0
|
||
|
+#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
|
||
|
+#define DRM_VMW_PARAM_3D 2
|
||
|
+#define DRM_VMW_PARAM_FIFO_OFFSET 3
|
||
|
+
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_getparam_arg
|
||
|
+ *
|
||
|
+ * @value: Returned value. //Out
|
||
|
+ * @param: Parameter to query. //In.
|
||
|
+ *
|
||
|
+ * Argument to the DRM_VMW_GET_PARAM Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_getparam_arg {
|
||
|
+ uint64_t value;
|
||
|
+ uint32_t param;
|
||
|
+ uint32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_EXTENSION - Query device extensions.
|
||
|
+ */
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_extension_rep
|
||
|
+ *
|
||
|
+ * @exists: The queried extension exists.
|
||
|
+ * @driver_ioctl_offset: Ioctl number of the first ioctl in the extension.
|
||
|
+ * @driver_sarea_offset: Offset to any space in the DRI SAREA
|
||
|
+ * used by the extension.
|
||
|
+ * @major: Major version number of the extension.
|
||
|
+ * @minor: Minor version number of the extension.
|
||
|
+ * @pl: Patch level version number of the extension.
|
||
|
+ *
|
||
|
+ * Output argument to the DRM_VMW_EXTENSION Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_extension_rep {
|
||
|
+ int32_t exists;
|
||
|
+ uint32_t driver_ioctl_offset;
|
||
|
+ uint32_t driver_sarea_offset;
|
||
|
+ uint32_t major;
|
||
|
+ uint32_t minor;
|
||
|
+ uint32_t pl;
|
||
|
+ uint32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+/**
|
||
|
+ * union drm_vmw_extension_arg
|
||
|
+ *
|
||
|
+ * @extension - Ascii name of the extension to be queried. //In
|
||
|
+ * @rep - Reply as defined above. //Out
|
||
|
+ *
|
||
|
+ * Argument to the DRM_VMW_EXTENSION Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+union drm_vmw_extension_arg {
|
||
|
+ char extension[DRM_VMW_EXT_NAME_LEN];
|
||
|
+ struct drm_vmw_extension_rep rep;
|
||
|
+};
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_CREATE_CONTEXT - Create a host context.
|
||
|
+ *
|
||
|
+ * Allocates a device unique context id, and queues a create context command
|
||
|
+ * for the host. Does not wait for host completion.
|
||
|
+ */
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_context_arg
|
||
|
+ *
|
||
|
+ * @cid: Device unique context ID.
|
||
|
+ *
|
||
|
+ * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl.
|
||
|
+ * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_context_arg {
|
||
|
+ int32_t cid;
|
||
|
+ uint32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_UNREF_CONTEXT - Create a host context.
|
||
|
+ *
|
||
|
+ * Frees a global context id, and queues a destroy host command for the host.
|
||
|
+ * Does not wait for host completion. The context ID can be used directly
|
||
|
+ * in the command stream and shows up as the same context ID on the host.
|
||
|
+ */
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_CREATE_SURFACE - Create a host suface.
|
||
|
+ *
|
||
|
+ * Allocates a device unique surface id, and queues a create surface command
|
||
|
+ * for the host. Does not wait for host completion. The surface ID can be
|
||
|
+ * used directly in the command stream and shows up as the same surface
|
||
|
+ * ID on the host.
|
||
|
+ */
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_wmv_surface_create_req
|
||
|
+ *
|
||
|
+ * @flags: Surface flags as understood by the host.
|
||
|
+ * @format: Surface format as understood by the host.
|
||
|
+ * @mip_levels: Number of mip levels for each face.
|
||
|
+ * An unused face should have 0 encoded.
|
||
|
+ * @size_addr: Address of a user-space array of sruct drm_vmw_size
|
||
|
+ * cast to an uint64_t for 32-64 bit compatibility.
|
||
|
+ * The size of the array should equal the total number of mipmap levels.
|
||
|
+ * @shareable: Boolean whether other clients (as identified by file descriptors)
|
||
|
+ * may reference this surface.
|
||
|
+ *
|
||
|
+ * Input data to the DRM_VMW_CREATE_SURFACE Ioctl.
|
||
|
+ * Output data from the DRM_VMW_REF_SURFACE Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_surface_create_req {
|
||
|
+ uint32_t flags;
|
||
|
+ uint32_t format;
|
||
|
+ uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES];
|
||
|
+ uint64_t size_addr;
|
||
|
+ int32_t shareable;
|
||
|
+ uint32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_wmv_surface_arg
|
||
|
+ *
|
||
|
+ * @sid: Surface id of created surface or surface to destroy or reference.
|
||
|
+ *
|
||
|
+ * Output data from the DRM_VMW_CREATE_SURFACE Ioctl.
|
||
|
+ * Input argument to the DRM_VMW_UNREF_SURFACE Ioctl.
|
||
|
+ * Input argument to the DRM_VMW_REF_SURFACE Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_surface_arg {
|
||
|
+ int32_t sid;
|
||
|
+ uint32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_size ioctl.
|
||
|
+ *
|
||
|
+ * @width - mip level width
|
||
|
+ * @height - mip level height
|
||
|
+ * @depth - mip level depth
|
||
|
+ *
|
||
|
+ * Description of a mip level.
|
||
|
+ * Input data to the DRM_WMW_CREATE_SURFACE Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_size {
|
||
|
+ uint32_t width;
|
||
|
+ uint32_t height;
|
||
|
+ uint32_t depth;
|
||
|
+ uint32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+/**
|
||
|
+ * union drm_vmw_surface_create_arg
|
||
|
+ *
|
||
|
+ * @rep: Output data as described above.
|
||
|
+ * @req: Input data as described above.
|
||
|
+ *
|
||
|
+ * Argument to the DRM_VMW_CREATE_SURFACE Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+union drm_vmw_surface_create_arg {
|
||
|
+ struct drm_vmw_surface_arg rep;
|
||
|
+ struct drm_vmw_surface_create_req req;
|
||
|
+};
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_REF_SURFACE - Reference a host surface.
|
||
|
+ *
|
||
|
+ * Puts a reference on a host surface with a give sid, as previously
|
||
|
+ * returned by the DRM_VMW_CREATE_SURFACE ioctl.
|
||
|
+ * A reference will make sure the surface isn't destroyed while we hold
|
||
|
+ * it and will allow the calling client to use the surface ID in the command
|
||
|
+ * stream.
|
||
|
+ *
|
||
|
+ * On successful return, the Ioctl returns the surface information given
|
||
|
+ * in the DRM_VMW_CREATE_SURFACE ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+/**
|
||
|
+ * union drm_vmw_surface_reference_arg
|
||
|
+ *
|
||
|
+ * @rep: Output data as described above.
|
||
|
+ * @req: Input data as described above.
|
||
|
+ *
|
||
|
+ * Argument to the DRM_VMW_REF_SURFACE Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+union drm_vmw_surface_reference_arg {
|
||
|
+ struct drm_vmw_surface_create_req rep;
|
||
|
+ struct drm_vmw_surface_arg req;
|
||
|
+};
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_UNREF_SURFACE - Unreference a host surface.
|
||
|
+ *
|
||
|
+ * Clear a reference previously put on a host surface.
|
||
|
+ * When all references are gone, including the one implicitly placed
|
||
|
+ * on creation,
|
||
|
+ * a destroy surface command will be queued for the host.
|
||
|
+ * Does not wait for completion.
|
||
|
+ */
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_EXECBUF
|
||
|
+ *
|
||
|
+ * Submit a command buffer for execution on the host, and return a
|
||
|
+ * fence sequence that when signaled, indicates that the command buffer has
|
||
|
+ * executed.
|
||
|
+ */
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_execbuf_arg
|
||
|
+ *
|
||
|
+ * @commands: User-space address of a command buffer cast to an uint64_t.
|
||
|
+ * @command-size: Size in bytes of the command buffer.
|
||
|
+ * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an
|
||
|
+ * uint64_t.
|
||
|
+ *
|
||
|
+ * Argument to the DRM_VMW_EXECBUF Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_execbuf_arg {
|
||
|
+ uint64_t commands;
|
||
|
+ uint32_t command_size;
|
||
|
+ uint32_t pad64;
|
||
|
+ uint64_t fence_rep;
|
||
|
+};
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_fence_rep
|
||
|
+ *
|
||
|
+ * @fence_seq: Fence sequence associated with a command submission.
|
||
|
+ * @error: This member should've been set to -EFAULT on submission.
|
||
|
+ * The following actions should be take on completion:
|
||
|
+ * error == -EFAULT: Fence communication failed. The host is synchronized.
|
||
|
+ * Use the last fence id read from the FIFO fence register.
|
||
|
+ * error != 0 && error != -EFAULT:
|
||
|
+ * Fence submission failed. The host is synchronized. Use the fence_seq member.
|
||
|
+ * error == 0: All is OK, The host may not be synchronized.
|
||
|
+ * Use the fence_seq member.
|
||
|
+ *
|
||
|
+ * Input / Output data to the DRM_VMW_EXECBUF Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_fence_rep {
|
||
|
+ uint64_t fence_seq;
|
||
|
+ int32_t error;
|
||
|
+ uint32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_ALLOC_DMABUF
|
||
|
+ *
|
||
|
+ * Allocate a DMA buffer that is visible also to the host.
|
||
|
+ * NOTE: The buffer is
|
||
|
+ * identified by a handle and an offset, which are private to the guest, but
|
||
|
+ * useable in the command stream. The guest kernel may translate these
|
||
|
+ * and patch up the command stream accordingly. In the future, the offset may
|
||
|
+ * be zero at all times, or it may disappear from the interface before it is
|
||
|
+ * fixed.
|
||
|
+ *
|
||
|
+ * The DMA buffer may stay user-space mapped in the guest at all times,
|
||
|
+ * and is thus suitable for sub-allocation.
|
||
|
+ *
|
||
|
+ * DMA buffers are mapped using the mmap() syscall on the drm device.
|
||
|
+ */
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_alloc_dmabuf_req
|
||
|
+ *
|
||
|
+ * @size: Required minimum size of the buffer.
|
||
|
+ *
|
||
|
+ * Input data to the DRM_VMW_ALLOC_DMABUF Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_alloc_dmabuf_req {
|
||
|
+ uint32_t size;
|
||
|
+ uint32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_dmabuf_rep
|
||
|
+ *
|
||
|
+ * @map_handle: Offset to use in the mmap() call used to map the buffer.
|
||
|
+ * @handle: Handle unique to this buffer. Used for unreferencing.
|
||
|
+ * @cur_gmr_id: GMR id to use in the command stream when this buffer is
|
||
|
+ * referenced. See not above.
|
||
|
+ * @cur_gmr_offset: Offset to use in the command stream when this buffer is
|
||
|
+ * referenced. See note above.
|
||
|
+ *
|
||
|
+ * Output data from the DRM_VMW_ALLOC_DMABUF Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_dmabuf_rep {
|
||
|
+ uint64_t map_handle;
|
||
|
+ uint32_t handle;
|
||
|
+ uint32_t cur_gmr_id;
|
||
|
+ uint32_t cur_gmr_offset;
|
||
|
+ uint32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+/**
|
||
|
+ * union drm_vmw_dmabuf_arg
|
||
|
+ *
|
||
|
+ * @req: Input data as described above.
|
||
|
+ * @rep: Output data as described above.
|
||
|
+ *
|
||
|
+ * Argument to the DRM_VMW_ALLOC_DMABUF Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+union drm_vmw_alloc_dmabuf_arg {
|
||
|
+ struct drm_vmw_alloc_dmabuf_req req;
|
||
|
+ struct drm_vmw_dmabuf_rep rep;
|
||
|
+};
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_UNREF_DMABUF - Free a DMA buffer.
|
||
|
+ *
|
||
|
+ */
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_unref_dmabuf_arg
|
||
|
+ *
|
||
|
+ * @handle: Handle indicating what buffer to free. Obtained from the
|
||
|
+ * DRM_VMW_ALLOC_DMABUF Ioctl.
|
||
|
+ *
|
||
|
+ * Argument to the DRM_VMW_UNREF_DMABUF Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_unref_dmabuf_arg {
|
||
|
+ uint32_t handle;
|
||
|
+ uint32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_FIFO_DEBUG - Get last FIFO submission.
|
||
|
+ *
|
||
|
+ * This IOCTL copies the last FIFO submission directly out of the FIFO buffer.
|
||
|
+ */
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_fifo_debug_arg
|
||
|
+ *
|
||
|
+ * @debug_buffer: User space address of a debug_buffer cast to an uint64_t //In
|
||
|
+ * @debug_buffer_size: Size in bytes of debug buffer //In
|
||
|
+ * @used_size: Number of bytes copied to the buffer // Out
|
||
|
+ * @did_not_fit: Boolean indicating that the fifo contents did not fit. //Out
|
||
|
+ *
|
||
|
+ * Argument to the DRM_VMW_FIFO_DEBUG Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_fifo_debug_arg {
|
||
|
+ uint64_t debug_buffer;
|
||
|
+ uint32_t debug_buffer_size;
|
||
|
+ uint32_t used_size;
|
||
|
+ int32_t did_not_fit;
|
||
|
+ uint32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+struct drm_vmw_fence_wait_arg {
|
||
|
+ uint64_t sequence;
|
||
|
+ uint64_t kernel_cookie;
|
||
|
+ int32_t cookie_valid;
|
||
|
+ int32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_CONTROL_STREAM - Control overlays, aka streams.
|
||
|
+ *
|
||
|
+ * This IOCTL controls the overlay units of the svga device.
|
||
|
+ * The SVGA overlay units does not work like regular hardware units in
|
||
|
+ * that they do not automaticaly read back the contents of the given dma
|
||
|
+ * buffer. But instead only read back for each call to this ioctl, and
|
||
|
+ * at any point between this call being made and a following call that
|
||
|
+ * either changes the buffer or disables the stream.
|
||
|
+ */
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_rect
|
||
|
+ *
|
||
|
+ * Defines a rectangle. Used in the overlay ioctl to define
|
||
|
+ * source and destination rectangle.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_rect {
|
||
|
+ int32_t x;
|
||
|
+ int32_t y;
|
||
|
+ uint32_t w;
|
||
|
+ uint32_t h;
|
||
|
+};
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_control_stream_arg
|
||
|
+ *
|
||
|
+ * @stream_id: Stearm to control
|
||
|
+ * @enabled: If false all following arguments are ignored.
|
||
|
+ * @handle: Handle to buffer for getting data from.
|
||
|
+ * @format: Format of the overlay as understood by the host.
|
||
|
+ * @width: Width of the overlay.
|
||
|
+ * @height: Height of the overlay.
|
||
|
+ * @size: Size of the overlay in bytes.
|
||
|
+ * @pitch: Array of pitches, the two last are only used for YUV12 formats.
|
||
|
+ * @offset: Offset from start of dma buffer to overlay.
|
||
|
+ * @src: Source rect, must be within the defined area above.
|
||
|
+ * @dst: Destination rect, x and y may be negative.
|
||
|
+ *
|
||
|
+ * Argument to the DRM_VMW_CONTROL_STREAM Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_control_stream_arg {
|
||
|
+ uint32_t stream_id;
|
||
|
+ uint32_t enabled;
|
||
|
+
|
||
|
+ uint32_t flags;
|
||
|
+ uint32_t color_key;
|
||
|
+
|
||
|
+ uint32_t handle;
|
||
|
+ uint32_t offset;
|
||
|
+ int32_t format;
|
||
|
+ uint32_t size;
|
||
|
+ uint32_t width;
|
||
|
+ uint32_t height;
|
||
|
+ uint32_t pitch[3];
|
||
|
+
|
||
|
+ uint32_t pad64;
|
||
|
+ struct drm_vmw_rect src;
|
||
|
+ struct drm_vmw_rect dst;
|
||
|
+};
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_CURSOR_BYPASS - Give extra information about cursor bypass.
|
||
|
+ *
|
||
|
+ */
|
||
|
+
|
||
|
+#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)
|
||
|
+#define DRM_VMW_CURSOR_BYPASS_FLAGS (1)
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_cursor_bypass_arg
|
||
|
+ *
|
||
|
+ * @flags: Flags.
|
||
|
+ * @crtc_id: Crtc id, only used if DMR_CURSOR_BYPASS_ALL isn't passed.
|
||
|
+ * @xpos: X position of cursor.
|
||
|
+ * @ypos: Y position of cursor.
|
||
|
+ * @xhot: X hotspot.
|
||
|
+ * @yhot: Y hotspot.
|
||
|
+ *
|
||
|
+ * Argument to the DRM_VMW_CURSOR_BYPASS Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_cursor_bypass_arg {
|
||
|
+ uint32_t flags;
|
||
|
+ uint32_t crtc_id;
|
||
|
+ int32_t xpos;
|
||
|
+ int32_t ypos;
|
||
|
+ int32_t xhot;
|
||
|
+ int32_t yhot;
|
||
|
+};
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_CLAIM_STREAM - Claim a single stream.
|
||
|
+ */
|
||
|
+
|
||
|
+/**
|
||
|
+ * struct drm_vmw_context_arg
|
||
|
+ *
|
||
|
+ * @stream_id: Device unique context ID.
|
||
|
+ *
|
||
|
+ * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl.
|
||
|
+ * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl.
|
||
|
+ */
|
||
|
+
|
||
|
+struct drm_vmw_stream_arg {
|
||
|
+ uint32_t stream_id;
|
||
|
+ uint32_t pad64;
|
||
|
+};
|
||
|
+
|
||
|
+/*************************************************************************/
|
||
|
+/**
|
||
|
+ * DRM_VMW_UNREF_STREAM - Unclaim a stream.
|
||
|
+ *
|
||
|
+ * Return a single stream that was claimed by this process. Also makes
|
||
|
+ * sure that the stream has been stopped.
|
||
|
+ */
|
||
|
+
|
||
|
+#endif
|
||
|
diff --git a/intel/intel_atomic.h b/intel/intel_atomic.h
|
||
|
index e725c4a..12bb96b 100644
|
||
|
--- a/intel/intel_atomic.h
|
||
|
+++ b/intel/intel_atomic.h
|
||
|
@@ -71,6 +71,21 @@ typedef struct {
|
||
|
|
||
|
#endif
|
||
|
|
||
|
+#if defined(__sun) && !defined(HAS_ATOMIC_OPS) /* Solaris & OpenSolaris */
|
||
|
+
|
||
|
+#include <sys/atomic.h>
|
||
|
+#define HAS_ATOMIC_OPS 1
|
||
|
+
|
||
|
+typedef struct { uint_t atomic; } atomic_t;
|
||
|
+
|
||
|
+# define atomic_read(x) (int) ((x)->atomic)
|
||
|
+# define atomic_set(x, val) ((x)->atomic = (uint_t)(val))
|
||
|
+# define atomic_inc(x) (atomic_inc_uint (&(x)->atomic))
|
||
|
+# define atomic_dec_and_test(x) (atomic_dec_uint_nv(&(x)->atomic) == 1)
|
||
|
+# define atomic_cmpxchg(x, oldv, newv) atomic_cas_uint (&(x)->atomic, oldv, newv)
|
||
|
+
|
||
|
+#endif
|
||
|
+
|
||
|
#if ! HAS_ATOMIC_OPS
|
||
|
#error libdrm-intel requires atomic operations, please define them for your CPU/compiler.
|
||
|
#endif
|
||
|
diff --git a/intel/intel_bufmgr_fake.c b/intel/intel_bufmgr_fake.c
|
||
|
index 54b3cb8..9914952 100644
|
||
|
--- a/intel/intel_bufmgr_fake.c
|
||
|
+++ b/intel/intel_bufmgr_fake.c
|
||
|
@@ -51,6 +51,11 @@
|
||
|
#include "mm.h"
|
||
|
#include "libdrm_lists.h"
|
||
|
|
||
|
+/* Support gcc's __FUNCTION__ for people using other compilers */
|
||
|
+#if !defined(__GNUC__) && !defined(__FUNCTION__)
|
||
|
+# define __FUNCTION__ __func__ /* C99 */
|
||
|
+#endif
|
||
|
+
|
||
|
#define DBG(...) do { \
|
||
|
if (bufmgr_fake->bufmgr.debug) \
|
||
|
drmMsg(__VA_ARGS__); \
|
||
|
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
|
||
|
index f3af3a9..0d011a2 100644
|
||
|
--- a/intel/intel_bufmgr_gem.c
|
||
|
+++ b/intel/intel_bufmgr_gem.c
|
||
|
@@ -1727,6 +1727,9 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
|
||
|
unsigned long size;
|
||
|
|
||
|
bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
|
||
|
+ if (bufmgr_gem == NULL)
|
||
|
+ return NULL;
|
||
|
+
|
||
|
bufmgr_gem->fd = fd;
|
||
|
|
||
|
if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
|
||
|
diff --git a/intel/libdrm_intel.pc.in b/intel/libdrm_intel.pc.in
|
||
|
index ea71cc3..b93f1c6 100644
|
||
|
--- a/intel/libdrm_intel.pc.in
|
||
|
+++ b/intel/libdrm_intel.pc.in
|
||
|
@@ -6,5 +6,6 @@ includedir=@includedir@
|
||
|
Name: libdrm
|
||
|
Description: Userspace interface to kernel DRM services
|
||
|
Version: @PACKAGE_VERSION@
|
||
|
-Libs: -L${libdir} -ldrm -ldrm_intel
|
||
|
+Requires: libdrm
|
||
|
+Libs: -L${libdir} -ldrm_intel
|
||
|
Cflags: -I${includedir} -I${includedir}/drm
|
||
|
diff --git a/libkms/Makefile.am b/libkms/Makefile.am
|
||
|
new file mode 100644
|
||
|
index 0000000..293045c
|
||
|
--- /dev/null
|
||
|
+++ b/libkms/Makefile.am
|
||
|
@@ -0,0 +1,29 @@
|
||
|
+AM_CFLAGS = \
|
||
|
+ $(WARN_CFLAGS) \
|
||
|
+ -I$(top_srcdir)/include/drm
|
||
|
+
|
||
|
+libkms_la_LTLIBRARIES = libkms.la
|
||
|
+libkms_ladir = $(libdir)
|
||
|
+libkms_la_LDFLAGS = -version-number 1:0:0 -no-undefined
|
||
|
+libkms_la_LIBADD =
|
||
|
+
|
||
|
+#if HAVE_LIBUDEV
|
||
|
+#libkms_la_LIBADD += $(LIBUDEV_LIBS)
|
||
|
+#endif
|
||
|
+
|
||
|
+libkms_la_SOURCES = \
|
||
|
+ linux.c \
|
||
|
+ intel.c \
|
||
|
+ api.c
|
||
|
+
|
||
|
+if HAVE_VMWGFX
|
||
|
+libkms_la_SOURCES += vmwgfx.c
|
||
|
+endif
|
||
|
+
|
||
|
+libkmsincludedir = ${includedir}/libkms
|
||
|
+libkmsinclude_HEADERS = libkms.h
|
||
|
+
|
||
|
+pkgconfigdir = @pkgconfigdir@
|
||
|
+pkgconfig_DATA = libkms.pc
|
||
|
+
|
||
|
+EXTRA_DIST = libkms.pc.in
|
||
|
diff --git a/libkms/api.c b/libkms/api.c
|
||
|
new file mode 100644
|
||
|
index 0000000..4a05f3d
|
||
|
--- /dev/null
|
||
|
+++ b/libkms/api.c
|
||
|
@@ -0,0 +1,138 @@
|
||
|
+/**************************************************************************
|
||
|
+ *
|
||
|
+ * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
|
||
|
+ * All Rights Reserved.
|
||
|
+ *
|
||
|
+ * Permission is hereby granted, free of charge, to any person obtaining a
|
||
|
+ * copy of this software and associated documentation files (the
|
||
|
+ * "Software"), to deal in the Software without restriction, including
|
||
|
+ * without limitation the rights to use, copy, modify, merge, publish,
|
||
|
+ * distribute, sub license, and/or sell copies of the Software, and to
|
||
|
+ * permit persons to whom the Software is furnished to do so, subject to
|
||
|
+ * the following conditions:
|
||
|
+ *
|
||
|
+ * The above copyright notice and this permission notice (including the
|
||
|
+ * next paragraph) shall be included in all copies or substantial portions
|
||
|
+ * of the Software.
|
||
|
+ *
|
||
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||
|
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||
|
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||
|
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||
|
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||
|
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
+ *
|
||
|
+ **************************************************************************/
|
||
|
+
|
||
|
+
|
||
|
+#include "config.h"
|
||
|
+#include <errno.h>
|
||
|
+#include <stdlib.h>
|
||
|
+#include <string.h>
|
||
|
+#include "internal.h"
|
||
|
+
|
||
|
+int kms_create(int fd, struct kms_driver **out)
|
||
|
+{
|
||
|
+ return linux_create(fd, out);
|
||
|
+}
|
||
|
+
|
||
|
+int kms_get_prop(struct kms_driver *kms, unsigned key, unsigned *out)
|
||
|
+{
|
||
|
+ switch (key) {
|
||
|
+ case KMS_BO_TYPE:
|
||
|
+ break;
|
||
|
+ default:
|
||
|
+ return -EINVAL;
|
||
|
+ }
|
||
|
+ return kms->get_prop(kms, key, out);
|
||
|
+}
|
||
|
+
|
||
|
+int kms_destroy(struct kms_driver **kms)
|
||
|
+{
|
||
|
+ if (!(*kms))
|
||
|
+ return 0;
|
||
|
+
|
||
|
+ free(*kms);
|
||
|
+ *kms = NULL;
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+int kms_bo_create(struct kms_driver *kms, const unsigned *attr, struct kms_bo **out)
|
||
|
+{
|
||
|
+ unsigned width = 0;
|
||
|
+ unsigned height = 0;
|
||
|
+ enum kms_bo_type type = KMS_BO_TYPE_SCANOUT_X8R8G8B8;
|
||
|
+ int i;
|
||
|
+
|
||
|
+ for (i = 0; attr[i];) {
|
||
|
+ unsigned key = attr[i++];
|
||
|
+ unsigned value = attr[i++];
|
||
|
+
|
||
|
+ switch (key) {
|
||
|
+ case KMS_WIDTH:
|
||
|
+ width = value;
|
||
|
+ break;
|
||
|
+ case KMS_HEIGHT:
|
||
|
+ height = value;
|
||
|
+ break;
|
||
|
+ case KMS_BO_TYPE:
|
||
|
+ type = value;
|
||
|
+ break;
|
||
|
+ default:
|
||
|
+ return EINVAL;
|
||
|
+ }
|
||
|
+ }
|
||
|
+
|
||
|
+ if (width == 0 || height == 0)
|
||
|
+ return -EINVAL;
|
||
|
+
|
||
|
+ /* XXX sanity check type */
|
||
|
+
|
||
|
+ if (type == KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8 &&
|
||
|
+ (width != 64 || height != 64))
|
||
|
+ return -EINVAL;
|
||
|
+
|
||
|
+ return kms->bo_create(kms, width, height, type, attr, out);
|
||
|
+}
|
||
|
+
|
||
|
+int kms_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out)
|
||
|
+{
|
||
|
+ switch (key) {
|
||
|
+ case KMS_PITCH:
|
||
|
+ *out = bo->pitch;
|
||
|
+ break;
|
||
|
+ case KMS_HANDLE:
|
||
|
+ *out = bo->handle;
|
||
|
+ break;
|
||
|
+ default:
|
||
|
+ return -EINVAL;
|
||
|
+ }
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+int kms_bo_map(struct kms_bo *bo, void **out)
|
||
|
+{
|
||
|
+ return bo->kms->bo_map(bo, out);
|
||
|
+}
|
||
|
+
|
||
|
+int kms_bo_unmap(struct kms_bo *bo)
|
||
|
+{
|
||
|
+ return bo->kms->bo_unmap(bo);
|
||
|
+}
|
||
|
+
|
||
|
+int kms_bo_destroy(struct kms_bo **bo)
|
||
|
+{
|
||
|
+ int ret;
|
||
|
+
|
||
|
+ if (!(*bo))
|
||
|
+ return 0;
|
||
|
+
|
||
|
+ ret = (*bo)->kms->bo_destroy(*bo);
|
||
|
+ if (ret)
|
||
|
+ return ret;
|
||
|
+
|
||
|
+ *bo = NULL;
|
||
|
+ return 0;
|
||
|
+}
|
||
|
diff --git a/libkms/intel.c b/libkms/intel.c
|
||
|
new file mode 100644
|
||
|
index 0000000..a1914f8
|
||
|
--- /dev/null
|
||
|
+++ b/libkms/intel.c
|
||
|
@@ -0,0 +1,240 @@
|
||
|
+/**************************************************************************
|
||
|
+ *
|
||
|
+ * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
|
||
|
+ * All Rights Reserved.
|
||
|
+ *
|
||
|
+ * Permission is hereby granted, free of charge, to any person obtaining a
|
||
|
+ * copy of this software and associated documentation files (the
|
||
|
+ * "Software"), to deal in the Software without restriction, including
|
||
|
+ * without limitation the rights to use, copy, modify, merge, publish,
|
||
|
+ * distribute, sub license, and/or sell copies of the Software, and to
|
||
|
+ * permit persons to whom the Software is furnished to do so, subject to
|
||
|
+ * the following conditions:
|
||
|
+ *
|
||
|
+ * The above copyright notice and this permission notice (including the
|
||
|
+ * next paragraph) shall be included in all copies or substantial portions
|
||
|
+ * of the Software.
|
||
|
+ *
|
||
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||
|
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||
|
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||
|
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||
|
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||
|
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
+ *
|
||
|
+ **************************************************************************/
|
||
|
+
|
||
|
+
|
||
|
+#define HAVE_STDINT_H
|
||
|
+#define _FILE_OFFSET_BITS 64
|
||
|
+
|
||
|
+#include <errno.h>
|
||
|
+#include <stdio.h>
|
||
|
+#include <stdlib.h>
|
||
|
+#include <string.h>
|
||
|
+#include "internal.h"
|
||
|
+
|
||
|
+#include <sys/mman.h>
|
||
|
+#include <sys/ioctl.h>
|
||
|
+#include "xf86drm.h"
|
||
|
+
|
||
|
+#include "i915_drm.h"
|
||
|
+
|
||
|
+struct intel_bo
|
||
|
+{
|
||
|
+ struct kms_bo base;
|
||
|
+ unsigned handle;
|
||
|
+ unsigned map_count;
|
||
|
+ int mapped;
|
||
|
+};
|
||
|
+
|
||
|
+static int
|
||
|
+intel_get_prop(struct kms_driver *kms, unsigned key, unsigned *out)
|
||
|
+{
|
||
|
+ switch (key) {
|
||
|
+ case KMS_BO_TYPE:
|
||
|
+ *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8;
|
||
|
+ break;
|
||
|
+ default:
|
||
|
+ return -EINVAL;
|
||
|
+ }
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+intel_destroy(struct kms_driver *kms)
|
||
|
+{
|
||
|
+ free(kms);
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+intel_bo_create(struct kms_driver *kms,
|
||
|
+ const unsigned width, const unsigned height,
|
||
|
+ const enum kms_bo_type type, const unsigned *attr,
|
||
|
+ struct kms_bo **out)
|
||
|
+{
|
||
|
+ struct drm_i915_gem_create arg;
|
||
|
+ unsigned size, pitch;
|
||
|
+ struct intel_bo *bo;
|
||
|
+ int i, ret;
|
||
|
+
|
||
|
+ for (i = 0; attr[i]; i += 2) {
|
||
|
+ switch (attr[i]) {
|
||
|
+ case KMS_WIDTH:
|
||
|
+ case KMS_HEIGHT:
|
||
|
+ case KMS_BO_TYPE:
|
||
|
+ break;
|
||
|
+ default:
|
||
|
+ return -EINVAL;
|
||
|
+ }
|
||
|
+ }
|
||
|
+
|
||
|
+ bo = calloc(1, sizeof(*bo));
|
||
|
+ if (!bo)
|
||
|
+ return -ENOMEM;
|
||
|
+
|
||
|
+ if (type == KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8) {
|
||
|
+ pitch = 64 * 4;
|
||
|
+ size = 64 * 64 * 4;
|
||
|
+ } else if (type == KMS_BO_TYPE_SCANOUT_X8R8G8B8) {
|
||
|
+ pitch = width * 4;
|
||
|
+ pitch = (pitch + 512 - 1) & ~(512 - 1);
|
||
|
+ size = pitch * ((height + 4 - 1) & ~(4 - 1));
|
||
|
+ } else {
|
||
|
+ return -EINVAL;
|
||
|
+ }
|
||
|
+
|
||
|
+ memset(&arg, 0, sizeof(arg));
|
||
|
+ arg.size = size;
|
||
|
+
|
||
|
+ ret = drmCommandWriteRead(kms->fd, DRM_I915_GEM_CREATE, &arg, sizeof(arg));
|
||
|
+ if (ret)
|
||
|
+ goto err_free;
|
||
|
+
|
||
|
+ bo->base.kms = kms;
|
||
|
+ bo->base.handle = arg.handle;
|
||
|
+ bo->base.size = size;
|
||
|
+ bo->base.pitch = pitch;
|
||
|
+
|
||
|
+ *out = &bo->base;
|
||
|
+ if (type == KMS_BO_TYPE_SCANOUT_X8R8G8B8 && pitch > 512) {
|
||
|
+ struct drm_i915_gem_set_tiling tile;
|
||
|
+
|
||
|
+ memset(&tile, 0, sizeof(tile));
|
||
|
+ tile.handle = bo->base.handle;
|
||
|
+ tile.tiling_mode = I915_TILING_X;
|
||
|
+ tile.stride = bo->base.pitch;
|
||
|
+
|
||
|
+ ret = drmCommandWriteRead(kms->fd, DRM_I915_GEM_SET_TILING, &tile, sizeof(tile));
|
||
|
+#if 0
|
||
|
+ if (ret) {
|
||
|
+ kms_bo_destroy(out);
|
||
|
+ return ret;
|
||
|
+ }
|
||
|
+#endif
|
||
|
+ }
|
||
|
+
|
||
|
+ return 0;
|
||
|
+
|
||
|
+err_free:
|
||
|
+ free(bo);
|
||
|
+ return ret;
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+intel_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out)
|
||
|
+{
|
||
|
+ switch (key) {
|
||
|
+ default:
|
||
|
+ return -EINVAL;
|
||
|
+ }
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+intel_bo_map(struct kms_bo *_bo, void **out)
|
||
|
+{
|
||
|
+ struct intel_bo *bo = (struct intel_bo *)_bo;
|
||
|
+ struct drm_i915_gem_mmap_gtt arg;
|
||
|
+ void *map = NULL;
|
||
|
+ int ret;
|
||
|
+
|
||
|
+ if (bo->base.ptr) {
|
||
|
+ bo->map_count++;
|
||
|
+ *out = bo->base.ptr;
|
||
|
+ return 0;
|
||
|
+ }
|
||
|
+
|
||
|
+ memset(&arg, 0, sizeof(arg));
|
||
|
+ arg.handle = bo->base.handle;
|
||
|
+
|
||
|
+ ret = drmCommandWriteRead(bo->base.kms->fd, DRM_I915_GEM_MMAP_GTT, &arg, sizeof(arg));
|
||
|
+ if (ret)
|
||
|
+ return ret;
|
||
|
+
|
||
|
+ map = mmap(0, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->base.kms->fd, arg.offset);
|
||
|
+ if (map == MAP_FAILED)
|
||
|
+ return -errno;
|
||
|
+
|
||
|
+ bo->base.ptr = map;
|
||
|
+ bo->map_count++;
|
||
|
+ *out = bo->base.ptr;
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+intel_bo_unmap(struct kms_bo *_bo)
|
||
|
+{
|
||
|
+ struct intel_bo *bo = (struct intel_bo *)_bo;
|
||
|
+ bo->map_count--;
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+intel_bo_destroy(struct kms_bo *_bo)
|
||
|
+{
|
||
|
+ struct intel_bo *bo = (struct intel_bo *)_bo;
|
||
|
+ struct drm_gem_close arg;
|
||
|
+ int ret;
|
||
|
+
|
||
|
+ if (bo->base.ptr) {
|
||
|
+ /* XXX Sanity check map_count */
|
||
|
+ munmap(bo->base.ptr, bo->base.size);
|
||
|
+ bo->base.ptr = NULL;
|
||
|
+ }
|
||
|
+
|
||
|
+ memset(&arg, 0, sizeof(arg));
|
||
|
+ arg.handle = bo->base.handle;
|
||
|
+
|
||
|
+ ret = drmIoctl(bo->base.kms->fd, DRM_IOCTL_GEM_CLOSE, &arg);
|
||
|
+ if (ret)
|
||
|
+ return -errno;
|
||
|
+
|
||
|
+ free(bo);
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+int
|
||
|
+intel_create(int fd, struct kms_driver **out)
|
||
|
+{
|
||
|
+ struct kms_driver *kms;
|
||
|
+
|
||
|
+ kms = calloc(1, sizeof(*kms));
|
||
|
+ if (!kms)
|
||
|
+ return -ENOMEM;
|
||
|
+
|
||
|
+ kms->fd = fd;
|
||
|
+
|
||
|
+ kms->bo_create = intel_bo_create;
|
||
|
+ kms->bo_map = intel_bo_map;
|
||
|
+ kms->bo_unmap = intel_bo_unmap;
|
||
|
+ kms->bo_get_prop = intel_bo_get_prop;
|
||
|
+ kms->bo_destroy = intel_bo_destroy;
|
||
|
+ kms->get_prop = intel_get_prop;
|
||
|
+ kms->destroy = intel_destroy;
|
||
|
+ *out = kms;
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
diff --git a/libkms/internal.h b/libkms/internal.h
|
||
|
new file mode 100644
|
||
|
index 0000000..9d1c5f7
|
||
|
--- /dev/null
|
||
|
+++ b/libkms/internal.h
|
||
|
@@ -0,0 +1,71 @@
|
||
|
+/**************************************************************************
|
||
|
+ *
|
||
|
+ * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
|
||
|
+ * All Rights Reserved.
|
||
|
+ *
|
||
|
+ * Permission is hereby granted, free of charge, to any person obtaining a
|
||
|
+ * copy of this software and associated documentation files (the
|
||
|
+ * "Software"), to deal in the Software without restriction, including
|
||
|
+ * without limitation the rights to use, copy, modify, merge, publish,
|
||
|
+ * distribute, sub license, and/or sell copies of the Software, and to
|
||
|
+ * permit persons to whom the Software is furnished to do so, subject to
|
||
|
+ * the following conditions:
|
||
|
+ *
|
||
|
+ * The above copyright notice and this permission notice (including the
|
||
|
+ * next paragraph) shall be included in all copies or substantial portions
|
||
|
+ * of the Software.
|
||
|
+ *
|
||
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||
|
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||
|
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||
|
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||
|
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||
|
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
+ *
|
||
|
+ **************************************************************************/
|
||
|
+
|
||
|
+
|
||
|
+#ifndef INTERNAL_H_
|
||
|
+#define INTERNAL_H_
|
||
|
+
|
||
|
+#include "libkms.h"
|
||
|
+
|
||
|
+struct kms_driver
|
||
|
+{
|
||
|
+ int (*get_prop)(struct kms_driver *kms, const unsigned key,
|
||
|
+ unsigned *out);
|
||
|
+ int (*destroy)(struct kms_driver *kms);
|
||
|
+
|
||
|
+ int (*bo_create)(struct kms_driver *kms,
|
||
|
+ unsigned width,
|
||
|
+ unsigned height,
|
||
|
+ enum kms_bo_type type,
|
||
|
+ const unsigned *attr,
|
||
|
+ struct kms_bo **out);
|
||
|
+ int (*bo_get_prop)(struct kms_bo *bo, const unsigned key,
|
||
|
+ unsigned *out);
|
||
|
+ int (*bo_map)(struct kms_bo *bo, void **out);
|
||
|
+ int (*bo_unmap)(struct kms_bo *bo);
|
||
|
+ int (*bo_destroy)(struct kms_bo *bo);
|
||
|
+
|
||
|
+ int fd;
|
||
|
+};
|
||
|
+
|
||
|
+struct kms_bo
|
||
|
+{
|
||
|
+ struct kms_driver *kms;
|
||
|
+ void *ptr;
|
||
|
+ size_t size;
|
||
|
+ size_t offset;
|
||
|
+ size_t pitch;
|
||
|
+ unsigned handle;
|
||
|
+};
|
||
|
+
|
||
|
+int linux_create(int fd, struct kms_driver **out);
|
||
|
+
|
||
|
+int vmwgfx_create(int fd, struct kms_driver **out);
|
||
|
+
|
||
|
+int intel_create(int fd, struct kms_driver **out);
|
||
|
+
|
||
|
+#endif
|
||
|
diff --git a/libkms/libkms.h b/libkms/libkms.h
|
||
|
new file mode 100644
|
||
|
index 0000000..4664442
|
||
|
--- /dev/null
|
||
|
+++ b/libkms/libkms.h
|
||
|
@@ -0,0 +1,74 @@
|
||
|
+/**************************************************************************
|
||
|
+ *
|
||
|
+ * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
|
||
|
+ * All Rights Reserved.
|
||
|
+ *
|
||
|
+ * Permission is hereby granted, free of charge, to any person obtaining a
|
||
|
+ * copy of this software and associated documentation files (the
|
||
|
+ * "Software"), to deal in the Software without restriction, including
|
||
|
+ * without limitation the rights to use, copy, modify, merge, publish,
|
||
|
+ * distribute, sub license, and/or sell copies of the Software, and to
|
||
|
+ * permit persons to whom the Software is furnished to do so, subject to
|
||
|
+ * the following conditions:
|
||
|
+ *
|
||
|
+ * The above copyright notice and this permission notice (including the
|
||
|
+ * next paragraph) shall be included in all copies or substantial portions
|
||
|
+ * of the Software.
|
||
|
+ *
|
||
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||
|
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||
|
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||
|
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||
|
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||
|
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
+ *
|
||
|
+ **************************************************************************/
|
||
|
+
|
||
|
+
|
||
|
+#ifndef _LIBKMS_H_
|
||
|
+#define _LIBKMS_H_
|
||
|
+
|
||
|
+/**
|
||
|
+ * \file
|
||
|
+ *
|
||
|
+ */
|
||
|
+
|
||
|
+struct kms_driver;
|
||
|
+struct kms_bo;
|
||
|
+
|
||
|
+enum kms_attrib
|
||
|
+{
|
||
|
+ KMS_TERMINATE_PROP_LIST,
|
||
|
+#define KMS_TERMINATE_PROP_LIST KMS_TERMINATE_PROP_LIST
|
||
|
+ KMS_BO_TYPE,
|
||
|
+#define KMS_BO_TYPE KMS_BO_TYPE
|
||
|
+ KMS_WIDTH,
|
||
|
+#define KMS_WIDTH KMS_WIDTH
|
||
|
+ KMS_HEIGHT,
|
||
|
+#define KMS_HEIGHT KMS_HEIGHT
|
||
|
+ KMS_PITCH,
|
||
|
+#define KMS_PITCH KMS_PITCH
|
||
|
+ KMS_HANDLE,
|
||
|
+#define KMS_HANDLE KMS_HANDLE
|
||
|
+};
|
||
|
+
|
||
|
+enum kms_bo_type
|
||
|
+{
|
||
|
+ KMS_BO_TYPE_SCANOUT_X8R8G8B8 = (1 << 0),
|
||
|
+#define KMS_BO_TYPE_SCANOUT_X8R8G8B8 KMS_BO_TYPE_SCANOUT_X8R8G8B8
|
||
|
+ KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8 = (1 << 1),
|
||
|
+#define KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8 KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8
|
||
|
+};
|
||
|
+
|
||
|
+int kms_create(int fd, struct kms_driver **out);
|
||
|
+int kms_get_prop(struct kms_driver *kms, unsigned key, unsigned *out);
|
||
|
+int kms_destroy(struct kms_driver **kms);
|
||
|
+
|
||
|
+int kms_bo_create(struct kms_driver *kms, const unsigned *attr, struct kms_bo **out);
|
||
|
+int kms_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out);
|
||
|
+int kms_bo_map(struct kms_bo *bo, void **out);
|
||
|
+int kms_bo_unmap(struct kms_bo *bo);
|
||
|
+int kms_bo_destroy(struct kms_bo **bo);
|
||
|
+
|
||
|
+#endif
|
||
|
diff --git a/libkms/libkms.pc.in b/libkms/libkms.pc.in
|
||
|
new file mode 100644
|
||
|
index 0000000..b3cbbf3
|
||
|
--- /dev/null
|
||
|
+++ b/libkms/libkms.pc.in
|
||
|
@@ -0,0 +1,10 @@
|
||
|
+prefix=@prefix@
|
||
|
+exec_prefix=@exec_prefix@
|
||
|
+libdir=@libdir@
|
||
|
+includedir=@includedir@
|
||
|
+
|
||
|
+Name: libkms
|
||
|
+Description: Library that abstract aways the different mm interface for kernel drivers
|
||
|
+Version: 1.0
|
||
|
+Libs: -L${libdir} -lkms
|
||
|
+Cflags: -I${includedir}/libkms
|
||
|
diff --git a/libkms/linux.c b/libkms/linux.c
|
||
|
new file mode 100644
|
||
|
index 0000000..94e1b52
|
||
|
--- /dev/null
|
||
|
+++ b/libkms/linux.c
|
||
|
@@ -0,0 +1,215 @@
|
||
|
+/**************************************************************************
|
||
|
+ *
|
||
|
+ * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
|
||
|
+ * All Rights Reserved.
|
||
|
+ *
|
||
|
+ * Permission is hereby granted, free of charge, to any person obtaining a
|
||
|
+ * copy of this software and associated documentation files (the
|
||
|
+ * "Software"), to deal in the Software without restriction, including
|
||
|
+ * without limitation the rights to use, copy, modify, merge, publish,
|
||
|
+ * distribute, sub license, and/or sell copies of the Software, and to
|
||
|
+ * permit persons to whom the Software is furnished to do so, subject to
|
||
|
+ * the following conditions:
|
||
|
+ *
|
||
|
+ * The above copyright notice and this permission notice (including the
|
||
|
+ * next paragraph) shall be included in all copies or substantial portions
|
||
|
+ * of the Software.
|
||
|
+ *
|
||
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||
|
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||
|
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||
|
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||
|
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||
|
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
+ *
|
||
|
+ **************************************************************************/
|
||
|
+/*
|
||
|
+ * Thanks to krh and jcristau for the tips on
|
||
|
+ * going from fd to pci id via fstat and udev.
|
||
|
+ */
|
||
|
+
|
||
|
+
|
||
|
+#include "config.h"
|
||
|
+#include <errno.h>
|
||
|
+#include <stdio.h>
|
||
|
+#include <stdlib.h>
|
||
|
+#include <xf86drm.h>
|
||
|
+#include <string.h>
|
||
|
+#include <unistd.h>
|
||
|
+
|
||
|
+#include <sys/stat.h>
|
||
|
+
|
||
|
+#include "internal.h"
|
||
|
+
|
||
|
+#define PATH_SIZE 512
|
||
|
+
|
||
|
+static int
|
||
|
+linux_name_from_sysfs(int fd, char **out)
|
||
|
+{
|
||
|
+ char path[PATH_SIZE+1] = ""; /* initialize to please valgrind */
|
||
|
+ char link[PATH_SIZE+1] = "";
|
||
|
+ struct stat buffer;
|
||
|
+ unsigned maj, min;
|
||
|
+ char* slash_name;
|
||
|
+ int ret;
|
||
|
+
|
||
|
+ /*
|
||
|
+ * Inside the sysfs directory for the device there is a symlink
|
||
|
+ * to the directory representing the driver module, that path
|
||
|
+ * happens to hold the name of the driver.
|
||
|
+ *
|
||
|
+ * So lets get the symlink for the drm device. Then read the link
|
||
|
+ * and filter out the last directory which happens to be the name
|
||
|
+ * of the driver, which we can use to load the correct interface.
|
||
|
+ *
|
||
|
+ * Thanks to Ray Strode of Plymouth for the code.
|
||
|
+ */
|
||
|
+
|
||
|
+ ret = fstat(fd, &buffer);
|
||
|
+ if (ret)
|
||
|
+ return ret;
|
||
|
+
|
||
|
+ if (!S_ISCHR(buffer.st_mode))
|
||
|
+ return -EINVAL;
|
||
|
+
|
||
|
+ maj = major(buffer.st_rdev);
|
||
|
+ min = minor(buffer.st_rdev);
|
||
|
+
|
||
|
+ snprintf(path, PATH_SIZE, "/sys/dev/char/%d:%d/device/driver", maj, min);
|
||
|
+
|
||
|
+ if (readlink(path, link, PATH_SIZE) < 0)
|
||
|
+ return -EINVAL;
|
||
|
+
|
||
|
+ /* link looks something like this: ../../../bus/pci/drivers/intel */
|
||
|
+ slash_name = strrchr(link, '/');
|
||
|
+ if (!slash_name)
|
||
|
+ return -EINVAL;
|
||
|
+
|
||
|
+ /* copy name and at the same time remove the slash */
|
||
|
+ *out = strdup(slash_name + 1);
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+linux_from_sysfs(int fd, struct kms_driver **out)
|
||
|
+{
|
||
|
+ char *name;
|
||
|
+ int ret;
|
||
|
+
|
||
|
+ ret = linux_name_from_sysfs(fd, &name);
|
||
|
+ if (ret)
|
||
|
+ return ret;
|
||
|
+
|
||
|
+ if (!strcmp(name, "intel"))
|
||
|
+ ret = intel_create(fd, out);
|
||
|
+#ifdef HAVE_VMWGFX
|
||
|
+ else if (!strcmp(name, "vmwgfx"))
|
||
|
+ ret = vmwgfx_create(fd, out);
|
||
|
+#endif
|
||
|
+ else
|
||
|
+ ret = -ENOSYS;
|
||
|
+
|
||
|
+ free(name);
|
||
|
+ return ret;
|
||
|
+}
|
||
|
+
|
||
|
+#if 0
|
||
|
+#define LIBUDEV_I_KNOW_THE_API_IS_SUBJECT_TO_CHANGE
|
||
|
+#include <libudev.h>
|
||
|
+
|
||
|
+struct create_record
|
||
|
+{
|
||
|
+ unsigned vendor;
|
||
|
+ unsigned chip;
|
||
|
+ int (*func)(int fd, struct kms_driver **out);
|
||
|
+};
|
||
|
+
|
||
|
+static struct create_record table[] = {
|
||
|
+ { 0x8086, 0x2a42, intel_create }, /* i965 */
|
||
|
+#ifdef HAVE_VMWGFX
|
||
|
+ { 0x15ad, 0x0405, vmwgfx_create }, /* VMware vGPU */
|
||
|
+#endif
|
||
|
+ { 0, 0, NULL },
|
||
|
+};
|
||
|
+
|
||
|
+static int
|
||
|
+linux_get_pciid_from_fd(int fd, unsigned *vendor_id, unsigned *chip_id)
|
||
|
+{
|
||
|
+ struct udev *udev;
|
||
|
+ struct udev_device *device;
|
||
|
+ struct udev_device *parent;
|
||
|
+ const char *pci_id;
|
||
|
+ struct stat buffer;
|
||
|
+ int ret;
|
||
|
+
|
||
|
+ ret = fstat(fd, &buffer);
|
||
|
+ if (ret)
|
||
|
+ return -EINVAL;
|
||
|
+
|
||
|
+ if (!S_ISCHR(buffer.st_mode))
|
||
|
+ return -EINVAL;
|
||
|
+
|
||
|
+ udev = udev_new();
|
||
|
+ if (!udev)
|
||
|
+ return -ENOMEM;
|
||
|
+
|
||
|
+ device = udev_device_new_from_devnum(udev, 'c', buffer.st_rdev);
|
||
|
+ if (!device)
|
||
|
+ goto err_free_udev;
|
||
|
+
|
||
|
+ parent = udev_device_get_parent(device);
|
||
|
+ if (!parent)
|
||
|
+ goto err_free_device;
|
||
|
+
|
||
|
+ pci_id = udev_device_get_property_value(parent, "PCI_ID");
|
||
|
+ if (!pci_id)
|
||
|
+ goto err_free_device;
|
||
|
+
|
||
|
+ if (sscanf(pci_id, "%x:%x", vendor_id, chip_id) != 2)
|
||
|
+ goto err_free_device;
|
||
|
+
|
||
|
+ udev_device_unref(device);
|
||
|
+ udev_unref(udev);
|
||
|
+
|
||
|
+ return 0;
|
||
|
+
|
||
|
+err_free_device:
|
||
|
+ udev_device_unref(device);
|
||
|
+err_free_udev:
|
||
|
+ udev_unref(udev);
|
||
|
+ return -EINVAL;
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+linux_from_udev(int fd, struct kms_driver **out)
|
||
|
+{
|
||
|
+ unsigned vendor_id, chip_id;
|
||
|
+ int ret, i;
|
||
|
+
|
||
|
+ ret = linux_get_pciid_from_fd(fd, &vendor_id, &chip_id);
|
||
|
+ if (ret)
|
||
|
+ return ret;
|
||
|
+
|
||
|
+ for (i = 0; table[i].func; i++)
|
||
|
+ if (table[i].vendor == vendor_id && table[i].chip == chip_id)
|
||
|
+ return table[i].func(fd, out);
|
||
|
+
|
||
|
+ return -ENOSYS;
|
||
|
+}
|
||
|
+#else
|
||
|
+static int
|
||
|
+linux_from_udev(int fd, struct kms_driver **out)
|
||
|
+{
|
||
|
+ return -ENOSYS;
|
||
|
+}
|
||
|
+#endif
|
||
|
+
|
||
|
+int
|
||
|
+linux_create(int fd, struct kms_driver **out)
|
||
|
+{
|
||
|
+ if (!linux_from_udev(fd, out))
|
||
|
+ return 0;
|
||
|
+
|
||
|
+ return linux_from_sysfs(fd, out);
|
||
|
+}
|
||
|
diff --git a/libkms/vmwgfx.c b/libkms/vmwgfx.c
|
||
|
new file mode 100644
|
||
|
index 0000000..d594b3b
|
||
|
--- /dev/null
|
||
|
+++ b/libkms/vmwgfx.c
|
||
|
@@ -0,0 +1,207 @@
|
||
|
+/**************************************************************************
|
||
|
+ *
|
||
|
+ * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
|
||
|
+ * All Rights Reserved.
|
||
|
+ *
|
||
|
+ * Permission is hereby granted, free of charge, to any person obtaining a
|
||
|
+ * copy of this software and associated documentation files (the
|
||
|
+ * "Software"), to deal in the Software without restriction, including
|
||
|
+ * without limitation the rights to use, copy, modify, merge, publish,
|
||
|
+ * distribute, sub license, and/or sell copies of the Software, and to
|
||
|
+ * permit persons to whom the Software is furnished to do so, subject to
|
||
|
+ * the following conditions:
|
||
|
+ *
|
||
|
+ * The above copyright notice and this permission notice (including the
|
||
|
+ * next paragraph) shall be included in all copies or substantial portions
|
||
|
+ * of the Software.
|
||
|
+ *
|
||
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||
|
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||
|
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||
|
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||
|
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||
|
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
+ *
|
||
|
+ **************************************************************************/
|
||
|
+
|
||
|
+
|
||
|
+#define HAVE_STDINT_H
|
||
|
+#define _FILE_OFFSET_BITS 64
|
||
|
+
|
||
|
+#include <errno.h>
|
||
|
+#include <stdlib.h>
|
||
|
+#include <string.h>
|
||
|
+#include "internal.h"
|
||
|
+
|
||
|
+#include <sys/mman.h>
|
||
|
+#include "xf86drm.h"
|
||
|
+#include "vmwgfx_drm.h"
|
||
|
+
|
||
|
+struct vmwgfx_bo
|
||
|
+{
|
||
|
+ struct kms_bo base;
|
||
|
+ uint64_t map_handle;
|
||
|
+ unsigned map_count;
|
||
|
+};
|
||
|
+
|
||
|
+static int
|
||
|
+vmwgfx_get_prop(struct kms_driver *kms, unsigned key, unsigned *out)
|
||
|
+{
|
||
|
+ switch (key) {
|
||
|
+ case KMS_BO_TYPE:
|
||
|
+ *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8;
|
||
|
+ break;
|
||
|
+ default:
|
||
|
+ return -EINVAL;
|
||
|
+ }
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+vmwgfx_destroy(struct kms_driver *kms)
|
||
|
+{
|
||
|
+ free(kms);
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+vmwgfx_bo_create(struct kms_driver *kms,
|
||
|
+ const unsigned width, const unsigned height,
|
||
|
+ const enum kms_bo_type type, const unsigned *attr,
|
||
|
+ struct kms_bo **out)
|
||
|
+{
|
||
|
+ struct vmwgfx_bo *bo;
|
||
|
+ int i, ret;
|
||
|
+
|
||
|
+ for (i = 0; attr[i]; i += 2) {
|
||
|
+ switch (attr[i]) {
|
||
|
+ case KMS_WIDTH:
|
||
|
+ case KMS_HEIGHT:
|
||
|
+ case KMS_BO_TYPE:
|
||
|
+ break;
|
||
|
+ default:
|
||
|
+ return -EINVAL;
|
||
|
+ }
|
||
|
+ }
|
||
|
+
|
||
|
+ bo = calloc(1, sizeof(*bo));
|
||
|
+ if (!bo)
|
||
|
+ return -EINVAL;
|
||
|
+
|
||
|
+ {
|
||
|
+ union drm_vmw_alloc_dmabuf_arg arg;
|
||
|
+ struct drm_vmw_alloc_dmabuf_req *req = &arg.req;
|
||
|
+ struct drm_vmw_dmabuf_rep *rep = &arg.rep;
|
||
|
+
|
||
|
+ memset(&arg, 0, sizeof(arg));
|
||
|
+ req->size = width * height * 4;
|
||
|
+ bo->base.size = req->size;
|
||
|
+ bo->base.pitch = width * 4;
|
||
|
+ bo->base.kms = kms;
|
||
|
+
|
||
|
+ do {
|
||
|
+ ret = drmCommandWriteRead(bo->base.kms->fd,
|
||
|
+ DRM_VMW_ALLOC_DMABUF,
|
||
|
+ &arg, sizeof(arg));
|
||
|
+ } while (ret == -ERESTART);
|
||
|
+
|
||
|
+ if (ret)
|
||
|
+ goto err_free;
|
||
|
+
|
||
|
+ bo->base.handle = rep->handle;
|
||
|
+ bo->map_handle = rep->map_handle;
|
||
|
+ bo->base.handle = rep->cur_gmr_id;
|
||
|
+ bo->base.offset = rep->cur_gmr_offset;
|
||
|
+ }
|
||
|
+
|
||
|
+ *out = &bo->base;
|
||
|
+
|
||
|
+ return 0;
|
||
|
+
|
||
|
+err_free:
|
||
|
+ free(bo);
|
||
|
+ return ret;
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+vmwgfx_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out)
|
||
|
+{
|
||
|
+ switch (key) {
|
||
|
+ default:
|
||
|
+ return -EINVAL;
|
||
|
+ }
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+vmwgfx_bo_map(struct kms_bo *_bo, void **out)
|
||
|
+{
|
||
|
+ struct vmwgfx_bo *bo = (struct vmwgfx_bo *)_bo;
|
||
|
+ void *map;
|
||
|
+
|
||
|
+ if (bo->base.ptr) {
|
||
|
+ bo->map_count++;
|
||
|
+ *out = bo->base.ptr;
|
||
|
+ return 0;
|
||
|
+ }
|
||
|
+
|
||
|
+ map = mmap(NULL, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->base.kms->fd, bo->map_handle);
|
||
|
+ if (map == MAP_FAILED)
|
||
|
+ return -errno;
|
||
|
+
|
||
|
+ bo->base.ptr = map;
|
||
|
+ bo->map_count++;
|
||
|
+ *out = bo->base.ptr;
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+vmwgfx_bo_unmap(struct kms_bo *_bo)
|
||
|
+{
|
||
|
+ struct vmwgfx_bo *bo = (struct vmwgfx_bo *)_bo;
|
||
|
+ bo->map_count--;
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+static int
|
||
|
+vmwgfx_bo_destroy(struct kms_bo *_bo)
|
||
|
+{
|
||
|
+ struct vmwgfx_bo *bo = (struct vmwgfx_bo *)_bo;
|
||
|
+ struct drm_vmw_unref_dmabuf_arg arg;
|
||
|
+
|
||
|
+ if (bo->base.ptr) {
|
||
|
+ /* XXX Sanity check map_count */
|
||
|
+ munmap(bo->base.ptr, bo->base.size);
|
||
|
+ bo->base.ptr = NULL;
|
||
|
+ }
|
||
|
+
|
||
|
+ memset(&arg, 0, sizeof(arg));
|
||
|
+ arg.handle = bo->base.handle;
|
||
|
+ drmCommandWrite(bo->base.kms->fd, DRM_VMW_UNREF_DMABUF, &arg, sizeof(arg));
|
||
|
+
|
||
|
+ free(bo);
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+int
|
||
|
+vmwgfx_create(int fd, struct kms_driver **out)
|
||
|
+{
|
||
|
+ struct kms_driver *kms;
|
||
|
+
|
||
|
+ kms = calloc(1, sizeof(*kms));
|
||
|
+ if (!kms)
|
||
|
+ return -ENOMEM;
|
||
|
+
|
||
|
+ kms->fd = fd;
|
||
|
+
|
||
|
+ kms->bo_create = vmwgfx_bo_create;
|
||
|
+ kms->bo_map = vmwgfx_bo_map;
|
||
|
+ kms->bo_unmap = vmwgfx_bo_unmap;
|
||
|
+ kms->bo_get_prop = vmwgfx_bo_get_prop;
|
||
|
+ kms->bo_destroy = vmwgfx_bo_destroy;
|
||
|
+ kms->get_prop = vmwgfx_get_prop;
|
||
|
+ kms->destroy = vmwgfx_destroy;
|
||
|
+ *out = kms;
|
||
|
+ return 0;
|
||
|
+}
|
||
|
diff --git a/nouveau/nouveau_channel.c b/nouveau/nouveau_channel.c
|
||
|
index 674c5c3..5622c1d 100644
|
||
|
--- a/nouveau/nouveau_channel.c
|
||
|
+++ b/nouveau/nouveau_channel.c
|
||
|
@@ -90,7 +90,11 @@ nouveau_channel_alloc(struct nouveau_device *dev, uint32_t fb_ctxdma,
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
- nouveau_pushbuf_init(&nvchan->base);
|
||
|
+ ret = nouveau_pushbuf_init(&nvchan->base);
|
||
|
+ if (ret) {
|
||
|
+ nouveau_channel_free((void *)&nvchan);
|
||
|
+ return ret;
|
||
|
+ }
|
||
|
|
||
|
*chan = &nvchan->base;
|
||
|
return 0;
|
||
|
@@ -102,18 +106,24 @@ nouveau_channel_free(struct nouveau_channel **chan)
|
||
|
struct nouveau_channel_priv *nvchan;
|
||
|
struct nouveau_device_priv *nvdev;
|
||
|
struct drm_nouveau_channel_free cf;
|
||
|
+ int i;
|
||
|
|
||
|
if (!chan || !*chan)
|
||
|
return;
|
||
|
nvchan = nouveau_channel(*chan);
|
||
|
+ (*chan)->flush_notify = NULL;
|
||
|
*chan = NULL;
|
||
|
nvdev = nouveau_device(nvchan->base.device);
|
||
|
|
||
|
FIRE_RING(&nvchan->base);
|
||
|
|
||
|
+ nouveau_pushbuf_fini(&nvchan->base);
|
||
|
nouveau_bo_unmap(nvchan->notifier_bo);
|
||
|
nouveau_bo_ref(NULL, &nvchan->notifier_bo);
|
||
|
|
||
|
+ for (i = 0; i < nvchan->drm.nr_subchan; i++)
|
||
|
+ free(nvchan->base.subc[i].gr);
|
||
|
+
|
||
|
nouveau_grobj_free(&nvchan->base.vram);
|
||
|
nouveau_grobj_free(&nvchan->base.gart);
|
||
|
nouveau_grobj_free(&nvchan->base.nullobj);
|
||
|
diff --git a/nouveau/nouveau_class.h b/nouveau/nouveau_class.h
|
||
|
index 0b8a6f0..8e7d0ff 100644
|
||
|
--- a/nouveau/nouveau_class.h
|
||
|
+++ b/nouveau/nouveau_class.h
|
||
|
@@ -2,6 +2,13 @@
|
||
|
|
||
|
Autogenerated file, do not edit !
|
||
|
|
||
|
+ This file was generated by renouveau-gen from renouveau.xml, the
|
||
|
+ XML database of nvidia objects and methods. renouveau-gen and
|
||
|
+ renouveau.xml can be found in CVS module renouveau of sourceforge.net
|
||
|
+ project nouveau:
|
||
|
+
|
||
|
+cvs -z3 -d:pserver:anonymous@nouveau.cvs.sourceforge.net:/cvsroot/nouveau co -P renouveau
|
||
|
+
|
||
|
**************************************************************************
|
||
|
|
||
|
Copyright (C) 2006-2008 :
|
||
|
@@ -71,25 +78,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV01_TIMER_ALARM_NOTIFY 0x00000308
|
||
|
|
||
|
|
||
|
-#define NV_IMAGE_STENCIL 0x00000010
|
||
|
-
|
||
|
-#define NV_IMAGE_STENCIL_NOTIFY 0x00000104
|
||
|
-#define NV_IMAGE_STENCIL_DMA_NOTIFY 0x00000180
|
||
|
-#define NV_IMAGE_STENCIL_IMAGE_OUTPUT 0x00000200
|
||
|
-#define NV_IMAGE_STENCIL_IMAGE_INPUT(x) (0x00000204+((x)*4))
|
||
|
-#define NV_IMAGE_STENCIL_IMAGE_INPUT__SIZE 0x00000002
|
||
|
-
|
||
|
-
|
||
|
-#define NV_IMAGE_BLEND_AND 0x00000011
|
||
|
-
|
||
|
-#define NV_IMAGE_BLEND_AND_NOP 0x00000100
|
||
|
-#define NV_IMAGE_BLEND_AND_NOTIFY 0x00000104
|
||
|
-#define NV_IMAGE_BLEND_AND_DMA_NOTIFY 0x00000180
|
||
|
-#define NV_IMAGE_BLEND_AND_IMAGE_OUTPUT 0x00000200
|
||
|
-#define NV_IMAGE_BLEND_AND_BETA_INPUT 0x00000204
|
||
|
-#define NV_IMAGE_BLEND_AND_IMAGE_INPUT 0x00000208
|
||
|
-
|
||
|
-
|
||
|
#define NV01_CONTEXT_BETA1 0x00000012
|
||
|
|
||
|
#define NV01_CONTEXT_BETA1_NOP 0x00000100
|
||
|
@@ -98,20 +86,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV01_CONTEXT_BETA1_BETA_1D31 0x00000300
|
||
|
|
||
|
|
||
|
-#define NV_IMAGE_ROP_AND 0x00000013
|
||
|
-
|
||
|
-#define NV_IMAGE_ROP_AND_NOTIFY 0x00000104
|
||
|
-#define NV_IMAGE_ROP_AND_DMA_NOTIFY 0x00000180
|
||
|
-#define NV_IMAGE_ROP_AND_IMAGE_OUTPUT 0x00000200
|
||
|
-#define NV_IMAGE_ROP_AND_ROP_INPUT 0x00000204
|
||
|
-#define NV_IMAGE_ROP_AND_IMAGE_INPUT(x) (0x00000208+((x)*4))
|
||
|
-#define NV_IMAGE_ROP_AND_IMAGE_INPUT__SIZE 0x00000002
|
||
|
-
|
||
|
-
|
||
|
-#define NV_IMAGE_COLOR_KEY 0x00000015
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
#define NV01_CONTEXT_COLOR_KEY 0x00000017
|
||
|
|
||
|
#define NV01_CONTEXT_COLOR_KEY_NOP 0x00000100
|
||
|
@@ -129,6 +103,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV01_CONTEXT_COLOR_KEY_COLOR 0x00000304
|
||
|
|
||
|
|
||
|
+#define NV04_CONTEXT_COLOR_KEY 0x00000057
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
#define NV01_CONTEXT_PATTERN 0x00000018
|
||
|
|
||
|
#define NV01_CONTEXT_PATTERN_NOP 0x00000100
|
||
|
@@ -228,6 +206,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y_MASK 0xffff0000
|
||
|
|
||
|
|
||
|
+#define NV04_RENDER_SOLID_LINE 0x0000005c
|
||
|
+
|
||
|
+#define NV04_RENDER_SOLID_LINE_BETA4 0x00000194
|
||
|
+#define NV04_RENDER_SOLID_LINE_SURFACE 0x00000198
|
||
|
+
|
||
|
+
|
||
|
#define NV01_RENDER_SOLID_TRIANGLE 0x0000001d
|
||
|
|
||
|
#define NV01_RENDER_SOLID_TRIANGLE_NOP 0x00000100
|
||
|
@@ -309,6 +293,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y_MASK 0xffff0000
|
||
|
|
||
|
|
||
|
+#define NV04_RENDER_SOLID_TRIANGLE 0x0000005d
|
||
|
+
|
||
|
+#define NV04_RENDER_SOLID_TRIANGLE_BETA4 0x00000194
|
||
|
+#define NV04_RENDER_SOLID_TRIANGLE_SURFACE 0x00000198
|
||
|
+
|
||
|
+
|
||
|
#define NV01_RENDER_SOLID_RECTANGLE 0x0000001e
|
||
|
|
||
|
#define NV01_RENDER_SOLID_RECTANGLE_NOP 0x00000100
|
||
|
@@ -343,6 +333,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H_MASK 0xffff0000
|
||
|
|
||
|
|
||
|
+#define NV04_RENDER_SOLID_RECTANGLE 0x0000005e
|
||
|
+
|
||
|
+#define NV04_RENDER_SOLID_RECTANGLE_BETA4 0x00000194
|
||
|
+#define NV04_RENDER_SOLID_RECTANGLE_SURFACE 0x00000198
|
||
|
+
|
||
|
+
|
||
|
#define NV01_IMAGE_BLIT 0x0000001f
|
||
|
|
||
|
#define NV01_IMAGE_BLIT_NOP 0x00000100
|
||
|
@@ -356,6 +352,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV01_IMAGE_BLIT_BETA1 0x00000194
|
||
|
#define NV01_IMAGE_BLIT_SURFACE 0x0000019c
|
||
|
#define NV01_IMAGE_BLIT_OPERATION 0x000002fc
|
||
|
+#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_AND 0x00000000
|
||
|
+#define NV01_IMAGE_BLIT_OPERATION_ROP_AND 0x00000001
|
||
|
+#define NV01_IMAGE_BLIT_OPERATION_BLEND_AND 0x00000002
|
||
|
+#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY 0x00000003
|
||
|
+#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_PREMULT 0x00000004
|
||
|
+#define NV01_IMAGE_BLIT_OPERATION_BLEND_PREMULT 0x00000005
|
||
|
#define NV01_IMAGE_BLIT_IMAGE_INPUT 0x00000204
|
||
|
#define NV01_IMAGE_BLIT_POINT_IN 0x00000300
|
||
|
#define NV01_IMAGE_BLIT_POINT_IN_X_SHIFT 0
|
||
|
@@ -374,6 +376,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV01_IMAGE_BLIT_SIZE_H_MASK 0xffff0000
|
||
|
|
||
|
|
||
|
+#define NV04_IMAGE_BLIT 0x0000005f
|
||
|
+
|
||
|
+#define NV04_IMAGE_BLIT_ROP 0x00000190
|
||
|
+#define NV04_IMAGE_BLIT_BETA4 0x00000198
|
||
|
+#define NV04_IMAGE_BLIT_SURFACE 0x0000019c
|
||
|
+
|
||
|
+
|
||
|
+#define NV12_IMAGE_BLIT 0x0000009f
|
||
|
+
|
||
|
+#define NV12_IMAGE_BLIT_WAIT_FOR_IDLE 0x00000108
|
||
|
+
|
||
|
+
|
||
|
#define NV01_IMAGE_FROM_CPU 0x00000021
|
||
|
|
||
|
#define NV01_IMAGE_FROM_CPU_NOP 0x00000100
|
||
|
@@ -418,6 +432,30 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV01_IMAGE_FROM_CPU_COLOR__SIZE 0x00000020
|
||
|
|
||
|
|
||
|
+#define NV04_IMAGE_FROM_CPU 0x00000061
|
||
|
+
|
||
|
+#define NV04_IMAGE_FROM_CPU_BETA4 0x00000198
|
||
|
+#define NV04_IMAGE_FROM_CPU_SURFACE 0x0000019c
|
||
|
+
|
||
|
+
|
||
|
+#define NV05_IMAGE_FROM_CPU 0x00000065
|
||
|
+
|
||
|
+#define NV05_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8
|
||
|
+
|
||
|
+
|
||
|
+#define NV10_IMAGE_FROM_CPU 0x0000008a
|
||
|
+
|
||
|
+#define NV10_IMAGE_FROM_CPU_WAIT_FOR_IDLE 0x00000108
|
||
|
+
|
||
|
+
|
||
|
+#define NV30_IMAGE_FROM_CPU 0x0000038a
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
+#define NV40_IMAGE_FROM_CPU 0x0000308a
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
#define NV01_NULL 0x00000030
|
||
|
|
||
|
|
||
|
@@ -461,6 +499,25 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__SIZE 0x00000020
|
||
|
|
||
|
|
||
|
+#define NV04_STRETCHED_IMAGE_FROM_CPU 0x00000076
|
||
|
+
|
||
|
+#define NV04_STRETCHED_IMAGE_FROM_CPU_BETA4 0x00000194
|
||
|
+#define NV04_STRETCHED_IMAGE_FROM_CPU_SURFACE 0x00000198
|
||
|
+
|
||
|
+
|
||
|
+#define NV05_STRETCHED_IMAGE_FROM_CPU 0x00000066
|
||
|
+
|
||
|
+#define NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8
|
||
|
+
|
||
|
+
|
||
|
+#define NV30_STRETCHED_IMAGE_FROM_CPU 0x00000366
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
+#define NV40_STRETCHED_IMAGE_FROM_CPU 0x00003066
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
#define NV03_SCALED_IMAGE_FROM_MEMORY 0x00000037
|
||
|
|
||
|
#define NV03_SCALED_IMAGE_FROM_MEMORY_NOP 0x00000100
|
||
|
@@ -498,45 +555,73 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_MASK 0x0000ffff
|
||
|
#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT 16
|
||
|
#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_MASK 0xffff0000
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT 0x00000310
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT_X_SHIFT 0
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT_X_MASK 0x0000ffff
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT_Y_SHIFT 16
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_POINT_Y_MASK 0xffff0000
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE 0x00000314
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE_W_SHIFT 0
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE_W_MASK 0x0000ffff
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE_H_SHIFT 16
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_OUT_SIZE_H_MASK 0xffff0000
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_DELTA_DU_DX 0x00000318
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_DELTA_DV_DY 0x0000031c
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE 0x00000400
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE_W_SHIFT 0
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE_W_MASK 0x0000ffff
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE_H_SHIFT 16
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_SIZE_H_MASK 0xffff0000
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT 0x00000404
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_PITCH_SHIFT 0
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_PITCH_MASK 0x0000ffff
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_ORIGIN_SHIFT 16
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_ORIGIN_MASK 0x00ff0000
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_ORIGIN_CENTER 0x00010000
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_ORIGIN_CORNER 0x00020000
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_INTERPOLATOR_SHIFT 24
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_FORMAT_INTERPOLATOR_MASK 0xff000000
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_OFFSET 0x00000408
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT 0x0000040c
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT_U_SHIFT 0
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT_U_MASK 0x0000ffff
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT_V_SHIFT 16
|
||
|
-#define NV03_SCALED_IMAGE_FROM_MEMORY_IMAGE_IN_POINT_V_MASK 0xffff0000
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT 0x00000310
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X_SHIFT 0
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X_MASK 0x0000ffff
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT 16
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_MASK 0xffff0000
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE 0x00000314
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W_SHIFT 0
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W_MASK 0x0000ffff
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT 16
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_MASK 0xffff0000
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_DU_DX 0x00000318
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_DV_DY 0x0000031c
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE 0x00000400
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W_SHIFT 0
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W_MASK 0x0000ffff
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT 16
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_MASK 0xffff0000
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT 0x00000404
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_SHIFT 0
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_MASK 0x0000ffff
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_SHIFT 16
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_MASK 0x00ff0000
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER 0x00010000
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CORNER 0x00020000
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_SHIFT 24
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_MASK 0xff000000
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE 0x00000000
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_BILINEAR 0x01000000
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OFFSET 0x00000408
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT 0x0000040c
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U_SHIFT 0
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U_MASK 0x0000ffff
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V_SHIFT 16
|
||
|
+#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V_MASK 0xffff0000
|
||
|
+
|
||
|
+
|
||
|
+#define NV04_SCALED_IMAGE_FROM_MEMORY 0x00000077
|
||
|
+
|
||
|
+#define NV04_SCALED_IMAGE_FROM_MEMORY_BETA4 0x00000194
|
||
|
+#define NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198
|
||
|
+
|
||
|
+
|
||
|
+#define NV05_SCALED_IMAGE_FROM_MEMORY 0x00000063
|
||
|
+
|
||
|
+#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION 0x000002fc
|
||
|
+#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER 0x00000000
|
||
|
+#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE 0x00000001
|
||
|
+#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE 0x00000002
|
||
|
+
|
||
|
+
|
||
|
+#define NV10_SCALED_IMAGE_FROM_MEMORY 0x00000089
|
||
|
+
|
||
|
+#define NV10_SCALED_IMAGE_FROM_MEMORY_WAIT_FOR_IDLE 0x00000108
|
||
|
+
|
||
|
+
|
||
|
+#define NV30_SCALED_IMAGE_FROM_MEMORY 0x00000389
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
+#define NV40_SCALED_IMAGE_FROM_MEMORY 0x00003089
|
||
|
+
|
||
|
|
||
|
|
||
|
#define NV04_DVD_SUBPICTURE 0x00000038
|
||
|
|
||
|
#define NV04_DVD_SUBPICTURE_NOP 0x00000100
|
||
|
#define NV04_DVD_SUBPICTURE_NOTIFY 0x00000104
|
||
|
-#define NV04_DVD_SUBPICTURE_WAIT_FOR_IDLE 0x00000108
|
||
|
#define NV04_DVD_SUBPICTURE_DMA_NOTIFY 0x00000180
|
||
|
#define NV04_DVD_SUBPICTURE_DMA_OVERLAY 0x00000184
|
||
|
#define NV04_DVD_SUBPICTURE_DMA_IMAGEIN 0x00000188
|
||
|
@@ -595,6 +680,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV04_DVD_SUBPICTURE_OVERLAY_POINT_V_MASK 0xffff0000
|
||
|
|
||
|
|
||
|
+#define NV10_DVD_SUBPICTURE 0x00000088
|
||
|
+
|
||
|
+#define NV10_DVD_SUBPICTURE_WAIT_FOR_IDLE 0x00000108
|
||
|
+
|
||
|
+
|
||
|
#define NV04_MEMORY_TO_MEMORY_FORMAT 0x00000039
|
||
|
|
||
|
#define NV04_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100
|
||
|
@@ -610,12 +700,41 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV04_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT 0x00000320
|
||
|
#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT 0x00000324
|
||
|
#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_SHIFT 0
|
||
|
-#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_MASK 0x0000000f
|
||
|
+#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_MASK 0x000000ff
|
||
|
#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_SHIFT 8
|
||
|
-#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_MASK 0x00000f00
|
||
|
+#define NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_MASK 0x0000ff00
|
||
|
#define NV04_MEMORY_TO_MEMORY_FORMAT_BUF_NOTIFY 0x00000328
|
||
|
|
||
|
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
|
||
|
+
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_SERIALIZE 0x00000110
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_IN 0x00000200
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_IN 0x00000204
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_IN 0x00000208
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_IN 0x0000020c
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_DEPTH_IN 0x00000210
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Z 0x00000214
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN 0x00000218
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_X_SHIFT 0
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_X_MASK 0x0000ffff
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Y_SHIFT 16
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Y_MASK 0xffff0000
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_OUT 0x0000021c
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_OUT 0x00000220
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_OUT 0x00000224
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_OUT 0x00000228
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_DEPTH_OUT 0x0000022c
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Z 0x00000230
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT 0x00000234
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_X_SHIFT 0
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_X_MASK 0x0000ffff
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Y_SHIFT 16
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Y_MASK 0xffff0000
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238
|
||
|
+#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c
|
||
|
+
|
||
|
+
|
||
|
#define NV01_MEMORY_LOCAL_BANKED 0x0000003d
|
||
|
|
||
|
|
||
|
@@ -665,6 +784,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV04_CONTEXT_SURFACES_2D_OFFSET_DESTIN 0x0000030c
|
||
|
|
||
|
|
||
|
+#define NV10_CONTEXT_SURFACES_2D 0x00000062
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
+#define NV30_CONTEXT_SURFACES_2D 0x00000362
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
+#define NV40_CONTEXT_SURFACES_2D 0x00003062
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
#define NV03_CONTEXT_ROP 0x00000043
|
||
|
|
||
|
#define NV03_CONTEXT_ROP_NOP 0x00000100
|
||
|
@@ -852,99 +983,99 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV03_VIDEO_LUT_CURSOR_DAC_SET_PIXEL_CLOCK 0x000003a0
|
||
|
|
||
|
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE 0x00000048
|
||
|
-
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_NOP 0x00000100
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_NOTIFY 0x00000104
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_PATCH 0x0000010c
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_DMA_NOTIFY 0x00000180
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_DMA_TEXTURE 0x00000184
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CLIP_RECTANGLE 0x00000188
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SURFACE 0x0000018c
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_OFFSET 0x00000304
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT 0x00000308
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_SHIFT 0
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_MASK 0x0000ffff
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_SHIFT 16
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_MASK 0x000f0000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_SHIFT 20
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_MASK 0x00f00000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_SHIFT 24
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_MASK 0x0f000000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_SHIFT 28
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_MASK 0xf0000000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER 0x0000030c
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER_SPREAD_X_SHIFT 0
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER_SPREAD_X_MASK 0x0000001f
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_SHIFT 8
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_MASK 0x00001f00
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_SHIFT 16
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_MASK 0x00ff0000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR 0x00000310
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_B_SHIFT 0
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_B_MASK 0x000000ff
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_G_SHIFT 8
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_G_MASK 0x0000ff00
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_R_SHIFT 16
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_FOG_COLOR_R_MASK 0x00ff0000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT 0x00000314
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_SHIFT 0
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_MASK 0x0000000f
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_SHIFT 4
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_MASK 0x00000030
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_SHIFT 6
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_MASK 0x000000c0
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_SHIFT 8
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_MASK 0x00000f00
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_SHIFT 12
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_MASK 0x00007000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_PERSPECTIVE_ENABLE (1 << 15)
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_SHIFT 16
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_MASK 0x000f0000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_SHIFT 20
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_MASK 0x00f00000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_SHIFT 24
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_MASK 0x07000000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_SHIFT 27
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_MASK 0x18000000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_BETA (1 << 29)
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_DST_BLEND (1 << 30)
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_CONTROL_OUT_SRC_BLEND (1 << 31)
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL 0x00000318
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_SHIFT 0
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_MASK 0x000000ff
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_SHIFT 8
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_MASK 0xffffff00
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR(x) (0x00001000+((x)*32))
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR__SIZE 0x00000040
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I0_SHIFT 0
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I0_MASK 0x0000000f
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I1_SHIFT 4
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I1_MASK 0x000000f0
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I2_SHIFT 8
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I2_MASK 0x00000f00
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I3_SHIFT 12
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I3_MASK 0x0000f000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I4_SHIFT 16
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I4_MASK 0x000f0000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I5_SHIFT 20
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_I5_MASK 0x00f00000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_FOG_SHIFT 24
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_SPECULAR_FOG_MASK 0xff000000
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_COLOR(x) (0x00001004+((x)*32))
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_COLOR__SIZE 0x00000040
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_X(x) (0x00001008+((x)*32))
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_X__SIZE 0x00000040
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_Y(x) (0x0000100c+((x)*32))
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_Y__SIZE 0x00000040
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_Z(x) (0x00001010+((x)*32))
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_Z__SIZE 0x00000040
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_M(x) (0x00001014+((x)*32))
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_M__SIZE 0x00000040
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_U(x) (0x00001018+((x)*32))
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_U__SIZE 0x00000040
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_V(x) (0x0000101c+((x)*32))
|
||
|
-#define NV03_DX3_TEXTURED_TRIANGLE_V__SIZE 0x00000040
|
||
|
+#define NV03_TEXTURED_TRIANGLE 0x00000048
|
||
|
+
|
||
|
+#define NV03_TEXTURED_TRIANGLE_NOP 0x00000100
|
||
|
+#define NV03_TEXTURED_TRIANGLE_NOTIFY 0x00000104
|
||
|
+#define NV03_TEXTURED_TRIANGLE_PATCH 0x0000010c
|
||
|
+#define NV03_TEXTURED_TRIANGLE_DMA_NOTIFY 0x00000180
|
||
|
+#define NV03_TEXTURED_TRIANGLE_DMA_TEXTURE 0x00000184
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CLIP_RECTANGLE 0x00000188
|
||
|
+#define NV03_TEXTURED_TRIANGLE_SURFACE 0x0000018c
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TEXTURE_OFFSET 0x00000304
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT 0x00000308
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_SHIFT 0
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_MASK 0x0000ffff
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_SHIFT 16
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_MASK 0x000f0000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_SHIFT 20
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_MASK 0x00f00000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_SHIFT 24
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_MASK 0x0f000000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_SHIFT 28
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_MASK 0xf0000000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FILTER 0x0000030c
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_X_SHIFT 0
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_X_MASK 0x0000001f
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_SHIFT 8
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_MASK 0x00001f00
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_SHIFT 16
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_MASK 0x00ff0000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FOG_COLOR 0x00000310
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_B_SHIFT 0
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_B_MASK 0x000000ff
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_G_SHIFT 8
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_G_MASK 0x0000ff00
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_R_SHIFT 16
|
||
|
+#define NV03_TEXTURED_TRIANGLE_FOG_COLOR_R_MASK 0x00ff0000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT 0x00000314
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_SHIFT 0
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_MASK 0x0000000f
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_SHIFT 4
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_MASK 0x00000030
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_SHIFT 6
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_MASK 0x000000c0
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_SHIFT 8
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_MASK 0x00000f00
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_SHIFT 12
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_MASK 0x00007000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_PERSPECTIVE_ENABLE (1 << 15)
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_SHIFT 16
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_MASK 0x000f0000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_SHIFT 20
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_MASK 0x00f00000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_SHIFT 24
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_MASK 0x07000000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_SHIFT 27
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_MASK 0x18000000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_BETA (1 << 29)
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_DST_BLEND (1 << 30)
|
||
|
+#define NV03_TEXTURED_TRIANGLE_CONTROL_OUT_SRC_BLEND (1 << 31)
|
||
|
+#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL 0x00000318
|
||
|
+#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_SHIFT 0
|
||
|
+#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_MASK 0x000000ff
|
||
|
+#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_SHIFT 8
|
||
|
+#define NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_MASK 0xffffff00
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR(x) (0x00001000+((x)*32))
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR__SIZE 0x00000080
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I0_SHIFT 0
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I0_MASK 0x0000000f
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I1_SHIFT 4
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I1_MASK 0x000000f0
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I2_SHIFT 8
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I2_MASK 0x00000f00
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I3_SHIFT 12
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I3_MASK 0x0000f000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I4_SHIFT 16
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I4_MASK 0x000f0000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I5_SHIFT 20
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I5_MASK 0x00f00000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_SHIFT 24
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_MASK 0xff000000
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_COLOR(x) (0x00001004+((x)*32))
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_COLOR__SIZE 0x00000080
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SX(x) (0x00001008+((x)*32))
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SX__SIZE 0x00000080
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SY(x) (0x0000100c+((x)*32))
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SY__SIZE 0x00000080
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SZ(x) (0x00001010+((x)*32))
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_SZ__SIZE 0x00000080
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_RHW(x) (0x00001014+((x)*32))
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_RHW__SIZE 0x00000080
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_TU(x) (0x00001018+((x)*32))
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_TU__SIZE 0x00000080
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_TV(x) (0x0000101c+((x)*32))
|
||
|
+#define NV03_TEXTURED_TRIANGLE_TLVERTEX_TV__SIZE 0x00000080
|
||
|
|
||
|
|
||
|
#define NV04_GDI_RECTANGLE_TEXT 0x0000004a
|
||
|
@@ -1265,6 +1396,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV04_SWIZZLED_SURFACE_OFFSET 0x00000304
|
||
|
|
||
|
|
||
|
+#define NV20_SWIZZLED_SURFACE 0x0000009e
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
+#define NV30_SWIZZLED_SURFACE 0x0000039e
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
+#define NV40_SWIZZLED_SURFACE 0x0000309e
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
#define NV04_CONTEXT_SURFACES_3D 0x00000053
|
||
|
|
||
|
#define NV04_CONTEXT_SURFACES_3D_NOP 0x00000100
|
||
|
@@ -1315,429 +1458,460 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA 0x00000310
|
||
|
|
||
|
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE 0x00000054
|
||
|
-
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_NOP 0x00000100
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_NOTIFY 0x00000104
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_DMA_NOTIFY 0x00000180
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_DMA_A 0x00000184
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_DMA_B 0x00000188
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_SURFACE 0x0000018c
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_COLORKEY 0x00000300
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_OFFSET 0x00000304
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT 0x00000308
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_DMA_SHIFT 0
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_DMA_MASK 0x00000003
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_SHIFT 2
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_MASK 0x0000000c
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT 4
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK 0x00000030
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CENTER 0x00000010
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CORNER 0x00000020
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT 6
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_MASK 0x000000c0
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CENTER 0x00000040
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CORNER 0x00000080
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_SHIFT 8
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_MASK 0x00000f00
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_Y8 0x00000100
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_A1R5G5B5 0x00000200
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_X1R5G5B5 0x00000300
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_A4R4G4B4 0x00000400
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_R5G6B5 0x00000500
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_A8R8G8B8 0x00000600
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_COLOR_X8R8G8B8 0x00000700
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT 12
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK 0x0000f000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT 16
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_MASK 0x000f0000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT 20
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_MASK 0x00f00000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT 24
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MASK 0x07000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_REPEAT 0x01000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MIRRORED_REPEAT 0x02000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE 0x03000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_BORDER 0x04000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP 0x05000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_WRAPU (1 << 27)
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_SHIFT 28
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MASK 0x70000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_REPEAT 0x10000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MIRRORED_REPEAT 0x20000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_EDGE 0x30000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_BORDER 0x40000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP 0x50000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FORMAT_WRAPV (1 << 31)
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER 0x0000030c
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT 0
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK 0x000000ff
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT 8
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK 0x00007f00
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE (1 << 15)
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT 16
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK 0x00ff0000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_SHIFT 24
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_MASK 0x07000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST 0x01000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR 0x02000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x03000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x04000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x05000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x06000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE (1 << 27)
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_SHIFT 28
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_MASK 0x70000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST 0x10000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR 0x20000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE (1 << 31)
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND 0x00000310
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_SHIFT 0
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_MASK 0x0000000f
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_MASK_BIT_SHIFT 4
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_MASK_BIT_MASK 0x00000030
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_SHIFT 6
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_MASK 0x000000c0
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_FLAT 0x00000040
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_GOURAUD 0x00000080
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_PHONG 0x000000c0
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE_SHIFT 8
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE_MASK 0x00000f00
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE_SHIFT 12
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE_MASK 0x0000f000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_FOG_ENABLE_SHIFT 16
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_FOG_ENABLE_MASK 0x000f0000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_ALPHA_ENABLE_SHIFT 20
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_ALPHA_ENABLE_MASK 0x00f00000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_SHIFT 24
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_SRC_MASK 0x0f000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_SHIFT 28
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_BLEND_DST_MASK 0xf0000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL 0x00000314
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_SHIFT 0
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_MASK 0x000000ff
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_SHIFT 8
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_MASK 0x00000f00
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_TEST_ENABLE (1 << 12)
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ORIGIN (1 << 13)
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE_SHIFT 14
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE_MASK 0x0000c000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_SHIFT 16
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_MASK 0x000f0000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_SHIFT 20
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_MASK 0x00300000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_DITHER_ENABLE (1 << 22)
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_PERSPECTIVE_ENABLE (1 << 23)
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_WRITE_ENABLE_SHIFT 24
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_WRITE_ENABLE_MASK 0x3f000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_SHIFT 30
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_MASK 0xc0000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR 0x00000318
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_B_SHIFT 0
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_B_MASK 0x000000ff
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_G_SHIFT 8
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_G_MASK 0x0000ff00
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_R_SHIFT 16
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_R_MASK 0x00ff0000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_A_SHIFT 24
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_FOGCOLOR_A_MASK 0xff000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX(x) (0x00000400+((x)*32))
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SX__SIZE 0x00000010
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SY(x) (0x00000404+((x)*32))
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SY__SIZE 0x00000010
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SZ(x) (0x00000408+((x)*32))
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SZ__SIZE 0x00000010
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_RHW(x) (0x0000040c+((x)*32))
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_RHW__SIZE 0x00000010
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR(x) (0x00000410+((x)*32))
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR__SIZE 0x00000010
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_SHIFT 0
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_MASK 0x000000ff
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_SHIFT 8
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_MASK 0x0000ff00
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_SHIFT 16
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_MASK 0x00ff0000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_SHIFT 24
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_MASK 0xff000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR(x) (0x00000414+((x)*32))
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR__SIZE 0x00000010
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_SHIFT 0
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_MASK 0x000000ff
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_SHIFT 8
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_MASK 0x0000ff00
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_SHIFT 16
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_MASK 0x00ff0000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_SHIFT 24
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_MASK 0xff000000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_TU(x) (0x00000418+((x)*32))
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_TU__SIZE 0x00000010
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_TV(x) (0x0000041c+((x)*32))
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_TV__SIZE 0x00000010
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE(x) (0x00000600+((x)*4))
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE__SIZE 0x00000040
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I0_SHIFT 0
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I0_MASK 0x0000000f
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I1_SHIFT 4
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I1_MASK 0x000000f0
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I2_SHIFT 8
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I2_MASK 0x00000f00
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I3_SHIFT 12
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I3_MASK 0x0000f000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I4_SHIFT 16
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I4_MASK 0x000f0000
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I5_SHIFT 20
|
||
|
-#define NV04_DX5_TEXTURED_TRIANGLE_TLVERTEX_DRAWPRIMITIVE_I5_MASK 0x00f00000
|
||
|
-
|
||
|
-
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE 0x00000055
|
||
|
-
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_NOP 0x00000100
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_NOTIFY 0x00000104
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_DMA_NOTIFY 0x00000180
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_DMA_A 0x00000184
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_DMA_B 0x00000188
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_SURFACE 0x0000018c
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_OFFSET(x) (0x00000308+((x)*4))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_OFFSET__SIZE 0x00000002
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT(x) (0x00000310+((x)*4))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT__SIZE 0x00000002
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_DMA_SHIFT 0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_DMA_MASK 0x0000000f
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT 4
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK 0x00000030
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT 6
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_MASK 0x000000c0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_COLOR_SHIFT 8
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_COLOR_MASK 0x00000f00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT 12
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK 0x0000f000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT 16
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_MASK 0x000f0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT 20
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_MASK 0x00f00000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_SHIFT 24
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_MASK 0x07000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_WRAPU (1 << 27)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_SHIFT 28
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_MASK 0x70000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FORMAT_WRAPV (1 << 31)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER(x) (0x00000318+((x)*4))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER__SIZE 0x00000002
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT 0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK 0x000000ff
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT 8
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK 0x00007f00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE (1 << 15)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT 16
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK 0x00ff0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MINIFY_SHIFT 24
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MINIFY_MASK 0x07000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE (1 << 27)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MAGNIFY_SHIFT 28
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_MAGNIFY_MASK 0x70000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE (1 << 31)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA 0x00000320
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_INVERSE0 (1 << 0)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ALPHA0 (1 << 1)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT0_SHIFT 2
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT0_MASK 0x000000fc
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_INVERSE1 (1 << 8)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ALPHA1 (1 << 9)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT1_SHIFT 10
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT1_MASK 0x0000fc00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_INVERSE2 (1 << 16)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ALPHA2 (1 << 17)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT2_SHIFT 18
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT2_MASK 0x00fc0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_INVERSE3 (1 << 24)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ALPHA3 (1 << 25)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT3_SHIFT 26
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_ARGUMENT3_MASK 0x1c000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_OPERATION_SHIFT 29
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_ALPHA_OPERATION_MASK 0xe0000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR 0x00000324
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_INVERSE0 (1 << 0)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ALPHA0 (1 << 1)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT0_SHIFT 2
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT0_MASK 0x000000fc
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_INVERSE1 (1 << 8)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ALPHA1 (1 << 9)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT1_SHIFT 10
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT1_MASK 0x0000fc00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_INVERSE2 (1 << 16)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ALPHA2 (1 << 17)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT2_SHIFT 18
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT2_MASK 0x00fc0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_INVERSE3 (1 << 24)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ALPHA3 (1 << 25)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT3_SHIFT 26
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_ARGUMENT3_MASK 0x1c000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_OPERATION_SHIFT 29
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_0_COLOR_OPERATION_MASK 0xe0000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA 0x0000032c
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_INVERSE0 (1 << 0)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ALPHA0 (1 << 1)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT0_SHIFT 2
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT0_MASK 0x000000fc
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_INVERSE1 (1 << 8)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ALPHA1 (1 << 9)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT1_SHIFT 10
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT1_MASK 0x0000fc00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_INVERSE2 (1 << 16)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ALPHA2 (1 << 17)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT2_SHIFT 18
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT2_MASK 0x00fc0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_INVERSE3 (1 << 24)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ALPHA3 (1 << 25)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT3_SHIFT 26
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_ARGUMENT3_MASK 0x1c000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_OPERATION_SHIFT 29
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_ALPHA_OPERATION_MASK 0xe0000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR 0x00000330
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_INVERSE0 (1 << 0)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ALPHA0 (1 << 1)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT0_SHIFT 2
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT0_MASK 0x000000fc
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_INVERSE1 (1 << 8)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ALPHA1 (1 << 9)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT1_SHIFT 10
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT1_MASK 0x0000fc00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_INVERSE2 (1 << 16)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ALPHA2 (1 << 17)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT2_SHIFT 18
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT2_MASK 0x00fc0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_INVERSE3 (1 << 24)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ALPHA3 (1 << 25)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT3_SHIFT 26
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_ARGUMENT3_MASK 0x1c000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_OPERATION_SHIFT 29
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_1_COLOR_OPERATION_MASK 0xe0000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR 0x00000334
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_SHIFT 0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_MASK 0x000000ff
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_SHIFT 8
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_MASK 0x0000ff00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_SHIFT 16
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_MASK 0x00ff0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_SHIFT 24
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_MASK 0xff000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND 0x00000338
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_MASK_BIT_SHIFT 4
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_MASK_BIT_MASK 0x00000030
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_SHIFT 6
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_MASK 0x000000c0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE_SHIFT 8
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE_MASK 0x00000f00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE_SHIFT 12
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE_MASK 0x0000f000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_FOG_ENABLE_SHIFT 16
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_FOG_ENABLE_MASK 0x000f0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_ALPHA_ENABLE_SHIFT 20
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_ALPHA_ENABLE_MASK 0x00f00000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_SHIFT 24
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_SRC_MASK 0x0f000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_SHIFT 28
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_BLEND_DST_MASK 0xf0000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0 0x0000033c
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_SHIFT 0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_MASK 0x000000ff
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_SHIFT 8
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_MASK 0x00000f00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_TEST_ENABLE (1 << 12)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ORIGIN (1 << 13)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_ENABLE_SHIFT 14
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_ENABLE_MASK 0x0000c000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_SHIFT 16
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_MASK 0x000f0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_SHIFT 20
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_MASK 0x00300000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_DITHER_ENABLE (1 << 22)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_PERSPECTIVE_ENABLE (1 << 23)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_WRITE_ENABLE (1 << 24)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE_ENABLE (1 << 25)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE_ENABLE (1 << 26)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE_ENABLE (1 << 27)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE_ENABLE (1 << 28)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE_ENABLE (1 << 29)
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_SHIFT 30
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_MASK 0xc0000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1 0x00000340
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_TEST_ENABLE_SHIFT 0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_TEST_ENABLE_MASK 0x0000000f
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_SHIFT 4
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_MASK 0x000000f0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_SHIFT 8
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_MASK 0x0000ff00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_SHIFT 16
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_MASK 0x00ff0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_SHIFT 24
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_MASK 0xff000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2 0x00000344
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_SHIFT 0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_MASK 0x0000000f
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_SHIFT 4
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_MASK 0x000000f0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_SHIFT 8
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_MASK 0x00000f00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR 0x00000348
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_B_SHIFT 0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_B_MASK 0x000000ff
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_G_SHIFT 8
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_G_MASK 0x0000ff00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_R_SHIFT 16
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_R_MASK 0x00ff0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_A_SHIFT 24
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_FOGCOLOR_A_MASK 0xff000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SX(x) (0x00000400+((x)*40))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SX__SIZE 0x00000008
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SY(x) (0x00000404+((x)*40))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SY__SIZE 0x00000008
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SZ(x) (0x00000408+((x)*40))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SZ__SIZE 0x00000008
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_RHW(x) (0x0000040c+((x)*40))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_RHW__SIZE 0x00000008
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR(x) (0x00000410+((x)*40))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR__SIZE 0x00000008
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_SHIFT 0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_MASK 0x000000ff
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_SHIFT 8
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_MASK 0x0000ff00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_SHIFT 16
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_MASK 0x00ff0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_SHIFT 24
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_MASK 0xff000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR(x) (0x00000414+((x)*40))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR__SIZE 0x00000008
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_SHIFT 0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_MASK 0x000000ff
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_SHIFT 8
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_MASK 0x0000ff00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_SHIFT 16
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_MASK 0x00ff0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_SHIFT 24
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_MASK 0xff000000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TU0(x) (0x00000418+((x)*40))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TU0__SIZE 0x00000008
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TV0(x) (0x0000041c+((x)*40))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TV0__SIZE 0x00000008
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TU1(x) (0x00000420+((x)*40))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TU1__SIZE 0x00000008
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TV1(x) (0x00000424+((x)*40))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_TV1__SIZE 0x00000008
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE(x) (0x00000540+((x)*4))
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE__SIZE 0x00000030
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I0_SHIFT 0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I0_MASK 0x0000000f
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I1_SHIFT 4
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I1_MASK 0x000000f0
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I2_SHIFT 8
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I2_MASK 0x00000f00
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I3_SHIFT 12
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I3_MASK 0x0000f000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I4_SHIFT 16
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I4_MASK 0x000f0000
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I5_SHIFT 20
|
||
|
-#define NV04_DX6_MULTITEX_TRIANGLE_TLMTVERTEX_DRAWPRIMITIVE_I5_MASK 0x00f00000
|
||
|
+#define NV10_CONTEXT_SURFACES_3D 0x00000093
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
+#define NV04_TEXTURED_TRIANGLE 0x00000054
|
||
|
+
|
||
|
+#define NV04_TEXTURED_TRIANGLE_NOP 0x00000100
|
||
|
+#define NV04_TEXTURED_TRIANGLE_NOTIFY 0x00000104
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DMA_NOTIFY 0x00000180
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DMA_A 0x00000184
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DMA_B 0x00000188
|
||
|
+#define NV04_TEXTURED_TRIANGLE_SURFACE 0x0000018c
|
||
|
+#define NV04_TEXTURED_TRIANGLE_COLORKEY 0x00000300
|
||
|
+#define NV04_TEXTURED_TRIANGLE_OFFSET 0x00000304
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT 0x00000308
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_DMA_A (1 << 0)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_DMA_B (1 << 1)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_SHIFT 2
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_MASK 0x0000000c
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT 4
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK 0x00000030
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CENTER 0x00000010
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CORNER 0x00000020
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT 6
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_MASK 0x000000c0
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CENTER 0x00000040
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CORNER 0x00000080
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_SHIFT 8
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_MASK 0x00000f00
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_Y8 0x00000100
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A1R5G5B5 0x00000200
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_X1R5G5B5 0x00000300
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A4R4G4B4 0x00000400
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_R5G6B5 0x00000500
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A8R8G8B8 0x00000600
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_X8R8G8B8 0x00000700
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT 12
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK 0x0000f000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT 16
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_MASK 0x000f0000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT 20
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_MASK 0x00f00000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT 24
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MASK 0x07000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_REPEAT 0x01000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MIRRORED_REPEAT 0x02000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE 0x03000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_BORDER 0x04000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP 0x05000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_WRAPU (1 << 27)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_SHIFT 28
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MASK 0x70000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_REPEAT 0x10000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MIRRORED_REPEAT 0x20000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_EDGE 0x30000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_BORDER 0x40000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP 0x50000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FORMAT_WRAPV (1 << 31)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER 0x0000030c
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT 0
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK 0x000000ff
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT 8
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK 0x00007f00
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE (1 << 15)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT 16
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK 0x00ff0000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_SHIFT 24
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_MASK 0x07000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST 0x01000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR 0x02000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST 0x03000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST 0x04000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR 0x05000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR 0x06000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE (1 << 27)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_SHIFT 28
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_MASK 0x70000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST 0x10000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR 0x20000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE (1 << 31)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND 0x00000310
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_SHIFT 0
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_MASK 0x0000000f
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_MASK_BIT_SHIFT 4
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_MASK_BIT_MASK 0x00000030
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_SHIFT 6
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_MASK 0x000000c0
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_FLAT 0x00000040
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_GOURAUD 0x00000080
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_PHONG 0x000000c0
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE (1 << 8)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE_SHIFT 12
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE_MASK 0x0000f000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_FOG_ENABLE (1 << 16)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_BLEND_ENABLE (1 << 20)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_SHIFT 24
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_MASK 0x0f000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_SHIFT 28
|
||
|
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_MASK 0xf0000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL 0x00000314
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_SHIFT 0
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_MASK 0x000000ff
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_SHIFT 8
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_MASK 0x00000f00
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_ENABLE (1 << 12)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ORIGIN (1 << 13)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE (1 << 14)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_SHIFT 16
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_MASK 0x000f0000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_SHIFT 20
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_MASK 0x00300000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_BOTH 0x00000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_NONE 0x00100000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_CW 0x00200000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_CCW 0x00300000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_DITHER_ENABLE (1 << 22)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_PERSPECTIVE_ENABLE (1 << 23)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_WRITE (1 << 24)
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_SHIFT 30
|
||
|
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_MASK 0xc0000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR 0x00000318
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_B_SHIFT 0
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_B_MASK 0x000000ff
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_G_SHIFT 8
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_G_MASK 0x0000ff00
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_R_SHIFT 16
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_R_MASK 0x00ff0000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_A_SHIFT 24
|
||
|
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_A_MASK 0xff000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(x) (0x00000400+((x)*32))
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SX__SIZE 0x00000010
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SY(x) (0x00000404+((x)*32))
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SY__SIZE 0x00000010
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SZ(x) (0x00000408+((x)*32))
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SZ__SIZE 0x00000010
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_RHW(x) (0x0000040c+((x)*32))
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_RHW__SIZE 0x00000010
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR(x) (0x00000410+((x)*32))
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR__SIZE 0x00000010
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_SHIFT 0
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_MASK 0x000000ff
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_SHIFT 8
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_MASK 0x0000ff00
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_SHIFT 16
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_MASK 0x00ff0000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_SHIFT 24
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_MASK 0xff000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR(x) (0x00000414+((x)*32))
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR__SIZE 0x00000010
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_SHIFT 0
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_MASK 0x000000ff
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_SHIFT 8
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_MASK 0x0000ff00
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_SHIFT 16
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_MASK 0x00ff0000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_SHIFT 24
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_MASK 0xff000000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TU(x) (0x00000418+((x)*32))
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TU__SIZE 0x00000010
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TV(x) (0x0000041c+((x)*32))
|
||
|
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TV__SIZE 0x00000010
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE(x) (0x00000600+((x)*4))
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE__SIZE 0x00000040
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I0_SHIFT 0
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I0_MASK 0x0000000f
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I1_SHIFT 4
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I1_MASK 0x000000f0
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I2_SHIFT 8
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I2_MASK 0x00000f00
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I3_SHIFT 12
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I3_MASK 0x0000f000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I4_SHIFT 16
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I4_MASK 0x000f0000
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I5_SHIFT 20
|
||
|
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I5_MASK 0x00f00000
|
||
|
+
|
||
|
+
|
||
|
+#define NV10_TEXTURED_TRIANGLE 0x00000094
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
+#define NV04_MULTITEX_TRIANGLE 0x00000055
|
||
|
+
|
||
|
+#define NV04_MULTITEX_TRIANGLE_NOP 0x00000100
|
||
|
+#define NV04_MULTITEX_TRIANGLE_NOTIFY 0x00000104
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DMA_NOTIFY 0x00000180
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DMA_A 0x00000184
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DMA_B 0x00000188
|
||
|
+#define NV04_MULTITEX_TRIANGLE_SURFACE 0x0000018c
|
||
|
+#define NV04_MULTITEX_TRIANGLE_OFFSET(x) (0x00000308+((x)*4))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_OFFSET__SIZE 0x00000002
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT(x) (0x00000310+((x)*4))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT__SIZE 0x00000002
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_DMA_A (1 << 0)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_DMA_B (1 << 1)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT 4
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK 0x00000030
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT 6
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_MASK 0x000000c0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_SHIFT 8
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_MASK 0x00000f00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT 12
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK 0x0000f000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT 16
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_MASK 0x000f0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT 20
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_MASK 0x00f00000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_SHIFT 24
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_MASK 0x07000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_WRAPU (1 << 27)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_SHIFT 28
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_MASK 0x70000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FORMAT_WRAPV (1 << 31)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER(x) (0x00000318+((x)*4))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER__SIZE 0x00000002
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT 0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK 0x000000ff
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT 8
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK 0x00007f00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE (1 << 15)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT 16
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK 0x00ff0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_SHIFT 24
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_MASK 0x07000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE (1 << 27)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_MAGNIFY_SHIFT 28
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_MAGNIFY_MASK 0x70000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE (1 << 31)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA(x) (0x00000320+((x)*12))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA__SIZE 0x00000002
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE0 (1 << 0)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_SHIFT 2
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_MASK 0x000000fc
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_ZERO 0x00000004
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_CONSTANT 0x00000008
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_PRIMARY_COLOR 0x0000000c
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_PREVIOUS 0x00000010
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_TEXTURE0 0x00000014
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_TEXTURE1 0x00000018
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE1 (1 << 8)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_SHIFT 10
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_MASK 0x0000fc00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_ZERO 0x00000400
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_CONSTANT 0x00000800
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_PRIMARY_COLOR 0x00000c00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_PREVIOUS 0x00001000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_TEXTURE0 0x00001400
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_TEXTURE1 0x00001800
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE2 (1 << 16)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_SHIFT 18
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_MASK 0x00fc0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_ZERO 0x00040000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_CONSTANT 0x00080000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_PRIMARY_COLOR 0x000c0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_PREVIOUS 0x00100000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_TEXTURE0 0x00140000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_TEXTURE1 0x00180000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE3 (1 << 24)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_SHIFT 26
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_MASK 0x1c000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_ZERO 0x04000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_CONSTANT 0x08000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_PRIMARY_COLOR 0x0c000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_PREVIOUS 0x10000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_TEXTURE0 0x14000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_TEXTURE1 0x18000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SHIFT 29
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_MASK 0xe0000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_IDENTITY 0x20000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SCALE2 0x40000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SCALE4 0x60000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_BIAS 0x80000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_BIAS_SCALE2 0xe0000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR(x) (0x00000324+((x)*12))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR__SIZE 0x00000002
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE0 (1 << 0)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA0 (1 << 1)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_SHIFT 2
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_MASK 0x000000fc
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_ZERO 0x00000004
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_CONSTANT 0x00000008
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_PRIMARY_COLOR 0x0000000c
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_PREVIOUS 0x00000010
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_TEXTURE0 0x00000014
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_TEXTURE1 0x00000018
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE1 (1 << 8)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA1 (1 << 9)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_SHIFT 10
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_MASK 0x0000fc00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_ZERO 0x00000400
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_CONSTANT 0x00000800
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_PRIMARY_COLOR 0x00000c00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_PREVIOUS 0x00001000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_TEXTURE0 0x00001400
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_TEXTURE1 0x00001800
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE2 (1 << 16)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA2 (1 << 17)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_SHIFT 18
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_MASK 0x00fc0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_ZERO 0x00040000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_CONSTANT 0x00080000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_PRIMARY_COLOR 0x000c0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_PREVIOUS 0x00100000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_TEXTURE0 0x00140000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_TEXTURE1 0x00180000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE3 (1 << 24)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA3 (1 << 25)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_SHIFT 26
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_MASK 0x1c000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_ZERO 0x04000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_CONSTANT 0x08000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_PRIMARY_COLOR 0x0c000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_PREVIOUS 0x10000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_TEXTURE0 0x14000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_TEXTURE1 0x18000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SHIFT 29
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_MASK 0xe0000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_IDENTITY 0x20000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SCALE2 0x40000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SCALE4 0x60000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_BIAS 0x80000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_BIAS_SCALE2 0xe0000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR 0x00000334
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_SHIFT 0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_MASK 0x000000ff
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_SHIFT 8
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_MASK 0x0000ff00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_SHIFT 16
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_MASK 0x00ff0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_SHIFT 24
|
||
|
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_MASK 0xff000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND 0x00000338
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_MASK_BIT_SHIFT 4
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_MASK_BIT_MASK 0x00000030
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_SHIFT 6
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_MASK 0x000000c0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_FLAT 0x00000040
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_GOURAUD 0x00000080
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_PHONG 0x000000c0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE (1 << 8)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE_SHIFT 12
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE_MASK 0x0000f000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_FOG_ENABLE (1 << 16)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_BLEND_ENABLE (1 << 20)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_SHIFT 24
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_MASK 0x0f000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_SHIFT 28
|
||
|
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_MASK 0xf0000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0 0x0000033c
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_SHIFT 0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_MASK 0x000000ff
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_SHIFT 8
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_MASK 0x00000f00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_ENABLE (1 << 12)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ORIGIN (1 << 13)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_ENABLE (1 << 14)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_SHIFT 16
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_MASK 0x000f0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_SHIFT 20
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_MASK 0x00300000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_BOTH 0x00000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_NONE 0x00100000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_CW 0x00200000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_CCW 0x00300000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_DITHER_ENABLE (1 << 22)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_PERSPECTIVE_ENABLE (1 << 23)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_WRITE (1 << 24)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE (1 << 25)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE (1 << 26)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE (1 << 27)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE (1 << 28)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE (1 << 29)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_SHIFT 30
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_MASK 0xc0000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL1 0x00000340
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_ENABLE (1 << 0)
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_SHIFT 4
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_MASK 0x000000f0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_SHIFT 8
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_MASK 0x0000ff00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_SHIFT 16
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_MASK 0x00ff0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_SHIFT 24
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_MASK 0xff000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL2 0x00000344
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_SHIFT 0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_MASK 0x0000000f
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_SHIFT 4
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_MASK 0x000000f0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_SHIFT 8
|
||
|
+#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_MASK 0x00000f00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR 0x00000348
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_B_SHIFT 0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_B_MASK 0x000000ff
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_G_SHIFT 8
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_G_MASK 0x0000ff00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_R_SHIFT 16
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_R_MASK 0x00ff0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_A_SHIFT 24
|
||
|
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_A_MASK 0xff000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SX(x) (0x00000400+((x)*40))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SX__SIZE 0x00000008
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SY(x) (0x00000404+((x)*40))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SY__SIZE 0x00000008
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SZ(x) (0x00000408+((x)*40))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SZ__SIZE 0x00000008
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_RHW(x) (0x0000040c+((x)*40))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_RHW__SIZE 0x00000008
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR(x) (0x00000410+((x)*40))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR__SIZE 0x00000008
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_SHIFT 0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_MASK 0x000000ff
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_SHIFT 8
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_MASK 0x0000ff00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_SHIFT 16
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_MASK 0x00ff0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_SHIFT 24
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_MASK 0xff000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR(x) (0x00000414+((x)*40))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR__SIZE 0x00000008
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_SHIFT 0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_MASK 0x000000ff
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_SHIFT 8
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_MASK 0x0000ff00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_SHIFT 16
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_MASK 0x00ff0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_SHIFT 24
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_MASK 0xff000000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU0(x) (0x00000418+((x)*40))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU0__SIZE 0x00000008
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV0(x) (0x0000041c+((x)*40))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV0__SIZE 0x00000008
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU1(x) (0x00000420+((x)*40))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU1__SIZE 0x00000008
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV1(x) (0x00000424+((x)*40))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV1__SIZE 0x00000008
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE(x) (0x00000540+((x)*4))
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE__SIZE 0x00000030
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I0_SHIFT 0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I0_MASK 0x0000000f
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I1_SHIFT 4
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I1_MASK 0x000000f0
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I2_SHIFT 8
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I2_MASK 0x00000f00
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I3_SHIFT 12
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I3_MASK 0x0000f000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I4_SHIFT 16
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I4_MASK 0x000f0000
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I5_SHIFT 20
|
||
|
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I5_MASK 0x00f00000
|
||
|
+
|
||
|
+
|
||
|
+#define NV10_MULTITEX_TRIANGLE 0x00000095
|
||
|
+
|
||
|
|
||
|
|
||
|
#define NV10TCL 0x00000056
|
||
|
@@ -1845,6 +2019,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV10TCL_TX_FORMAT_WRAP_T_CLAMP 0x50000000
|
||
|
#define NV10TCL_TX_ENABLE(x) (0x00000228+((x)*4))
|
||
|
#define NV10TCL_TX_ENABLE__SIZE 0x00000002
|
||
|
+#define NV10TCL_TX_ENABLE_CULL_SHIFT 0
|
||
|
+#define NV10TCL_TX_ENABLE_CULL_MASK 0x0000000f
|
||
|
+#define NV10TCL_TX_ENABLE_CULL_DISABLED 0x00000000
|
||
|
+#define NV10TCL_TX_ENABLE_CULL_TEST_ALL 0x00000003
|
||
|
+#define NV10TCL_TX_ENABLE_CULL_TEST_ALPHA 0x00000004
|
||
|
#define NV10TCL_TX_ENABLE_ANISOTROPY_SHIFT 4
|
||
|
#define NV10TCL_TX_ENABLE_ANISOTROPY_MASK 0x00000030
|
||
|
#define NV10TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT 14
|
||
|
@@ -1885,237 +2064,237 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV10TCL_RC_IN_ALPHA_D_INPUT_SHIFT 0
|
||
|
#define NV10TCL_RC_IN_ALPHA_D_INPUT_MASK 0x0000000f
|
||
|
#define NV10TCL_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV10TCL_RC_IN_ALPHA_D_INPUT_FOG 0x00000003
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0 0x00000008
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1 0x00000009
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE0 0x0000000c
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE1 0x0000000d
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3 0x0000000b
|
||
|
#define NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE (1 << 4)
|
||
|
#define NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000
|
||
|
#define NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010
|
||
|
#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SHIFT 5
|
||
|
#define NV10TCL_RC_IN_ALPHA_D_MAPPING_MASK 0x000000e0
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
|
||
|
-#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT 0x00000020
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL 0x00000040
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE 0x00000060
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL 0x00000080
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY 0x000000c0
|
||
|
+#define NV10TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE 0x000000e0
|
||
|
#define NV10TCL_RC_IN_ALPHA_C_INPUT_SHIFT 8
|
||
|
#define NV10TCL_RC_IN_ALPHA_C_INPUT_MASK 0x00000f00
|
||
|
#define NV10TCL_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV10TCL_RC_IN_ALPHA_C_INPUT_FOG 0x00000300
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0 0x00000800
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1 0x00000900
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE0 0x00000c00
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE1 0x00000d00
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3 0x00000b00
|
||
|
#define NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE (1 << 12)
|
||
|
#define NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000
|
||
|
#define NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000
|
||
|
#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SHIFT 13
|
||
|
#define NV10TCL_RC_IN_ALPHA_C_MAPPING_MASK 0x0000e000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT 0x00002000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL 0x00004000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE 0x00006000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL 0x00008000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY 0x0000c000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE 0x0000e000
|
||
|
#define NV10TCL_RC_IN_ALPHA_B_INPUT_SHIFT 16
|
||
|
#define NV10TCL_RC_IN_ALPHA_B_INPUT_MASK 0x000f0000
|
||
|
#define NV10TCL_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0 0x00010000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1 0x00020000
|
||
|
#define NV10TCL_RC_IN_ALPHA_B_INPUT_FOG 0x00030000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR_NV 0x00040000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR_NV 0x00050000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0_ARB 0x00080000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1_ARB 0x00090000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE0_NV 0x000c0000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE1_NV 0x000d0000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F_NV 0x000f0000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2_ARB 0x000a0000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3_ARB 0x000b0000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR 0x00040000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR 0x00050000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0 0x00080000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1 0x00090000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE0 0x000c0000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE1 0x000d0000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F 0x000f0000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2 0x000a0000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3 0x000b0000
|
||
|
#define NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE (1 << 20)
|
||
|
#define NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000
|
||
|
#define NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000
|
||
|
#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SHIFT 21
|
||
|
#define NV10TCL_RC_IN_ALPHA_B_MAPPING_MASK 0x00e00000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT 0x00200000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL 0x00400000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE 0x00600000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL 0x00800000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY 0x00c00000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE 0x00e00000
|
||
|
#define NV10TCL_RC_IN_ALPHA_A_INPUT_SHIFT 24
|
||
|
#define NV10TCL_RC_IN_ALPHA_A_INPUT_MASK 0x0f000000
|
||
|
#define NV10TCL_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0 0x01000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1 0x02000000
|
||
|
#define NV10TCL_RC_IN_ALPHA_A_INPUT_FOG 0x03000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR_NV 0x04000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR_NV 0x05000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0_ARB 0x08000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1_ARB 0x09000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE0_NV 0x0c000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE1_NV 0x0d000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F_NV 0x0f000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2_ARB 0x0a000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3_ARB 0x0b000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR 0x04000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR 0x05000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0 0x08000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1 0x09000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE0 0x0c000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE1 0x0d000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F 0x0f000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2 0x0a000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3 0x0b000000
|
||
|
#define NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE (1 << 28)
|
||
|
#define NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000
|
||
|
#define NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000
|
||
|
#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SHIFT 29
|
||
|
#define NV10TCL_RC_IN_ALPHA_A_MAPPING_MASK 0xe0000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
|
||
|
-#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT 0x20000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL 0x40000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE 0x60000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL 0x80000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY 0xc0000000
|
||
|
+#define NV10TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE 0xe0000000
|
||
|
#define NV10TCL_RC_IN_RGB(x) (0x00000268+((x)*4))
|
||
|
#define NV10TCL_RC_IN_RGB__SIZE 0x00000002
|
||
|
#define NV10TCL_RC_IN_RGB_D_INPUT_SHIFT 0
|
||
|
#define NV10TCL_RC_IN_RGB_D_INPUT_MASK 0x0000000f
|
||
|
#define NV10TCL_RC_IN_RGB_D_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV10TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV10TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV10TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV10TCL_RC_IN_RGB_D_INPUT_FOG 0x00000003
|
||
|
-#define NV10TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV10TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV10TCL_RC_IN_RGB_D_INPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV10TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV10TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE0 0x00000008
|
||
|
+#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE1 0x00000009
|
||
|
+#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE0 0x0000000c
|
||
|
+#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE1 0x0000000d
|
||
|
+#define NV10TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV10TCL_RC_IN_RGB_D_INPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE3 0x0000000b
|
||
|
#define NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE (1 << 4)
|
||
|
#define NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010
|
||
|
#define NV10TCL_RC_IN_RGB_D_MAPPING_SHIFT 5
|
||
|
#define NV10TCL_RC_IN_RGB_D_MAPPING_MASK 0x000000e0
|
||
|
-#define NV10TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
|
||
|
-#define NV10TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
|
||
|
-#define NV10TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
|
||
|
-#define NV10TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
|
||
|
-#define NV10TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
|
||
|
-#define NV10TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
|
||
|
-#define NV10TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
|
||
|
+#define NV10TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT 0x00000020
|
||
|
+#define NV10TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL 0x00000040
|
||
|
+#define NV10TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE 0x00000060
|
||
|
+#define NV10TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL 0x00000080
|
||
|
+#define NV10TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0
|
||
|
+#define NV10TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY 0x000000c0
|
||
|
+#define NV10TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE 0x000000e0
|
||
|
#define NV10TCL_RC_IN_RGB_C_INPUT_SHIFT 8
|
||
|
#define NV10TCL_RC_IN_RGB_C_INPUT_MASK 0x00000f00
|
||
|
#define NV10TCL_RC_IN_RGB_C_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV10TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV10TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV10TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV10TCL_RC_IN_RGB_C_INPUT_FOG 0x00000300
|
||
|
-#define NV10TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV10TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV10TCL_RC_IN_RGB_C_INPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV10TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV10TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE0 0x00000800
|
||
|
+#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE1 0x00000900
|
||
|
+#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE0 0x00000c00
|
||
|
+#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE1 0x00000d00
|
||
|
+#define NV10TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV10TCL_RC_IN_RGB_C_INPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE3 0x00000b00
|
||
|
#define NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE (1 << 12)
|
||
|
#define NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000
|
||
|
#define NV10TCL_RC_IN_RGB_C_MAPPING_SHIFT 13
|
||
|
#define NV10TCL_RC_IN_RGB_C_MAPPING_MASK 0x0000e000
|
||
|
-#define NV10TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
|
||
|
-#define NV10TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
|
||
|
-#define NV10TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
|
||
|
-#define NV10TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
|
||
|
-#define NV10TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
|
||
|
-#define NV10TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
|
||
|
-#define NV10TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
|
||
|
+#define NV10TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT 0x00002000
|
||
|
+#define NV10TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL 0x00004000
|
||
|
+#define NV10TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE 0x00006000
|
||
|
+#define NV10TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL 0x00008000
|
||
|
+#define NV10TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000
|
||
|
+#define NV10TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY 0x0000c000
|
||
|
+#define NV10TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE 0x0000e000
|
||
|
#define NV10TCL_RC_IN_RGB_B_INPUT_SHIFT 16
|
||
|
#define NV10TCL_RC_IN_RGB_B_INPUT_MASK 0x000f0000
|
||
|
#define NV10TCL_RC_IN_RGB_B_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0 0x00010000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1 0x00020000
|
||
|
#define NV10TCL_RC_IN_RGB_B_INPUT_FOG 0x00030000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR_NV 0x00040000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR_NV 0x00050000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE0_ARB 0x00080000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE1_ARB 0x00090000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE0_NV 0x000c0000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE1_NV 0x000d0000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_INPUT_E_TIMES_F_NV 0x000f0000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE2_ARB 0x000a0000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE3_ARB 0x000b0000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR 0x00040000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR 0x00050000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE0 0x00080000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE1 0x00090000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE0 0x000c0000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE1 0x000d0000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_INPUT_E_TIMES_F 0x000f0000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE2 0x000a0000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE3 0x000b0000
|
||
|
#define NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE (1 << 20)
|
||
|
#define NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000
|
||
|
#define NV10TCL_RC_IN_RGB_B_MAPPING_SHIFT 21
|
||
|
#define NV10TCL_RC_IN_RGB_B_MAPPING_MASK 0x00e00000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
|
||
|
-#define NV10TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT 0x00200000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL 0x00400000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE 0x00600000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL 0x00800000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY 0x00c00000
|
||
|
+#define NV10TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE 0x00e00000
|
||
|
#define NV10TCL_RC_IN_RGB_A_INPUT_SHIFT 24
|
||
|
#define NV10TCL_RC_IN_RGB_A_INPUT_MASK 0x0f000000
|
||
|
#define NV10TCL_RC_IN_RGB_A_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0 0x01000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1 0x02000000
|
||
|
#define NV10TCL_RC_IN_RGB_A_INPUT_FOG 0x03000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR_NV 0x04000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR_NV 0x05000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE0_ARB 0x08000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE1_ARB 0x09000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE0_NV 0x0c000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE1_NV 0x0d000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_INPUT_E_TIMES_F_NV 0x0f000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE2_ARB 0x0a000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE3_ARB 0x0b000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR 0x04000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR 0x05000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE0 0x08000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE1 0x09000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE0 0x0c000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE1 0x0d000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_INPUT_E_TIMES_F 0x0f000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE2 0x0a000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE3 0x0b000000
|
||
|
#define NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE (1 << 28)
|
||
|
#define NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000
|
||
|
#define NV10TCL_RC_IN_RGB_A_MAPPING_SHIFT 29
|
||
|
#define NV10TCL_RC_IN_RGB_A_MAPPING_MASK 0xe0000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
|
||
|
-#define NV10TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT 0x20000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL 0x40000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE 0x60000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL 0x80000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY 0xc0000000
|
||
|
+#define NV10TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE 0xe0000000
|
||
|
#define NV10TCL_RC_COLOR(x) (0x00000270+((x)*4))
|
||
|
#define NV10TCL_RC_COLOR__SIZE 0x00000002
|
||
|
#define NV10TCL_RC_COLOR_B_SHIFT 0
|
||
|
@@ -2131,352 +2310,351 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT 0
|
||
|
#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f
|
||
|
#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0 0x00000008
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1 0x00000009
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0 0x0000000c
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1 0x0000000d
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3 0x0000000b
|
||
|
#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4
|
||
|
#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0
|
||
|
#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV 0x00000010
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV 0x00000020
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0 0x00000010
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1 0x00000020
|
||
|
#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV 0x00000040
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV 0x00000050
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB 0x00000080
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB 0x00000090
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV 0x000000c0
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV 0x000000d0
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000000e0
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV 0x000000f0
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2_ARB 0x000000a0
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3_ARB 0x000000b0
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR 0x00000040
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR 0x00000050
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0 0x00000080
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1 0x00000090
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0 0x000000c0
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1 0x000000d0
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F 0x000000f0
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2 0x000000a0
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3 0x000000b0
|
||
|
#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8
|
||
|
#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00
|
||
|
#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0 0x00000800
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1 0x00000900
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0 0x00000c00
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1 0x00000d00
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3 0x00000b00
|
||
|
#define NV10TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12)
|
||
|
#define NV10TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13)
|
||
|
#define NV10TCL_RC_OUT_ALPHA_MUX_SUM (1 << 14)
|
||
|
#define NV10TCL_RC_OUT_ALPHA_BIAS (1 << 15)
|
||
|
#define NV10TCL_RC_OUT_ALPHA_BIAS_NONE 0x00000000
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00008000
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000
|
||
|
#define NV10TCL_RC_OUT_ALPHA_SCALE_SHIFT 17
|
||
|
#define NV10TCL_RC_OUT_ALPHA_SCALE_MASK 0x00000000
|
||
|
#define NV10TCL_RC_OUT_ALPHA_SCALE_NONE 0x00000000
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV 0x00020000
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV 0x00040000
|
||
|
-#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV 0x00060000
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO 0x00020000
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR 0x00040000
|
||
|
+#define NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF 0x00060000
|
||
|
#define NV10TCL_RC_OUT_RGB(x) (0x00000280+((x)*4))
|
||
|
#define NV10TCL_RC_OUT_RGB__SIZE 0x00000002
|
||
|
#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT 0
|
||
|
#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f
|
||
|
#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003
|
||
|
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0 0x00000008
|
||
|
+#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1 0x00000009
|
||
|
+#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0 0x0000000c
|
||
|
+#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1 0x0000000d
|
||
|
+#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3 0x0000000b
|
||
|
#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT 4
|
||
|
#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0
|
||
|
#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV 0x00000010
|
||
|
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV 0x00000020
|
||
|
+#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0 0x00000010
|
||
|
+#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1 0x00000020
|
||
|
#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030
|
||
|
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV 0x00000040
|
||
|
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV 0x00000050
|
||
|
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB 0x00000080
|
||
|
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB 0x00000090
|
||
|
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV 0x000000c0
|
||
|
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV 0x000000d0
|
||
|
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000000e0
|
||
|
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV 0x000000f0
|
||
|
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2_ARB 0x000000a0
|
||
|
-#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3_ARB 0x000000b0
|
||
|
+#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR 0x00000040
|
||
|
+#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR 0x00000050
|
||
|
+#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0 0x00000080
|
||
|
+#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1 0x00000090
|
||
|
+#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0 0x000000c0
|
||
|
+#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1 0x000000d0
|
||
|
+#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0
|
||
|
+#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F 0x000000f0
|
||
|
+#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2 0x000000a0
|
||
|
+#define NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3 0x000000b0
|
||
|
#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8
|
||
|
#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00
|
||
|
#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300
|
||
|
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0 0x00000800
|
||
|
+#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1 0x00000900
|
||
|
+#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0 0x00000c00
|
||
|
+#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1 0x00000d00
|
||
|
+#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3 0x00000b00
|
||
|
#define NV10TCL_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12)
|
||
|
#define NV10TCL_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13)
|
||
|
#define NV10TCL_RC_OUT_RGB_MUX_SUM (1 << 14)
|
||
|
#define NV10TCL_RC_OUT_RGB_BIAS (1 << 15)
|
||
|
#define NV10TCL_RC_OUT_RGB_BIAS_NONE 0x00000000
|
||
|
-#define NV10TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00008000
|
||
|
+#define NV10TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000
|
||
|
#define NV10TCL_RC_OUT_RGB_SCALE_SHIFT 17
|
||
|
#define NV10TCL_RC_OUT_RGB_SCALE_MASK 0x00000000
|
||
|
#define NV10TCL_RC_OUT_RGB_SCALE_NONE 0x00000000
|
||
|
-#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV 0x00020000
|
||
|
-#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV 0x00040000
|
||
|
-#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV 0x00060000
|
||
|
+#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO 0x00020000
|
||
|
+#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR 0x00040000
|
||
|
+#define NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF 0x00060000
|
||
|
#define NV10TCL_RC_OUT_RGB_OPERATION_SHIFT 27
|
||
|
#define NV10TCL_RC_OUT_RGB_OPERATION_MASK 0x38000000
|
||
|
#define NV10TCL_RC_FINAL0 0x00000288
|
||
|
#define NV10TCL_RC_FINAL0_D_INPUT_SHIFT 0
|
||
|
#define NV10TCL_RC_FINAL0_D_INPUT_MASK 0x0000000f
|
||
|
#define NV10TCL_RC_FINAL0_D_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV10TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV10TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV10TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV10TCL_RC_FINAL0_D_INPUT_FOG 0x00000003
|
||
|
-#define NV10TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV10TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV10TCL_RC_FINAL0_D_INPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV10TCL_RC_FINAL0_D_INPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV10TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV10TCL_RC_FINAL0_D_INPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV10TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV10TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE0 0x00000008
|
||
|
+#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE1 0x00000009
|
||
|
+#define NV10TCL_RC_FINAL0_D_INPUT_SPARE0 0x0000000c
|
||
|
+#define NV10TCL_RC_FINAL0_D_INPUT_SPARE1 0x0000000d
|
||
|
+#define NV10TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV10TCL_RC_FINAL0_D_INPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV10TCL_RC_FINAL0_D_INPUT_TEXTURE3 0x0000000b
|
||
|
#define NV10TCL_RC_FINAL0_D_COMPONENT_USAGE (1 << 4)
|
||
|
#define NV10TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV10TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010
|
||
|
#define NV10TCL_RC_FINAL0_D_MAPPING_SHIFT 5
|
||
|
#define NV10TCL_RC_FINAL0_D_MAPPING_MASK 0x000000e0
|
||
|
-#define NV10TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
|
||
|
-#define NV10TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
|
||
|
-#define NV10TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
|
||
|
-#define NV10TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
|
||
|
-#define NV10TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
|
||
|
-#define NV10TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
|
||
|
-#define NV10TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
|
||
|
+#define NV10TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT 0x00000020
|
||
|
+#define NV10TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL 0x00000040
|
||
|
+#define NV10TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE 0x00000060
|
||
|
+#define NV10TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL 0x00000080
|
||
|
+#define NV10TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0
|
||
|
+#define NV10TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY 0x000000c0
|
||
|
+#define NV10TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE 0x000000e0
|
||
|
#define NV10TCL_RC_FINAL0_C_INPUT_SHIFT 8
|
||
|
#define NV10TCL_RC_FINAL0_C_INPUT_MASK 0x00000f00
|
||
|
#define NV10TCL_RC_FINAL0_C_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV10TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV10TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV10TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV10TCL_RC_FINAL0_C_INPUT_FOG 0x00000300
|
||
|
-#define NV10TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV10TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV10TCL_RC_FINAL0_C_INPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV10TCL_RC_FINAL0_C_INPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV10TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV10TCL_RC_FINAL0_C_INPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV10TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV10TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE0 0x00000800
|
||
|
+#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE1 0x00000900
|
||
|
+#define NV10TCL_RC_FINAL0_C_INPUT_SPARE0 0x00000c00
|
||
|
+#define NV10TCL_RC_FINAL0_C_INPUT_SPARE1 0x00000d00
|
||
|
+#define NV10TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV10TCL_RC_FINAL0_C_INPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV10TCL_RC_FINAL0_C_INPUT_TEXTURE3 0x00000b00
|
||
|
#define NV10TCL_RC_FINAL0_C_COMPONENT_USAGE (1 << 12)
|
||
|
#define NV10TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV10TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000
|
||
|
#define NV10TCL_RC_FINAL0_C_MAPPING_SHIFT 13
|
||
|
#define NV10TCL_RC_FINAL0_C_MAPPING_MASK 0x0000e000
|
||
|
-#define NV10TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
|
||
|
-#define NV10TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
|
||
|
-#define NV10TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
|
||
|
-#define NV10TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
|
||
|
-#define NV10TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
|
||
|
-#define NV10TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
|
||
|
-#define NV10TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
|
||
|
+#define NV10TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT 0x00002000
|
||
|
+#define NV10TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL 0x00004000
|
||
|
+#define NV10TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE 0x00006000
|
||
|
+#define NV10TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL 0x00008000
|
||
|
+#define NV10TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000
|
||
|
+#define NV10TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY 0x0000c000
|
||
|
+#define NV10TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE 0x0000e000
|
||
|
#define NV10TCL_RC_FINAL0_B_INPUT_SHIFT 16
|
||
|
#define NV10TCL_RC_FINAL0_B_INPUT_MASK 0x000f0000
|
||
|
#define NV10TCL_RC_FINAL0_B_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
|
||
|
-#define NV10TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
|
||
|
+#define NV10TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0 0x00010000
|
||
|
+#define NV10TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1 0x00020000
|
||
|
#define NV10TCL_RC_FINAL0_B_INPUT_FOG 0x00030000
|
||
|
-#define NV10TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR_NV 0x00040000
|
||
|
-#define NV10TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR_NV 0x00050000
|
||
|
-#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE0_ARB 0x00080000
|
||
|
-#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE1_ARB 0x00090000
|
||
|
-#define NV10TCL_RC_FINAL0_B_INPUT_SPARE0_NV 0x000c0000
|
||
|
-#define NV10TCL_RC_FINAL0_B_INPUT_SPARE1_NV 0x000d0000
|
||
|
-#define NV10TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
|
||
|
-#define NV10TCL_RC_FINAL0_B_INPUT_E_TIMES_F_NV 0x000f0000
|
||
|
-#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE2_ARB 0x000a0000
|
||
|
-#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE3_ARB 0x000b0000
|
||
|
+#define NV10TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR 0x00040000
|
||
|
+#define NV10TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR 0x00050000
|
||
|
+#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE0 0x00080000
|
||
|
+#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE1 0x00090000
|
||
|
+#define NV10TCL_RC_FINAL0_B_INPUT_SPARE0 0x000c0000
|
||
|
+#define NV10TCL_RC_FINAL0_B_INPUT_SPARE1 0x000d0000
|
||
|
+#define NV10TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
|
||
|
+#define NV10TCL_RC_FINAL0_B_INPUT_E_TIMES_F 0x000f0000
|
||
|
+#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE2 0x000a0000
|
||
|
+#define NV10TCL_RC_FINAL0_B_INPUT_TEXTURE3 0x000b0000
|
||
|
#define NV10TCL_RC_FINAL0_B_COMPONENT_USAGE (1 << 20)
|
||
|
#define NV10TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV10TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000
|
||
|
#define NV10TCL_RC_FINAL0_B_MAPPING_SHIFT 21
|
||
|
#define NV10TCL_RC_FINAL0_B_MAPPING_MASK 0x00e00000
|
||
|
-#define NV10TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
|
||
|
-#define NV10TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
|
||
|
-#define NV10TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
|
||
|
-#define NV10TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
|
||
|
-#define NV10TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
|
||
|
-#define NV10TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
|
||
|
-#define NV10TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
|
||
|
+#define NV10TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT 0x00200000
|
||
|
+#define NV10TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL 0x00400000
|
||
|
+#define NV10TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE 0x00600000
|
||
|
+#define NV10TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL 0x00800000
|
||
|
+#define NV10TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000
|
||
|
+#define NV10TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY 0x00c00000
|
||
|
+#define NV10TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE 0x00e00000
|
||
|
#define NV10TCL_RC_FINAL0_A_INPUT_SHIFT 24
|
||
|
#define NV10TCL_RC_FINAL0_A_INPUT_MASK 0x0f000000
|
||
|
#define NV10TCL_RC_FINAL0_A_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0 0x01000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1 0x02000000
|
||
|
#define NV10TCL_RC_FINAL0_A_INPUT_FOG 0x03000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR_NV 0x04000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR_NV 0x05000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE0_ARB 0x08000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE1_ARB 0x09000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_INPUT_SPARE0_NV 0x0c000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_INPUT_SPARE1_NV 0x0d000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_INPUT_E_TIMES_F_NV 0x0f000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE2_ARB 0x0a000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE3_ARB 0x0b000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR 0x04000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR 0x05000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE0 0x08000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE1 0x09000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_INPUT_SPARE0 0x0c000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_INPUT_SPARE1 0x0d000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_INPUT_E_TIMES_F 0x0f000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE2 0x0a000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_INPUT_TEXTURE3 0x0b000000
|
||
|
#define NV10TCL_RC_FINAL0_A_COMPONENT_USAGE (1 << 28)
|
||
|
#define NV10TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV10TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000
|
||
|
#define NV10TCL_RC_FINAL0_A_MAPPING_SHIFT 29
|
||
|
#define NV10TCL_RC_FINAL0_A_MAPPING_MASK 0xe0000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
|
||
|
-#define NV10TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT 0x20000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL 0x40000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE 0x60000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL 0x80000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY 0xc0000000
|
||
|
+#define NV10TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE 0xe0000000
|
||
|
#define NV10TCL_RC_FINAL1 0x0000028c
|
||
|
#define NV10TCL_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7)
|
||
|
#define NV10TCL_RC_FINAL1_G_INPUT_SHIFT 8
|
||
|
#define NV10TCL_RC_FINAL1_G_INPUT_MASK 0x00000f00
|
||
|
#define NV10TCL_RC_FINAL1_G_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV10TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV10TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV10TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV10TCL_RC_FINAL1_G_INPUT_FOG 0x00000300
|
||
|
-#define NV10TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV10TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV10TCL_RC_FINAL1_G_INPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV10TCL_RC_FINAL1_G_INPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV10TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV10TCL_RC_FINAL1_G_INPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV10TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV10TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE0 0x00000800
|
||
|
+#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE1 0x00000900
|
||
|
+#define NV10TCL_RC_FINAL1_G_INPUT_SPARE0 0x00000c00
|
||
|
+#define NV10TCL_RC_FINAL1_G_INPUT_SPARE1 0x00000d00
|
||
|
+#define NV10TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV10TCL_RC_FINAL1_G_INPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV10TCL_RC_FINAL1_G_INPUT_TEXTURE3 0x00000b00
|
||
|
#define NV10TCL_RC_FINAL1_G_COMPONENT_USAGE (1 << 12)
|
||
|
#define NV10TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV10TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000
|
||
|
#define NV10TCL_RC_FINAL1_G_MAPPING_SHIFT 13
|
||
|
#define NV10TCL_RC_FINAL1_G_MAPPING_MASK 0x0000e000
|
||
|
-#define NV10TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT_NV 0x00002000
|
||
|
-#define NV10TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL_NV 0x00004000
|
||
|
-#define NV10TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE_NV 0x00006000
|
||
|
-#define NV10TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
|
||
|
-#define NV10TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
|
||
|
-#define NV10TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
|
||
|
-#define NV10TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE_NV 0x0000e000
|
||
|
+#define NV10TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT 0x00002000
|
||
|
+#define NV10TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL 0x00004000
|
||
|
+#define NV10TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE 0x00006000
|
||
|
+#define NV10TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL 0x00008000
|
||
|
+#define NV10TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE 0x0000a000
|
||
|
+#define NV10TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY 0x0000c000
|
||
|
+#define NV10TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE 0x0000e000
|
||
|
#define NV10TCL_RC_FINAL1_F_INPUT_SHIFT 16
|
||
|
#define NV10TCL_RC_FINAL1_F_INPUT_MASK 0x000f0000
|
||
|
#define NV10TCL_RC_FINAL1_F_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0_NV 0x00010000
|
||
|
-#define NV10TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1_NV 0x00020000
|
||
|
+#define NV10TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0 0x00010000
|
||
|
+#define NV10TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1 0x00020000
|
||
|
#define NV10TCL_RC_FINAL1_F_INPUT_FOG 0x00030000
|
||
|
-#define NV10TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR_NV 0x00040000
|
||
|
-#define NV10TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR_NV 0x00050000
|
||
|
-#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE0_ARB 0x00080000
|
||
|
-#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE1_ARB 0x00090000
|
||
|
-#define NV10TCL_RC_FINAL1_F_INPUT_SPARE0_NV 0x000c0000
|
||
|
-#define NV10TCL_RC_FINAL1_F_INPUT_SPARE1_NV 0x000d0000
|
||
|
-#define NV10TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
|
||
|
-#define NV10TCL_RC_FINAL1_F_INPUT_E_TIMES_F_NV 0x000f0000
|
||
|
-#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE2_ARB 0x000a0000
|
||
|
-#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE3_ARB 0x000b0000
|
||
|
+#define NV10TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR 0x00040000
|
||
|
+#define NV10TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR 0x00050000
|
||
|
+#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE0 0x00080000
|
||
|
+#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE1 0x00090000
|
||
|
+#define NV10TCL_RC_FINAL1_F_INPUT_SPARE0 0x000c0000
|
||
|
+#define NV10TCL_RC_FINAL1_F_INPUT_SPARE1 0x000d0000
|
||
|
+#define NV10TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
|
||
|
+#define NV10TCL_RC_FINAL1_F_INPUT_E_TIMES_F 0x000f0000
|
||
|
+#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE2 0x000a0000
|
||
|
+#define NV10TCL_RC_FINAL1_F_INPUT_TEXTURE3 0x000b0000
|
||
|
#define NV10TCL_RC_FINAL1_F_COMPONENT_USAGE (1 << 20)
|
||
|
#define NV10TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV10TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000
|
||
|
#define NV10TCL_RC_FINAL1_F_MAPPING_SHIFT 21
|
||
|
#define NV10TCL_RC_FINAL1_F_MAPPING_MASK 0x00e00000
|
||
|
-#define NV10TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT_NV 0x00200000
|
||
|
-#define NV10TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL_NV 0x00400000
|
||
|
-#define NV10TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE_NV 0x00600000
|
||
|
-#define NV10TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
|
||
|
-#define NV10TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
|
||
|
-#define NV10TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
|
||
|
-#define NV10TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE_NV 0x00e00000
|
||
|
+#define NV10TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT 0x00200000
|
||
|
+#define NV10TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL 0x00400000
|
||
|
+#define NV10TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE 0x00600000
|
||
|
+#define NV10TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL 0x00800000
|
||
|
+#define NV10TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE 0x00a00000
|
||
|
+#define NV10TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY 0x00c00000
|
||
|
+#define NV10TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE 0x00e00000
|
||
|
#define NV10TCL_RC_FINAL1_E_INPUT_SHIFT 24
|
||
|
#define NV10TCL_RC_FINAL1_E_INPUT_MASK 0x0f000000
|
||
|
#define NV10TCL_RC_FINAL1_E_INPUT_ZERO 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0_NV 0x01000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1_NV 0x02000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0 0x01000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1 0x02000000
|
||
|
#define NV10TCL_RC_FINAL1_E_INPUT_FOG 0x03000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR_NV 0x04000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR_NV 0x05000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE0_ARB 0x08000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE1_ARB 0x09000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_INPUT_SPARE0_NV 0x0c000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_INPUT_SPARE1_NV 0x0d000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_INPUT_E_TIMES_F_NV 0x0f000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE2_ARB 0x0a000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE3_ARB 0x0b000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR 0x04000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR 0x05000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE0 0x08000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE1 0x09000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_INPUT_SPARE0 0x0c000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_INPUT_SPARE1 0x0d000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_INPUT_E_TIMES_F 0x0f000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE2 0x0a000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_INPUT_TEXTURE3 0x0b000000
|
||
|
#define NV10TCL_RC_FINAL1_E_COMPONENT_USAGE (1 << 28)
|
||
|
#define NV10TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV10TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000
|
||
|
#define NV10TCL_RC_FINAL1_E_MAPPING_SHIFT 29
|
||
|
#define NV10TCL_RC_FINAL1_E_MAPPING_MASK 0xe0000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT_NV 0x20000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL_NV 0x40000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE_NV 0x60000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
|
||
|
-#define NV10TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE_NV 0xe0000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT 0x20000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL 0x40000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE 0x60000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL 0x80000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE 0xa0000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY 0xc0000000
|
||
|
+#define NV10TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE 0xe0000000
|
||
|
#define NV10TCL_LIGHT_MODEL 0x00000294
|
||
|
-#define NV10TCL_LIGHT_MODEL_COLOR_CONTROL (1 << 1)
|
||
|
+#define NV10TCL_LIGHT_MODEL_SEPARATE_SPECULAR (1 << 1)
|
||
|
#define NV10TCL_LIGHT_MODEL_LOCAL_VIEWER (1 << 16)
|
||
|
-#define NV10TCL_COLOR_MATERIAL_ENABLE 0x00000298
|
||
|
-#define NV10TCL_COLOR_MATERIAL_ENABLE_SPECULAR (1 << 0)
|
||
|
-#define NV10TCL_COLOR_MATERIAL_ENABLE_DIFFUSE (1 << 1)
|
||
|
-#define NV10TCL_COLOR_MATERIAL_ENABLE_AMBIENT (1 << 2)
|
||
|
-#define NV10TCL_COLOR_MATERIAL_ENABLE_EMISSION (1 << 3)
|
||
|
+#define NV10TCL_COLOR_MATERIAL 0x00000298
|
||
|
+#define NV10TCL_COLOR_MATERIAL_EMISSION (1 << 0)
|
||
|
+#define NV10TCL_COLOR_MATERIAL_AMBIENT (1 << 1)
|
||
|
+#define NV10TCL_COLOR_MATERIAL_DIFFUSE (1 << 2)
|
||
|
+#define NV10TCL_COLOR_MATERIAL_SPECULAR (1 << 3)
|
||
|
#define NV10TCL_FOG_MODE 0x0000029c
|
||
|
+#define NV10TCL_FOG_MODE_LINEAR 0x00002601
|
||
|
#define NV10TCL_FOG_MODE_EXP 0x00000800
|
||
|
-#define NV10TCL_FOG_MODE_EXP_2 0x00000802
|
||
|
+#define NV10TCL_FOG_MODE_EXP_ABS 0x00000802
|
||
|
#define NV10TCL_FOG_MODE_EXP2 0x00000803
|
||
|
-#define NV10TCL_FOG_MODE_LINEAR 0x00000804
|
||
|
-#define NV10TCL_FOG_MODE_LINEAR_2 0x00002601
|
||
|
-#define NV10TCL_FOG_COORD_DIST 0x000002a0
|
||
|
-#define NV10TCL_FOG_COORD_DIST_COORD_FALSE 0x00000000
|
||
|
-#define NV10TCL_FOG_COORD_DIST_COORD_FRAGMENT_DEPTH_DISTANCE_EYE_RADIAL_NV 0x00000001
|
||
|
-#define NV10TCL_FOG_COORD_DIST_COORD_FRAGMENT_DEPTH_DISTANCE_EYE_PLANE_ABSOLUTE_NV 0x00000002
|
||
|
-#define NV10TCL_FOG_COORD_DIST_COORD_FOG 0x00000003
|
||
|
+#define NV10TCL_FOG_COORD 0x000002a0
|
||
|
+#define NV10TCL_FOG_COORD_FOG 0x00000000
|
||
|
+#define NV10TCL_FOG_COORD_DIST_RADIAL 0x00000001
|
||
|
+#define NV10TCL_FOG_COORD_DIST_ORTHOGONAL 0x00000002
|
||
|
+#define NV10TCL_FOG_COORD_DIST_ORTHOGONAL_ABS 0x00000003
|
||
|
#define NV10TCL_FOG_ENABLE 0x000002a4
|
||
|
#define NV10TCL_FOG_COLOR 0x000002a8
|
||
|
#define NV10TCL_FOG_COLOR_R_SHIFT 0
|
||
|
@@ -2525,7 +2703,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV10TCL_ALPHA_FUNC_FUNC_EQUAL 0x00000202
|
||
|
#define NV10TCL_ALPHA_FUNC_FUNC_LEQUAL 0x00000203
|
||
|
#define NV10TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204
|
||
|
-#define NV10TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204
|
||
|
#define NV10TCL_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV10TCL_ALPHA_FUNC_FUNC_GEQUAL 0x00000206
|
||
|
#define NV10TCL_ALPHA_FUNC_FUNC_ALWAYS 0x00000207
|
||
|
@@ -2583,7 +2760,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV10TCL_DEPTH_FUNC_EQUAL 0x00000202
|
||
|
#define NV10TCL_DEPTH_FUNC_LEQUAL 0x00000203
|
||
|
#define NV10TCL_DEPTH_FUNC_GREATER 0x00000204
|
||
|
-#define NV10TCL_DEPTH_FUNC_GREATER 0x00000204
|
||
|
#define NV10TCL_DEPTH_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV10TCL_DEPTH_FUNC_GEQUAL 0x00000206
|
||
|
#define NV10TCL_DEPTH_FUNC_ALWAYS 0x00000207
|
||
|
@@ -2600,7 +2776,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV10TCL_STENCIL_FUNC_FUNC_EQUAL 0x00000202
|
||
|
#define NV10TCL_STENCIL_FUNC_FUNC_LEQUAL 0x00000203
|
||
|
#define NV10TCL_STENCIL_FUNC_FUNC_GREATER 0x00000204
|
||
|
-#define NV10TCL_STENCIL_FUNC_FUNC_GREATER 0x00000204
|
||
|
#define NV10TCL_STENCIL_FUNC_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV10TCL_STENCIL_FUNC_FUNC_GEQUAL 0x00000206
|
||
|
#define NV10TCL_STENCIL_FUNC_FUNC_ALWAYS 0x00000207
|
||
|
@@ -2657,20 +2832,60 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV10TCL_FRONT_FACE_CW 0x00000900
|
||
|
#define NV10TCL_FRONT_FACE_CCW 0x00000901
|
||
|
#define NV10TCL_NORMALIZE_ENABLE 0x000003a4
|
||
|
-#define NV10TCL_COLOR_MATERIAL_R 0x000003a8
|
||
|
-#define NV10TCL_COLOR_MATERIAL_G 0x000003ac
|
||
|
-#define NV10TCL_COLOR_MATERIAL_B 0x000003b0
|
||
|
-#define NV10TCL_COLOR_MATERIAL_A 0x000003b4
|
||
|
-#define NV10TCL_COLOR_CONTROL 0x000003b8
|
||
|
+#define NV10TCL_MATERIAL_FACTOR_R 0x000003a8
|
||
|
+#define NV10TCL_MATERIAL_FACTOR_G 0x000003ac
|
||
|
+#define NV10TCL_MATERIAL_FACTOR_B 0x000003b0
|
||
|
+#define NV10TCL_MATERIAL_FACTOR_A 0x000003b4
|
||
|
+#define NV10TCL_SEPARATE_SPECULAR_ENABLE 0x000003b8
|
||
|
#define NV10TCL_ENABLED_LIGHTS 0x000003bc
|
||
|
-#define NV10TCL_ENABLED_LIGHTS_LIGHT0 (1 << 0)
|
||
|
-#define NV10TCL_ENABLED_LIGHTS_LIGHT1 (1 << 2)
|
||
|
-#define NV10TCL_ENABLED_LIGHTS_LIGHT2 (1 << 4)
|
||
|
-#define NV10TCL_ENABLED_LIGHTS_LIGHT3 (1 << 6)
|
||
|
-#define NV10TCL_ENABLED_LIGHTS_LIGHT4 (1 << 8)
|
||
|
-#define NV10TCL_ENABLED_LIGHTS_LIGHT5 (1 << 10)
|
||
|
-#define NV10TCL_ENABLED_LIGHTS_LIGHT6 (1 << 12)
|
||
|
-#define NV10TCL_ENABLED_LIGHTS_LIGHT7 (1 << 14)
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_0_SHIFT 0
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_0_MASK 0x00000003
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_0_DISABLED 0x00000000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_0_NONPOSITIONAL 0x00000001
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_0_POSITIONAL 0x00000002
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_0_DIRECTIONAL 0x00000003
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_1_SHIFT 2
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_1_MASK 0x0000000c
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_1_DISABLED 0x00000000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_1_NONPOSITIONAL 0x00000004
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_1_POSITIONAL 0x00000008
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_1_DIRECTIONAL 0x0000000c
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_2_SHIFT 4
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_2_MASK 0x00000030
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_2_DISABLED 0x00000000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_2_NONPOSITIONAL 0x00000010
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_2_POSITIONAL 0x00000020
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_2_DIRECTIONAL 0x00000030
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_3_SHIFT 6
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_3_MASK 0x000000c0
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_3_DISABLED 0x00000000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_3_NONPOSITIONAL 0x00000040
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_3_POSITIONAL 0x00000080
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_3_DIRECTIONAL 0x000000c0
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_4_SHIFT 8
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_4_MASK 0x00000300
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_4_DISABLED 0x00000000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_4_NONPOSITIONAL 0x00000100
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_4_POSITIONAL 0x00000200
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_4_DIRECTIONAL 0x00000300
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_5_SHIFT 10
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_5_MASK 0x00000c00
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_5_DISABLED 0x00000000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_5_NONPOSITIONAL 0x00000400
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_5_POSITIONAL 0x00000800
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_5_DIRECTIONAL 0x00000c00
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_6_SHIFT 12
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_6_MASK 0x00003000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_6_DISABLED 0x00000000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_6_NONPOSITIONAL 0x00001000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_6_POSITIONAL 0x00002000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_6_DIRECTIONAL 0x00003000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_7_SHIFT 14
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_7_MASK 0x0000c000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_7_DISABLED 0x00000000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_7_NONPOSITIONAL 0x00004000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_7_POSITIONAL 0x00008000
|
||
|
+#define NV10TCL_ENABLED_LIGHTS_7_DIRECTIONAL 0x0000c000
|
||
|
#define NV10TCL_TX_GEN_S(x) (0x000003c0+((x)*16))
|
||
|
#define NV10TCL_TX_GEN_S__SIZE 0x00000002
|
||
|
#define NV10TCL_TX_GEN_S_FALSE 0x00000000
|
||
|
@@ -2735,35 +2950,35 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV10TCL_FOG_EQUATION_CONSTANT 0x00000680
|
||
|
#define NV10TCL_FOG_EQUATION_LINEAR 0x00000684
|
||
|
#define NV10TCL_FOG_EQUATION_QUADRATIC 0x00000688
|
||
|
-#define NV10TCL_FRONT_MATERIAL_SHININESS(x) (0x000006a0+((x)*4))
|
||
|
-#define NV10TCL_FRONT_MATERIAL_SHININESS__SIZE 0x00000006
|
||
|
-#define NV10TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000006c4
|
||
|
-#define NV10TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000006c8
|
||
|
-#define NV10TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000006cc
|
||
|
+#define NV10TCL_MATERIAL_SHININESS(x) (0x000006a0+((x)*4))
|
||
|
+#define NV10TCL_MATERIAL_SHININESS__SIZE 0x00000006
|
||
|
+#define NV10TCL_LIGHT_MODEL_AMBIENT_R 0x000006c4
|
||
|
+#define NV10TCL_LIGHT_MODEL_AMBIENT_G 0x000006c8
|
||
|
+#define NV10TCL_LIGHT_MODEL_AMBIENT_B 0x000006cc
|
||
|
#define NV10TCL_VIEWPORT_TRANSLATE_X 0x000006e8
|
||
|
#define NV10TCL_VIEWPORT_TRANSLATE_Y 0x000006ec
|
||
|
#define NV10TCL_VIEWPORT_TRANSLATE_Z 0x000006f0
|
||
|
#define NV10TCL_VIEWPORT_TRANSLATE_W 0x000006f4
|
||
|
#define NV10TCL_POINT_PARAMETER(x) (0x000006f8+((x)*4))
|
||
|
#define NV10TCL_POINT_PARAMETER__SIZE 0x00000008
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(x) (0x00000800+((x)*128))
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R__SIZE 0x00000008
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(x) (0x00000804+((x)*128))
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G__SIZE 0x00000008
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(x) (0x00000808+((x)*128))
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B__SIZE 0x00000008
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(x) (0x0000080c+((x)*128))
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R__SIZE 0x00000008
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(x) (0x00000810+((x)*128))
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G__SIZE 0x00000008
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(x) (0x00000814+((x)*128))
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B__SIZE 0x00000008
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(x) (0x00000818+((x)*128))
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R__SIZE 0x00000008
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(x) (0x0000081c+((x)*128))
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G__SIZE 0x00000008
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(x) (0x00000820+((x)*128))
|
||
|
-#define NV10TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B__SIZE 0x00000008
|
||
|
+#define NV10TCL_LIGHT_AMBIENT_R(x) (0x00000800+((x)*128))
|
||
|
+#define NV10TCL_LIGHT_AMBIENT_R__SIZE 0x00000008
|
||
|
+#define NV10TCL_LIGHT_AMBIENT_G(x) (0x00000804+((x)*128))
|
||
|
+#define NV10TCL_LIGHT_AMBIENT_G__SIZE 0x00000008
|
||
|
+#define NV10TCL_LIGHT_AMBIENT_B(x) (0x00000808+((x)*128))
|
||
|
+#define NV10TCL_LIGHT_AMBIENT_B__SIZE 0x00000008
|
||
|
+#define NV10TCL_LIGHT_DIFFUSE_R(x) (0x0000080c+((x)*128))
|
||
|
+#define NV10TCL_LIGHT_DIFFUSE_R__SIZE 0x00000008
|
||
|
+#define NV10TCL_LIGHT_DIFFUSE_G(x) (0x00000810+((x)*128))
|
||
|
+#define NV10TCL_LIGHT_DIFFUSE_G__SIZE 0x00000008
|
||
|
+#define NV10TCL_LIGHT_DIFFUSE_B(x) (0x00000814+((x)*128))
|
||
|
+#define NV10TCL_LIGHT_DIFFUSE_B__SIZE 0x00000008
|
||
|
+#define NV10TCL_LIGHT_SPECULAR_R(x) (0x00000818+((x)*128))
|
||
|
+#define NV10TCL_LIGHT_SPECULAR_R__SIZE 0x00000008
|
||
|
+#define NV10TCL_LIGHT_SPECULAR_G(x) (0x0000081c+((x)*128))
|
||
|
+#define NV10TCL_LIGHT_SPECULAR_G__SIZE 0x00000008
|
||
|
+#define NV10TCL_LIGHT_SPECULAR_B(x) (0x00000820+((x)*128))
|
||
|
+#define NV10TCL_LIGHT_SPECULAR_B__SIZE 0x00000008
|
||
|
#define NV10TCL_LIGHT_HALF_VECTOR_X(x) (0x00000828+((x)*128))
|
||
|
#define NV10TCL_LIGHT_HALF_VECTOR_X__SIZE 0x00000008
|
||
|
#define NV10TCL_LIGHT_HALF_VECTOR_Y(x) (0x0000082c+((x)*128))
|
||
|
@@ -2898,13 +3113,15 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV10TCL_VTXFMT__SIZE 0x00000008
|
||
|
#define NV10TCL_VTXFMT_TYPE_SHIFT 0
|
||
|
#define NV10TCL_VTXFMT_TYPE_MASK 0x0000000f
|
||
|
-#define NV10TCL_VTXFMT_TYPE_UBYTE 0x00000000
|
||
|
-#define NV10TCL_VTXFMT_TYPE_USHORT 0x00000001
|
||
|
+#define NV10TCL_VTXFMT_TYPE_BYTE_BGRA 0x00000000
|
||
|
+#define NV10TCL_VTXFMT_TYPE_SHORT 0x00000001
|
||
|
#define NV10TCL_VTXFMT_TYPE_FLOAT 0x00000002
|
||
|
+#define NV10TCL_VTXFMT_TYPE_BYTE_RGBA 0x00000004
|
||
|
#define NV10TCL_VTXFMT_FIELDS_SHIFT 4
|
||
|
#define NV10TCL_VTXFMT_FIELDS_MASK 0x000000f0
|
||
|
#define NV10TCL_VTXFMT_STRIDE_SHIFT 8
|
||
|
#define NV10TCL_VTXFMT_STRIDE_MASK 0x0000ff00
|
||
|
+#define NV10TCL_VTXFMT_POS_HOMOGENEOUS (1 << 24)
|
||
|
#define NV10TCL_VERTEX_ARRAY_OFFSET_POS 0x00000d00
|
||
|
#define NV10TCL_VERTEX_ARRAY_FORMAT_POS 0x00000d04
|
||
|
#define NV10TCL_VERTEX_ARRAY_FORMAT_POS_TYPE_SHIFT 0
|
||
|
@@ -3007,8 +3224,42 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV10TCL_VERTEX_ARRAY_DATA 0x00001800
|
||
|
|
||
|
|
||
|
-#define NV04_CONTEXT_COLOR_KEY 0x00000057
|
||
|
+#define NV11TCL 0x00000096
|
||
|
+
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_ENABLE 0x00000d40
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP 0x00000d44
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_CLEAR 0x00001500
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_AND 0x00001501
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_COPY 0x00001503
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_NOOP 0x00001505
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_XOR 0x00001506
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_OR 0x00001507
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_NOR 0x00001508
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_EQUIV 0x00001509
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_INVERT 0x0000150a
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_NAND 0x0000150e
|
||
|
+#define NV11TCL_COLOR_LOGIC_OP_OP_SET 0x0000150f
|
||
|
+
|
||
|
+
|
||
|
+#define NV17TCL 0x00000099
|
||
|
|
||
|
+#define NV17TCL_DMA_IN_MEMORY4 0x000001ac
|
||
|
+#define NV17TCL_DMA_IN_MEMORY5 0x000001b0
|
||
|
+#define NV17TCL_COLOR_MASK_ENABLE 0x000002bc
|
||
|
+#define NV17TCL_LMA_DEPTH_BUFFER_PITCH 0x00000d5c
|
||
|
+#define NV17TCL_LMA_DEPTH_BUFFER_OFFSET 0x00000d60
|
||
|
+#define NV17TCL_LMA_DEPTH_FILL_VALUE 0x00000d68
|
||
|
+#define NV17TCL_LMA_DEPTH_BUFFER_CLEAR 0x00000d6c
|
||
|
+#define NV17TCL_LMA_DEPTH_WINDOW_X 0x00001638
|
||
|
+#define NV17TCL_LMA_DEPTH_WINDOW_Y 0x0000163c
|
||
|
+#define NV17TCL_LMA_DEPTH_WINDOW_Z 0x00001640
|
||
|
+#define NV17TCL_LMA_DEPTH_WINDOW_W 0x00001644
|
||
|
+#define NV17TCL_LMA_DEPTH_ENABLE 0x00001658
|
||
|
|
||
|
|
||
|
#define NV03_CONTEXT_SURFACES_2D 0x00000058
|
||
|
@@ -3037,40 +3288,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV03_CONTEXT_SURFACES_3D_OFFSET_ZETA 0x00000308
|
||
|
|
||
|
|
||
|
-#define NV04_RENDER_SOLID_LINE 0x0000005c
|
||
|
-
|
||
|
-#define NV04_RENDER_SOLID_LINE_SURFACE 0x00000198
|
||
|
-
|
||
|
-
|
||
|
-#define NV04_RENDER_SOLID_TRIANGLE 0x0000005d
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV04_RENDER_SOLID_RECTANGLE 0x0000005e
|
||
|
-
|
||
|
-#define NV04_RENDER_SOLID_RECTANGLE_SURFACE 0x00000198
|
||
|
-
|
||
|
-
|
||
|
-#define NV04_IMAGE_BLIT 0x0000005f
|
||
|
-
|
||
|
-#define NV04_IMAGE_BLIT_NOP 0x00000100
|
||
|
-#define NV04_IMAGE_BLIT_NOTIFY 0x00000104
|
||
|
-#define NV04_IMAGE_BLIT_DMA_NOTIFY 0x00000180
|
||
|
-#define NV04_IMAGE_BLIT_COLOR_KEY 0x00000184
|
||
|
-#define NV04_IMAGE_BLIT_CLIP_RECTANGLE 0x00000188
|
||
|
-#define NV04_IMAGE_BLIT_PATTERN 0x0000018c
|
||
|
-#define NV04_IMAGE_BLIT_ROP 0x00000190
|
||
|
-#define NV04_IMAGE_BLIT_BETA4 0x00000198
|
||
|
-#define NV04_IMAGE_BLIT_SURFACE 0x0000019c
|
||
|
-#define NV04_IMAGE_BLIT_OPERATION 0x000002fc
|
||
|
-#define NV04_IMAGE_BLIT_OPERATION_SRCCOPY_AND 0x00000000
|
||
|
-#define NV04_IMAGE_BLIT_OPERATION_ROP_AND 0x00000001
|
||
|
-#define NV04_IMAGE_BLIT_OPERATION_BLEND_AND 0x00000002
|
||
|
-#define NV04_IMAGE_BLIT_OPERATION_SRCCOPY 0x00000003
|
||
|
-#define NV04_IMAGE_BLIT_OPERATION_SRCCOPY_PREMULT 0x00000004
|
||
|
-#define NV04_IMAGE_BLIT_OPERATION_BLEND_PREMULT 0x00000005
|
||
|
-
|
||
|
-
|
||
|
#define NV04_INDEXED_IMAGE_FROM_CPU 0x00000060
|
||
|
|
||
|
#define NV04_INDEXED_IMAGE_FROM_CPU_NOP 0x00000100
|
||
|
@@ -3078,76 +3295,27 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV04_INDEXED_IMAGE_FROM_CPU_PATCH 0x0000010c
|
||
|
#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_NOTIFY 0x00000180
|
||
|
#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_LUT 0x00000184
|
||
|
+#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_KEY 0x00000188
|
||
|
+#define NV04_INDEXED_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x0000018c
|
||
|
+#define NV04_INDEXED_IMAGE_FROM_CPU_PATTERN 0x00000190
|
||
|
+#define NV04_INDEXED_IMAGE_FROM_CPU_ROP 0x00000194
|
||
|
+#define NV04_INDEXED_IMAGE_FROM_CPU_BETA1 0x00000198
|
||
|
+#define NV04_INDEXED_IMAGE_FROM_CPU_BETA4 0x0000019c
|
||
|
+#define NV04_INDEXED_IMAGE_FROM_CPU_SURFACE 0x000001a0
|
||
|
+#define NV04_INDEXED_IMAGE_FROM_CPU_OPERATION 0x000003e4
|
||
|
#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_FORMAT 0x000003e8
|
||
|
#define NV04_INDEXED_IMAGE_FROM_CPU_INDEX_FORMAT 0x000003ec
|
||
|
#define NV04_INDEXED_IMAGE_FROM_CPU_LUT_OFFSET 0x000003f0
|
||
|
#define NV04_INDEXED_IMAGE_FROM_CPU_POINT 0x000003f4
|
||
|
#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_OUT 0x000003f8
|
||
|
#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_IN 0x000003fc
|
||
|
-#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR 0x00000400
|
||
|
-
|
||
|
-
|
||
|
-#define NV04_IMAGE_FROM_CPU 0x00000061
|
||
|
-
|
||
|
-#define NV04_IMAGE_FROM_CPU_BETA4 0x00000198
|
||
|
-#define NV04_IMAGE_FROM_CPU_SURFACE 0x0000019c
|
||
|
-
|
||
|
-
|
||
|
-#define NV10_CONTEXT_SURFACES_2D 0x00000062
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV05_SCALED_IMAGE_FROM_MEMORY 0x00000063
|
||
|
-
|
||
|
-#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION 0x000002fc
|
||
|
-#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER 0x00000000
|
||
|
-#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE 0x00000001
|
||
|
-#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE 0x00000002
|
||
|
-
|
||
|
-
|
||
|
-#define NV01_IMAGE_SRCCOPY_AND 0x00000064
|
||
|
-
|
||
|
-#define NV01_IMAGE_SRCCOPY_AND_NOTIFY 0x00000104
|
||
|
-#define NV01_IMAGE_SRCCOPY_AND_DMA_NOTIFY 0x00000180
|
||
|
-#define NV01_IMAGE_SRCCOPY_AND_IMAGE_OUTPUT 0x00000200
|
||
|
-#define NV01_IMAGE_SRCCOPY_AND_IMAGE_INPUT 0x00000204
|
||
|
+#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR(x) (0x00000400+((x)*4))
|
||
|
+#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR__SIZE 0x00000700
|
||
|
|
||
|
|
||
|
#define NV05_INDEXED_IMAGE_FROM_CPU 0x00000064
|
||
|
|
||
|
-#define NV05_INDEXED_IMAGE_FROM_CPU_COLOR_KEY 0x00000188
|
||
|
-#define NV05_INDEXED_IMAGE_FROM_CPU_CLIP_RECTANGLE 0x0000018c
|
||
|
-#define NV05_INDEXED_IMAGE_FROM_CPU_PATTERN 0x00000190
|
||
|
-#define NV05_INDEXED_IMAGE_FROM_CPU_ROP 0x00000194
|
||
|
-#define NV05_INDEXED_IMAGE_FROM_CPU_BETA1 0x00000198
|
||
|
-#define NV05_INDEXED_IMAGE_FROM_CPU_BETA4 0x0000019c
|
||
|
-#define NV05_INDEXED_IMAGE_FROM_CPU_SURFACE 0x000001a0
|
||
|
#define NV05_INDEXED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000003e0
|
||
|
-#define NV05_INDEXED_IMAGE_FROM_CPU_OPERATION 0x000003e4
|
||
|
-#define NV05_INDEXED_IMAGE_FROM_CPU_INDICES 0x00000400
|
||
|
-
|
||
|
-
|
||
|
-#define NV05_IMAGE_FROM_CPU 0x00000065
|
||
|
-
|
||
|
-#define NV05_IMAGE_FROM_CPU_BETA4 0x00000198
|
||
|
-#define NV05_IMAGE_FROM_CPU_SURFACE 0x0000019c
|
||
|
-
|
||
|
-
|
||
|
-#define NV05_STRETCHED_IMAGE_FROM_CPU 0x00000066
|
||
|
-
|
||
|
-#define NV05_STRETCHED_IMAGE_FROM_CPU_BETA4 0x00000194
|
||
|
-#define NV05_STRETCHED_IMAGE_FROM_CPU_SURFACE 0x00000198
|
||
|
-#define NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8
|
||
|
-
|
||
|
-
|
||
|
-#define NV04_IMAGE_BLEND_PREMULT 0x00000067
|
||
|
-
|
||
|
-#define NV04_IMAGE_BLEND_PREMULT_NOP 0x00000100
|
||
|
-#define NV04_IMAGE_BLEND_PREMULT_NOTIFY 0x00000104
|
||
|
-#define NV04_IMAGE_BLEND_PREMULT_DMA_NOTIFY 0x00000180
|
||
|
-#define NV04_IMAGE_BLEND_PREMULT_IMAGE_OUTPUT 0x00000200
|
||
|
-#define NV04_IMAGE_BLEND_PREMULT_BETA_INPUT 0x00000204
|
||
|
-#define NV04_IMAGE_BLEND_PREMULT_IMAGE_INPUT 0x00000208
|
||
|
|
||
|
|
||
|
#define NV03_CHANNEL_PIO 0x0000006a
|
||
|
@@ -3167,88 +3335,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV04_BETA_SOLID_BETA_FACTOR 0x00000300
|
||
|
|
||
|
|
||
|
-#define NV04_STRETCHED_IMAGE_FROM_CPU 0x00000076
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY 0x00000077
|
||
|
-
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_NOP 0x00000100
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_NOTIFY 0x00000104
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY 0x00000180
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE 0x00000184
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_PATTERN 0x00000188
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_ROP 0x0000018c
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_BETA1 0x00000190
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_BETA4 0x00000194
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE 0x00000198
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION 0x000002fc
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER 0x00000000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE 0x00000001
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE 0x00000002
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT 0x00000300
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5 0x00000001
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5 0x00000002
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8 0x00000003
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8 0x00000004
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_V8YB8U8YA8 0x00000005
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_YB8V8YA8U8 0x00000006
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5 0x00000007
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8 0x00000008
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_AY8 0x00000009
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION 0x00000304
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_AND 0x00000000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_ROP_AND 0x00000001
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_AND 0x00000002
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY 0x00000003
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_PREMULT 0x00000004
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_PREMULT 0x00000005
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT 0x00000308
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_SHIFT 0
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_MASK 0x0000ffff
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT 16
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_MASK 0xffff0000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE 0x0000030c
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_SHIFT 0
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_MASK 0x0000ffff
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT 16
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_MASK 0xffff0000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POINT 0x00000310
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X_SHIFT 0
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X_MASK 0x0000ffff
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT 16
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_MASK 0xffff0000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE 0x00000314
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W_SHIFT 0
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W_MASK 0x0000ffff
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT 16
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_MASK 0xffff0000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_DU_DX 0x00000318
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_DV_DY 0x0000031c
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE 0x00000400
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_W_SHIFT 0
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_W_MASK 0x0000ffff
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT 16
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_SIZE_H_MASK 0xffff0000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT 0x00000404
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_SHIFT 0
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_MASK 0x0000ffff
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_SHIFT 16
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_MASK 0x00ff0000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER 0x00010000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CORNER 0x00020000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_SHIFT 24
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_MASK 0xff000000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE 0x00000000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_BILINEAR 0x01000000
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_ADDRESS 0x00000408
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_POINT 0x0000040c
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_X_SHIFT 0
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_X_MASK 0x0000ffff
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_Y_SHIFT 16
|
||
|
-#define NV04_SCALED_IMAGE_FROM_MEMORY_POINT_Y_MASK 0xffff0000
|
||
|
-
|
||
|
-
|
||
|
#define NV10_TEXTURE_FROM_CPU 0x0000007b
|
||
|
|
||
|
#define NV10_TEXTURE_FROM_CPU_NOP 0x00000100
|
||
|
@@ -3282,57 +3368,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV10_TEXTURE_FROM_CPU_COLOR__SIZE 0x00000700
|
||
|
|
||
|
|
||
|
-#define NV10_VIDEO_DISPLAY 0x0000007c
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV10_DVD_SUBPICTURE 0x00000088
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV10_SCALED_IMAGE_FROM_MEMORY 0x00000089
|
||
|
-
|
||
|
-#define NV10_SCALED_IMAGE_FROM_MEMORY_WAIT_FOR_IDLE 0x00000108
|
||
|
-
|
||
|
-
|
||
|
-#define NV10_IMAGE_FROM_CPU 0x0000008a
|
||
|
-
|
||
|
-#define NV10_IMAGE_FROM_CPU_COLOR_CONVERSION 0x000002f8
|
||
|
-
|
||
|
-
|
||
|
-#define NV10_CONTEXT_SURFACES_3D 0x00000093
|
||
|
-
|
||
|
+#define NV30_TEXTURE_FROM_CPU 0x0000037b
|
||
|
|
||
|
|
||
|
-#define NV10_DX5_TEXTURED_TRIANGLE 0x00000094
|
||
|
|
||
|
+#define NV40_TEXTURE_FROM_CPU 0x0000307b
|
||
|
|
||
|
|
||
|
-#define NV10_DX6_MULTITEX_TRIANGLE 0x00000095
|
||
|
|
||
|
+#define NV10_VIDEO_DISPLAY 0x0000007c
|
||
|
|
||
|
|
||
|
-#define NV11TCL 0x00000096
|
||
|
-
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_ENABLE 0x00000d40
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP 0x00000d44
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_CLEAR 0x00001500
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_AND 0x00001501
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_AND_REVERSE 0x00001502
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_COPY 0x00001503
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_AND_INVERTED 0x00001504
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_NOOP 0x00001505
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_XOR 0x00001506
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_OR 0x00001507
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_NOR 0x00001508
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_EQUIV 0x00001509
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_INVERT 0x0000150a
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_OR_REVERSE 0x0000150b
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_COPY_INVERTED 0x0000150c
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_OR_INVERTED 0x0000150d
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_NAND 0x0000150e
|
||
|
-#define NV11TCL_COLOR_LOGIC_OP_OP_SET 0x0000150f
|
||
|
-
|
||
|
|
||
|
#define NV20TCL 0x00000097
|
||
|
|
||
|
@@ -3383,337 +3429,384 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_RC_IN_ALPHA_D_INPUT_SHIFT 0
|
||
|
#define NV20TCL_RC_IN_ALPHA_D_INPUT_MASK 0x0000000f
|
||
|
#define NV20TCL_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV20TCL_RC_IN_ALPHA_D_INPUT_FOG 0x00000003
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0 0x00000008
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1 0x00000009
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE0 0x0000000c
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE1 0x0000000d
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3 0x0000000b
|
||
|
#define NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE (1 << 4)
|
||
|
#define NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000
|
||
|
#define NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010
|
||
|
#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SHIFT 5
|
||
|
#define NV20TCL_RC_IN_ALPHA_D_MAPPING_MASK 0x000000e0
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
|
||
|
-#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT 0x00000020
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL 0x00000040
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE 0x00000060
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL 0x00000080
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY 0x000000c0
|
||
|
+#define NV20TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE 0x000000e0
|
||
|
#define NV20TCL_RC_IN_ALPHA_C_INPUT_SHIFT 8
|
||
|
#define NV20TCL_RC_IN_ALPHA_C_INPUT_MASK 0x00000f00
|
||
|
#define NV20TCL_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV20TCL_RC_IN_ALPHA_C_INPUT_FOG 0x00000300
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0 0x00000800
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1 0x00000900
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE0 0x00000c00
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE1 0x00000d00
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3 0x00000b00
|
||
|
#define NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE (1 << 12)
|
||
|
#define NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000
|
||
|
#define NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000
|
||
|
#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SHIFT 13
|
||
|
#define NV20TCL_RC_IN_ALPHA_C_MAPPING_MASK 0x0000e000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT 0x00002000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL 0x00004000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE 0x00006000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL 0x00008000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY 0x0000c000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE 0x0000e000
|
||
|
#define NV20TCL_RC_IN_ALPHA_B_INPUT_SHIFT 16
|
||
|
#define NV20TCL_RC_IN_ALPHA_B_INPUT_MASK 0x000f0000
|
||
|
#define NV20TCL_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0 0x00010000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1 0x00020000
|
||
|
#define NV20TCL_RC_IN_ALPHA_B_INPUT_FOG 0x00030000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR_NV 0x00040000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR_NV 0x00050000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0_ARB 0x00080000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1_ARB 0x00090000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE0_NV 0x000c0000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE1_NV 0x000d0000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F_NV 0x000f0000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2_ARB 0x000a0000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3_ARB 0x000b0000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR 0x00040000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR 0x00050000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0 0x00080000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1 0x00090000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE0 0x000c0000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE1 0x000d0000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F 0x000f0000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2 0x000a0000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3 0x000b0000
|
||
|
#define NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE (1 << 20)
|
||
|
#define NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000
|
||
|
#define NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000
|
||
|
#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SHIFT 21
|
||
|
#define NV20TCL_RC_IN_ALPHA_B_MAPPING_MASK 0x00e00000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT 0x00200000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL 0x00400000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE 0x00600000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL 0x00800000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY 0x00c00000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE 0x00e00000
|
||
|
#define NV20TCL_RC_IN_ALPHA_A_INPUT_SHIFT 24
|
||
|
#define NV20TCL_RC_IN_ALPHA_A_INPUT_MASK 0x0f000000
|
||
|
#define NV20TCL_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0 0x01000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1 0x02000000
|
||
|
#define NV20TCL_RC_IN_ALPHA_A_INPUT_FOG 0x03000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR_NV 0x04000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR_NV 0x05000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0_ARB 0x08000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1_ARB 0x09000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE0_NV 0x0c000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE1_NV 0x0d000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F_NV 0x0f000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2_ARB 0x0a000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3_ARB 0x0b000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR 0x04000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR 0x05000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0 0x08000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1 0x09000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE0 0x0c000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE1 0x0d000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F 0x0f000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2 0x0a000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3 0x0b000000
|
||
|
#define NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE (1 << 28)
|
||
|
#define NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000
|
||
|
#define NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000
|
||
|
#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SHIFT 29
|
||
|
#define NV20TCL_RC_IN_ALPHA_A_MAPPING_MASK 0xe0000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
|
||
|
-#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT 0x20000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL 0x40000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE 0x60000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL 0x80000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY 0xc0000000
|
||
|
+#define NV20TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE 0xe0000000
|
||
|
#define NV20TCL_RC_FINAL0 0x00000288
|
||
|
#define NV20TCL_RC_FINAL0_D_INPUT_SHIFT 0
|
||
|
#define NV20TCL_RC_FINAL0_D_INPUT_MASK 0x0000000f
|
||
|
#define NV20TCL_RC_FINAL0_D_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV20TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV20TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV20TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV20TCL_RC_FINAL0_D_INPUT_FOG 0x00000003
|
||
|
-#define NV20TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV20TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV20TCL_RC_FINAL0_D_INPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV20TCL_RC_FINAL0_D_INPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV20TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV20TCL_RC_FINAL0_D_INPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV20TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV20TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE0 0x00000008
|
||
|
+#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE1 0x00000009
|
||
|
+#define NV20TCL_RC_FINAL0_D_INPUT_SPARE0 0x0000000c
|
||
|
+#define NV20TCL_RC_FINAL0_D_INPUT_SPARE1 0x0000000d
|
||
|
+#define NV20TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV20TCL_RC_FINAL0_D_INPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV20TCL_RC_FINAL0_D_INPUT_TEXTURE3 0x0000000b
|
||
|
#define NV20TCL_RC_FINAL0_D_COMPONENT_USAGE (1 << 4)
|
||
|
#define NV20TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV20TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010
|
||
|
#define NV20TCL_RC_FINAL0_D_MAPPING_SHIFT 5
|
||
|
#define NV20TCL_RC_FINAL0_D_MAPPING_MASK 0x000000e0
|
||
|
-#define NV20TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
|
||
|
-#define NV20TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
|
||
|
-#define NV20TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
|
||
|
-#define NV20TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
|
||
|
-#define NV20TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
|
||
|
-#define NV20TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
|
||
|
-#define NV20TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
|
||
|
+#define NV20TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT 0x00000020
|
||
|
+#define NV20TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL 0x00000040
|
||
|
+#define NV20TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE 0x00000060
|
||
|
+#define NV20TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL 0x00000080
|
||
|
+#define NV20TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0
|
||
|
+#define NV20TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY 0x000000c0
|
||
|
+#define NV20TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE 0x000000e0
|
||
|
#define NV20TCL_RC_FINAL0_C_INPUT_SHIFT 8
|
||
|
#define NV20TCL_RC_FINAL0_C_INPUT_MASK 0x00000f00
|
||
|
#define NV20TCL_RC_FINAL0_C_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV20TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV20TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV20TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV20TCL_RC_FINAL0_C_INPUT_FOG 0x00000300
|
||
|
-#define NV20TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV20TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV20TCL_RC_FINAL0_C_INPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV20TCL_RC_FINAL0_C_INPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV20TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV20TCL_RC_FINAL0_C_INPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV20TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV20TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE0 0x00000800
|
||
|
+#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE1 0x00000900
|
||
|
+#define NV20TCL_RC_FINAL0_C_INPUT_SPARE0 0x00000c00
|
||
|
+#define NV20TCL_RC_FINAL0_C_INPUT_SPARE1 0x00000d00
|
||
|
+#define NV20TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV20TCL_RC_FINAL0_C_INPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV20TCL_RC_FINAL0_C_INPUT_TEXTURE3 0x00000b00
|
||
|
#define NV20TCL_RC_FINAL0_C_COMPONENT_USAGE (1 << 12)
|
||
|
#define NV20TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV20TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000
|
||
|
#define NV20TCL_RC_FINAL0_C_MAPPING_SHIFT 13
|
||
|
#define NV20TCL_RC_FINAL0_C_MAPPING_MASK 0x0000e000
|
||
|
-#define NV20TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
|
||
|
-#define NV20TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
|
||
|
-#define NV20TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
|
||
|
-#define NV20TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
|
||
|
-#define NV20TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
|
||
|
-#define NV20TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
|
||
|
-#define NV20TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
|
||
|
+#define NV20TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT 0x00002000
|
||
|
+#define NV20TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL 0x00004000
|
||
|
+#define NV20TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE 0x00006000
|
||
|
+#define NV20TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL 0x00008000
|
||
|
+#define NV20TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000
|
||
|
+#define NV20TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY 0x0000c000
|
||
|
+#define NV20TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE 0x0000e000
|
||
|
#define NV20TCL_RC_FINAL0_B_INPUT_SHIFT 16
|
||
|
#define NV20TCL_RC_FINAL0_B_INPUT_MASK 0x000f0000
|
||
|
#define NV20TCL_RC_FINAL0_B_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
|
||
|
-#define NV20TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
|
||
|
+#define NV20TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0 0x00010000
|
||
|
+#define NV20TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1 0x00020000
|
||
|
#define NV20TCL_RC_FINAL0_B_INPUT_FOG 0x00030000
|
||
|
-#define NV20TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR_NV 0x00040000
|
||
|
-#define NV20TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR_NV 0x00050000
|
||
|
-#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE0_ARB 0x00080000
|
||
|
-#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE1_ARB 0x00090000
|
||
|
-#define NV20TCL_RC_FINAL0_B_INPUT_SPARE0_NV 0x000c0000
|
||
|
-#define NV20TCL_RC_FINAL0_B_INPUT_SPARE1_NV 0x000d0000
|
||
|
-#define NV20TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
|
||
|
-#define NV20TCL_RC_FINAL0_B_INPUT_E_TIMES_F_NV 0x000f0000
|
||
|
-#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE2_ARB 0x000a0000
|
||
|
-#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE3_ARB 0x000b0000
|
||
|
+#define NV20TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR 0x00040000
|
||
|
+#define NV20TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR 0x00050000
|
||
|
+#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE0 0x00080000
|
||
|
+#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE1 0x00090000
|
||
|
+#define NV20TCL_RC_FINAL0_B_INPUT_SPARE0 0x000c0000
|
||
|
+#define NV20TCL_RC_FINAL0_B_INPUT_SPARE1 0x000d0000
|
||
|
+#define NV20TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
|
||
|
+#define NV20TCL_RC_FINAL0_B_INPUT_E_TIMES_F 0x000f0000
|
||
|
+#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE2 0x000a0000
|
||
|
+#define NV20TCL_RC_FINAL0_B_INPUT_TEXTURE3 0x000b0000
|
||
|
#define NV20TCL_RC_FINAL0_B_COMPONENT_USAGE (1 << 20)
|
||
|
#define NV20TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV20TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000
|
||
|
#define NV20TCL_RC_FINAL0_B_MAPPING_SHIFT 21
|
||
|
#define NV20TCL_RC_FINAL0_B_MAPPING_MASK 0x00e00000
|
||
|
-#define NV20TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
|
||
|
-#define NV20TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
|
||
|
-#define NV20TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
|
||
|
-#define NV20TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
|
||
|
-#define NV20TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
|
||
|
-#define NV20TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
|
||
|
-#define NV20TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
|
||
|
+#define NV20TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT 0x00200000
|
||
|
+#define NV20TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL 0x00400000
|
||
|
+#define NV20TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE 0x00600000
|
||
|
+#define NV20TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL 0x00800000
|
||
|
+#define NV20TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000
|
||
|
+#define NV20TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY 0x00c00000
|
||
|
+#define NV20TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE 0x00e00000
|
||
|
#define NV20TCL_RC_FINAL0_A_INPUT_SHIFT 24
|
||
|
#define NV20TCL_RC_FINAL0_A_INPUT_MASK 0x0f000000
|
||
|
#define NV20TCL_RC_FINAL0_A_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0 0x01000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1 0x02000000
|
||
|
#define NV20TCL_RC_FINAL0_A_INPUT_FOG 0x03000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR_NV 0x04000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR_NV 0x05000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE0_ARB 0x08000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE1_ARB 0x09000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_INPUT_SPARE0_NV 0x0c000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_INPUT_SPARE1_NV 0x0d000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_INPUT_E_TIMES_F_NV 0x0f000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE2_ARB 0x0a000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE3_ARB 0x0b000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR 0x04000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR 0x05000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE0 0x08000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE1 0x09000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_INPUT_SPARE0 0x0c000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_INPUT_SPARE1 0x0d000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_INPUT_E_TIMES_F 0x0f000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE2 0x0a000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_INPUT_TEXTURE3 0x0b000000
|
||
|
#define NV20TCL_RC_FINAL0_A_COMPONENT_USAGE (1 << 28)
|
||
|
#define NV20TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV20TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000
|
||
|
#define NV20TCL_RC_FINAL0_A_MAPPING_SHIFT 29
|
||
|
#define NV20TCL_RC_FINAL0_A_MAPPING_MASK 0xe0000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
|
||
|
-#define NV20TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT 0x20000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL 0x40000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE 0x60000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL 0x80000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY 0xc0000000
|
||
|
+#define NV20TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE 0xe0000000
|
||
|
#define NV20TCL_RC_FINAL1 0x0000028c
|
||
|
#define NV20TCL_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7)
|
||
|
#define NV20TCL_RC_FINAL1_G_INPUT_SHIFT 8
|
||
|
#define NV20TCL_RC_FINAL1_G_INPUT_MASK 0x00000f00
|
||
|
#define NV20TCL_RC_FINAL1_G_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV20TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV20TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV20TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV20TCL_RC_FINAL1_G_INPUT_FOG 0x00000300
|
||
|
-#define NV20TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV20TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV20TCL_RC_FINAL1_G_INPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV20TCL_RC_FINAL1_G_INPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV20TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV20TCL_RC_FINAL1_G_INPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV20TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV20TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE0 0x00000800
|
||
|
+#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE1 0x00000900
|
||
|
+#define NV20TCL_RC_FINAL1_G_INPUT_SPARE0 0x00000c00
|
||
|
+#define NV20TCL_RC_FINAL1_G_INPUT_SPARE1 0x00000d00
|
||
|
+#define NV20TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV20TCL_RC_FINAL1_G_INPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV20TCL_RC_FINAL1_G_INPUT_TEXTURE3 0x00000b00
|
||
|
#define NV20TCL_RC_FINAL1_G_COMPONENT_USAGE (1 << 12)
|
||
|
#define NV20TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV20TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000
|
||
|
#define NV20TCL_RC_FINAL1_G_MAPPING_SHIFT 13
|
||
|
#define NV20TCL_RC_FINAL1_G_MAPPING_MASK 0x0000e000
|
||
|
-#define NV20TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT_NV 0x00002000
|
||
|
-#define NV20TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL_NV 0x00004000
|
||
|
-#define NV20TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE_NV 0x00006000
|
||
|
-#define NV20TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
|
||
|
-#define NV20TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
|
||
|
-#define NV20TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
|
||
|
-#define NV20TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE_NV 0x0000e000
|
||
|
+#define NV20TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT 0x00002000
|
||
|
+#define NV20TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL 0x00004000
|
||
|
+#define NV20TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE 0x00006000
|
||
|
+#define NV20TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL 0x00008000
|
||
|
+#define NV20TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE 0x0000a000
|
||
|
+#define NV20TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY 0x0000c000
|
||
|
+#define NV20TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE 0x0000e000
|
||
|
#define NV20TCL_RC_FINAL1_F_INPUT_SHIFT 16
|
||
|
#define NV20TCL_RC_FINAL1_F_INPUT_MASK 0x000f0000
|
||
|
#define NV20TCL_RC_FINAL1_F_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0_NV 0x00010000
|
||
|
-#define NV20TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1_NV 0x00020000
|
||
|
+#define NV20TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0 0x00010000
|
||
|
+#define NV20TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1 0x00020000
|
||
|
#define NV20TCL_RC_FINAL1_F_INPUT_FOG 0x00030000
|
||
|
-#define NV20TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR_NV 0x00040000
|
||
|
-#define NV20TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR_NV 0x00050000
|
||
|
-#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE0_ARB 0x00080000
|
||
|
-#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE1_ARB 0x00090000
|
||
|
-#define NV20TCL_RC_FINAL1_F_INPUT_SPARE0_NV 0x000c0000
|
||
|
-#define NV20TCL_RC_FINAL1_F_INPUT_SPARE1_NV 0x000d0000
|
||
|
-#define NV20TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
|
||
|
-#define NV20TCL_RC_FINAL1_F_INPUT_E_TIMES_F_NV 0x000f0000
|
||
|
-#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE2_ARB 0x000a0000
|
||
|
-#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE3_ARB 0x000b0000
|
||
|
+#define NV20TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR 0x00040000
|
||
|
+#define NV20TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR 0x00050000
|
||
|
+#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE0 0x00080000
|
||
|
+#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE1 0x00090000
|
||
|
+#define NV20TCL_RC_FINAL1_F_INPUT_SPARE0 0x000c0000
|
||
|
+#define NV20TCL_RC_FINAL1_F_INPUT_SPARE1 0x000d0000
|
||
|
+#define NV20TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
|
||
|
+#define NV20TCL_RC_FINAL1_F_INPUT_E_TIMES_F 0x000f0000
|
||
|
+#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE2 0x000a0000
|
||
|
+#define NV20TCL_RC_FINAL1_F_INPUT_TEXTURE3 0x000b0000
|
||
|
#define NV20TCL_RC_FINAL1_F_COMPONENT_USAGE (1 << 20)
|
||
|
#define NV20TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV20TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000
|
||
|
#define NV20TCL_RC_FINAL1_F_MAPPING_SHIFT 21
|
||
|
#define NV20TCL_RC_FINAL1_F_MAPPING_MASK 0x00e00000
|
||
|
-#define NV20TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT_NV 0x00200000
|
||
|
-#define NV20TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL_NV 0x00400000
|
||
|
-#define NV20TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE_NV 0x00600000
|
||
|
-#define NV20TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
|
||
|
-#define NV20TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
|
||
|
-#define NV20TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
|
||
|
-#define NV20TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE_NV 0x00e00000
|
||
|
+#define NV20TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT 0x00200000
|
||
|
+#define NV20TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL 0x00400000
|
||
|
+#define NV20TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE 0x00600000
|
||
|
+#define NV20TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL 0x00800000
|
||
|
+#define NV20TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE 0x00a00000
|
||
|
+#define NV20TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY 0x00c00000
|
||
|
+#define NV20TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE 0x00e00000
|
||
|
#define NV20TCL_RC_FINAL1_E_INPUT_SHIFT 24
|
||
|
#define NV20TCL_RC_FINAL1_E_INPUT_MASK 0x0f000000
|
||
|
#define NV20TCL_RC_FINAL1_E_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0_NV 0x01000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1_NV 0x02000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0 0x01000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1 0x02000000
|
||
|
#define NV20TCL_RC_FINAL1_E_INPUT_FOG 0x03000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR_NV 0x04000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR_NV 0x05000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE0_ARB 0x08000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE1_ARB 0x09000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_INPUT_SPARE0_NV 0x0c000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_INPUT_SPARE1_NV 0x0d000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_INPUT_E_TIMES_F_NV 0x0f000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE2_ARB 0x0a000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE3_ARB 0x0b000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR 0x04000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR 0x05000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE0 0x08000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE1 0x09000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_INPUT_SPARE0 0x0c000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_INPUT_SPARE1 0x0d000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_INPUT_E_TIMES_F 0x0f000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE2 0x0a000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_INPUT_TEXTURE3 0x0b000000
|
||
|
#define NV20TCL_RC_FINAL1_E_COMPONENT_USAGE (1 << 28)
|
||
|
#define NV20TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV20TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000
|
||
|
#define NV20TCL_RC_FINAL1_E_MAPPING_SHIFT 29
|
||
|
#define NV20TCL_RC_FINAL1_E_MAPPING_MASK 0xe0000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT_NV 0x20000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL_NV 0x40000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE_NV 0x60000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
|
||
|
-#define NV20TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE_NV 0xe0000000
|
||
|
-#define NV20TCL_LIGHT_CONTROL 0x00000294
|
||
|
+#define NV20TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT 0x20000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL 0x40000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE 0x60000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL 0x80000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE 0xa0000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY 0xc0000000
|
||
|
+#define NV20TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE 0xe0000000
|
||
|
+#define NV20TCL_LIGHT_MODEL 0x00000294
|
||
|
+#define NV20TCL_LIGHT_MODEL_VIEWER_SHIFT 16
|
||
|
+#define NV20TCL_LIGHT_MODEL_VIEWER_MASK 0x00030000
|
||
|
+#define NV20TCL_LIGHT_MODEL_VIEWER_NONLOCAL 0x00020000
|
||
|
+#define NV20TCL_LIGHT_MODEL_VIEWER_LOCAL 0x00030000
|
||
|
+#define NV20TCL_LIGHT_MODEL_SEPARATE_SPECULAR (1 << 0)
|
||
|
+#define NV20TCL_COLOR_MATERIAL 0x00000298
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_SHIFT 0
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_MASK 0x00000003
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_OFF 0x00000000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_COL1 0x00000001
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_COL2 0x00000002
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_SHIFT 2
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_MASK 0x0000000c
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_OFF 0x00000000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_COL1 0x00000004
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_COL2 0x00000008
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_SHIFT 4
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_MASK 0x00000030
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_OFF 0x00000000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_COL1 0x00000010
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_COL2 0x00000020
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_SHIFT 6
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_MASK 0x000000c0
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_OFF 0x00000000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_COL1 0x00000040
|
||
|
+#define NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_COL2 0x00000080
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_SHIFT 8
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_MASK 0x00000300
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_OFF 0x00000000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_COL1 0x00000100
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_EMISSION_COL2 0x00000200
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_SHIFT 10
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_MASK 0x00000c00
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_OFF 0x00000000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_COL1 0x00000400
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_COL2 0x00000800
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_SHIFT 12
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_MASK 0x00003000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_OFF 0x00000000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_COL1 0x00001000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_COL2 0x00002000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_SHIFT 14
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_MASK 0x0000c000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_OFF 0x00000000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_COL1 0x00004000
|
||
|
+#define NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_COL2 0x00008000
|
||
|
#define NV20TCL_FOG_MODE 0x0000029c
|
||
|
-#define NV20TCL_FOG_MODE_EXP 0x00000800
|
||
|
-#define NV20TCL_FOG_MODE_EXP_2 0x00000802
|
||
|
-#define NV20TCL_FOG_MODE_EXP2 0x00000803
|
||
|
-#define NV20TCL_FOG_MODE_LINEAR 0x00000804
|
||
|
-#define NV20TCL_FOG_MODE_LINEAR_2 0x00002601
|
||
|
-#define NV20TCL_FOG_COORD_DIST 0x000002a0
|
||
|
-#define NV20TCL_FOG_COORD_DIST_COORD_FALSE 0x00000000
|
||
|
-#define NV20TCL_FOG_COORD_DIST_COORD_FRAGMENT_DEPTH_DISTANCE_EYE_RADIAL_NV 0x00000001
|
||
|
-#define NV20TCL_FOG_COORD_DIST_COORD_FRAGMENT_DEPTH_DISTANCE_EYE_PLANE_ABSOLUTE_NV 0x00000002
|
||
|
-#define NV20TCL_FOG_COORD_DIST_COORD_FOG 0x00000003
|
||
|
+#define NV20TCL_FOG_MODE_LINEAR_UNSIGNED 0x00000804
|
||
|
+#define NV20TCL_FOG_MODE_LINEAR_SIGNED 0x00002601
|
||
|
+#define NV20TCL_FOG_MODE_EXP_UNSIGNED 0x00000802
|
||
|
+#define NV20TCL_FOG_MODE_EXP_SIGNED 0x00000800
|
||
|
+#define NV20TCL_FOG_MODE_EXP2_UNSIGNED 0x00000803
|
||
|
+#define NV20TCL_FOG_MODE_EXP2_SIGNED 0x00000801
|
||
|
+#define NV20TCL_FOG_COORD 0x000002a0
|
||
|
+#define NV20TCL_FOG_COORD_DIST_RADIAL 0x00000001
|
||
|
+#define NV20TCL_FOG_COORD_DIST_ORTHOGONAL 0x00000002
|
||
|
+#define NV20TCL_FOG_COORD_DIST_ORTHOGONAL_ABS 0x00000003
|
||
|
+#define NV20TCL_FOG_COORD_FOG 0x00000006
|
||
|
#define NV20TCL_FOG_ENABLE 0x000002a4
|
||
|
#define NV20TCL_FOG_COLOR 0x000002a8
|
||
|
#define NV20TCL_FOG_COLOR_R_SHIFT 0
|
||
|
@@ -3749,7 +3842,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_ALPHA_FUNC_FUNC_EQUAL 0x00000202
|
||
|
#define NV20TCL_ALPHA_FUNC_FUNC_LEQUAL 0x00000203
|
||
|
#define NV20TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204
|
||
|
-#define NV20TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204
|
||
|
#define NV20TCL_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV20TCL_ALPHA_FUNC_FUNC_GEQUAL 0x00000206
|
||
|
#define NV20TCL_ALPHA_FUNC_FUNC_ALWAYS 0x00000207
|
||
|
@@ -3807,7 +3899,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_DEPTH_FUNC_EQUAL 0x00000202
|
||
|
#define NV20TCL_DEPTH_FUNC_LEQUAL 0x00000203
|
||
|
#define NV20TCL_DEPTH_FUNC_GREATER 0x00000204
|
||
|
-#define NV20TCL_DEPTH_FUNC_GREATER 0x00000204
|
||
|
#define NV20TCL_DEPTH_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV20TCL_DEPTH_FUNC_GEQUAL 0x00000206
|
||
|
#define NV20TCL_DEPTH_FUNC_ALWAYS 0x00000207
|
||
|
@@ -3824,7 +3915,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_STENCIL_FUNC_FUNC_EQUAL 0x00000202
|
||
|
#define NV20TCL_STENCIL_FUNC_FUNC_LEQUAL 0x00000203
|
||
|
#define NV20TCL_STENCIL_FUNC_FUNC_GREATER 0x00000204
|
||
|
-#define NV20TCL_STENCIL_FUNC_FUNC_GREATER 0x00000204
|
||
|
#define NV20TCL_STENCIL_FUNC_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV20TCL_STENCIL_FUNC_FUNC_GEQUAL 0x00000206
|
||
|
#define NV20TCL_STENCIL_FUNC_FUNC_ALWAYS 0x00000207
|
||
|
@@ -3881,12 +3971,60 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_FRONT_FACE_CW 0x00000900
|
||
|
#define NV20TCL_FRONT_FACE_CCW 0x00000901
|
||
|
#define NV20TCL_NORMALIZE_ENABLE 0x000003a4
|
||
|
-#define NV20TCL_COLOR_MATERIAL_FRONT_R 0x000003a8
|
||
|
-#define NV20TCL_COLOR_MATERIAL_FRONT_G 0x000003ac
|
||
|
-#define NV20TCL_COLOR_MATERIAL_FRONT_B 0x000003b0
|
||
|
-#define NV20TCL_COLOR_MATERIAL_FRONT_A 0x000003b4
|
||
|
+#define NV20TCL_MATERIAL_FACTOR_FRONT_R 0x000003a8
|
||
|
+#define NV20TCL_MATERIAL_FACTOR_FRONT_G 0x000003ac
|
||
|
+#define NV20TCL_MATERIAL_FACTOR_FRONT_B 0x000003b0
|
||
|
+#define NV20TCL_MATERIAL_FACTOR_FRONT_A 0x000003b4
|
||
|
#define NV20TCL_SEPARATE_SPECULAR_ENABLE 0x000003b8
|
||
|
#define NV20TCL_ENABLED_LIGHTS 0x000003bc
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_0_SHIFT 0
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_0_MASK 0x00000003
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_0_DISABLED 0x00000000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_0_NONPOSITIONAL 0x00000001
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_0_POSITIONAL 0x00000002
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_0_DIRECTIONAL 0x00000003
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_1_SHIFT 2
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_1_MASK 0x0000000c
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_1_DISABLED 0x00000000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_1_NONPOSITIONAL 0x00000004
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_1_POSITIONAL 0x00000008
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_1_DIRECTIONAL 0x0000000c
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_2_SHIFT 4
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_2_MASK 0x00000030
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_2_DISABLED 0x00000000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_2_NONPOSITIONAL 0x00000010
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_2_POSITIONAL 0x00000020
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_2_DIRECTIONAL 0x00000030
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_3_SHIFT 6
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_3_MASK 0x000000c0
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_3_DISABLED 0x00000000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_3_NONPOSITIONAL 0x00000040
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_3_POSITIONAL 0x00000080
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_3_DIRECTIONAL 0x000000c0
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_4_SHIFT 8
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_4_MASK 0x00000300
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_4_DISABLED 0x00000000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_4_NONPOSITIONAL 0x00000100
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_4_POSITIONAL 0x00000200
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_4_DIRECTIONAL 0x00000300
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_5_SHIFT 10
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_5_MASK 0x00000c00
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_5_DISABLED 0x00000000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_5_NONPOSITIONAL 0x00000400
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_5_POSITIONAL 0x00000800
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_5_DIRECTIONAL 0x00000c00
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_6_SHIFT 12
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_6_MASK 0x00003000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_6_DISABLED 0x00000000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_6_NONPOSITIONAL 0x00001000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_6_POSITIONAL 0x00002000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_6_DIRECTIONAL 0x00003000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_7_SHIFT 14
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_7_MASK 0x0000c000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_7_DISABLED 0x00000000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_7_NONPOSITIONAL 0x00004000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_7_POSITIONAL 0x00008000
|
||
|
+#define NV20TCL_ENABLED_LIGHTS_7_DIRECTIONAL 0x0000c000
|
||
|
#define NV20TCL_TX_GEN_S(x) (0x000003c0+((x)*16))
|
||
|
#define NV20TCL_TX_GEN_S__SIZE 0x00000004
|
||
|
#define NV20TCL_TX_GEN_S_FALSE 0x00000000
|
||
|
@@ -3985,9 +4123,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_FOG_EQUATION_QUADRATIC 0x000009c8
|
||
|
#define NV20TCL_FRONT_MATERIAL_SHININESS(x) (0x000009e0+((x)*4))
|
||
|
#define NV20TCL_FRONT_MATERIAL_SHININESS__SIZE 0x00000006
|
||
|
-#define NV20TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x00000a10
|
||
|
-#define NV20TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x00000a14
|
||
|
-#define NV20TCL_LIGHT_MODEL_FRONT_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x00000a18
|
||
|
+#define NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_R 0x00000a10
|
||
|
+#define NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_G 0x00000a14
|
||
|
+#define NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_B 0x00000a18
|
||
|
#define NV20TCL_VIEWPORT_TRANSLATE_X 0x00000a20
|
||
|
#define NV20TCL_VIEWPORT_TRANSLATE_Y 0x00000a24
|
||
|
#define NV20TCL_VIEWPORT_TRANSLATE_Z 0x00000a28
|
||
|
@@ -4019,181 +4157,181 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT 0
|
||
|
#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f
|
||
|
#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0 0x00000008
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1 0x00000009
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0 0x0000000c
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1 0x0000000d
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3 0x0000000b
|
||
|
#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4
|
||
|
#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0
|
||
|
#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV 0x00000010
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV 0x00000020
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0 0x00000010
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1 0x00000020
|
||
|
#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV 0x00000040
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV 0x00000050
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB 0x00000080
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB 0x00000090
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV 0x000000c0
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV 0x000000d0
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000000e0
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV 0x000000f0
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2_ARB 0x000000a0
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3_ARB 0x000000b0
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR 0x00000040
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR 0x00000050
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0 0x00000080
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1 0x00000090
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0 0x000000c0
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1 0x000000d0
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F 0x000000f0
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2 0x000000a0
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3 0x000000b0
|
||
|
#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8
|
||
|
#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00
|
||
|
#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0 0x00000800
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1 0x00000900
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0 0x00000c00
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1 0x00000d00
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3 0x00000b00
|
||
|
#define NV20TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12)
|
||
|
#define NV20TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13)
|
||
|
#define NV20TCL_RC_OUT_ALPHA_MUX_SUM (1 << 14)
|
||
|
#define NV20TCL_RC_OUT_ALPHA_BIAS (1 << 15)
|
||
|
#define NV20TCL_RC_OUT_ALPHA_BIAS_NONE 0x00000000
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00008000
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000
|
||
|
#define NV20TCL_RC_OUT_ALPHA_SCALE_SHIFT 17
|
||
|
#define NV20TCL_RC_OUT_ALPHA_SCALE_MASK 0x00000000
|
||
|
#define NV20TCL_RC_OUT_ALPHA_SCALE_NONE 0x00000000
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV 0x00020000
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV 0x00040000
|
||
|
-#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV 0x00060000
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO 0x00020000
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR 0x00040000
|
||
|
+#define NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF 0x00060000
|
||
|
#define NV20TCL_RC_IN_RGB(x) (0x00000ac0+((x)*4))
|
||
|
#define NV20TCL_RC_IN_RGB__SIZE 0x00000008
|
||
|
#define NV20TCL_RC_IN_RGB_D_INPUT_SHIFT 0
|
||
|
#define NV20TCL_RC_IN_RGB_D_INPUT_MASK 0x0000000f
|
||
|
#define NV20TCL_RC_IN_RGB_D_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV20TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV20TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV20TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV20TCL_RC_IN_RGB_D_INPUT_FOG 0x00000003
|
||
|
-#define NV20TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV20TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV20TCL_RC_IN_RGB_D_INPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV20TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV20TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE0 0x00000008
|
||
|
+#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE1 0x00000009
|
||
|
+#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE0 0x0000000c
|
||
|
+#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE1 0x0000000d
|
||
|
+#define NV20TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV20TCL_RC_IN_RGB_D_INPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE3 0x0000000b
|
||
|
#define NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE (1 << 4)
|
||
|
#define NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010
|
||
|
#define NV20TCL_RC_IN_RGB_D_MAPPING_SHIFT 5
|
||
|
#define NV20TCL_RC_IN_RGB_D_MAPPING_MASK 0x000000e0
|
||
|
-#define NV20TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
|
||
|
-#define NV20TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
|
||
|
-#define NV20TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
|
||
|
-#define NV20TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
|
||
|
-#define NV20TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
|
||
|
-#define NV20TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
|
||
|
-#define NV20TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
|
||
|
+#define NV20TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT 0x00000020
|
||
|
+#define NV20TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL 0x00000040
|
||
|
+#define NV20TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE 0x00000060
|
||
|
+#define NV20TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL 0x00000080
|
||
|
+#define NV20TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0
|
||
|
+#define NV20TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY 0x000000c0
|
||
|
+#define NV20TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE 0x000000e0
|
||
|
#define NV20TCL_RC_IN_RGB_C_INPUT_SHIFT 8
|
||
|
#define NV20TCL_RC_IN_RGB_C_INPUT_MASK 0x00000f00
|
||
|
#define NV20TCL_RC_IN_RGB_C_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV20TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV20TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV20TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV20TCL_RC_IN_RGB_C_INPUT_FOG 0x00000300
|
||
|
-#define NV20TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV20TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV20TCL_RC_IN_RGB_C_INPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV20TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV20TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE0 0x00000800
|
||
|
+#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE1 0x00000900
|
||
|
+#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE0 0x00000c00
|
||
|
+#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE1 0x00000d00
|
||
|
+#define NV20TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV20TCL_RC_IN_RGB_C_INPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE3 0x00000b00
|
||
|
#define NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE (1 << 12)
|
||
|
#define NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000
|
||
|
#define NV20TCL_RC_IN_RGB_C_MAPPING_SHIFT 13
|
||
|
#define NV20TCL_RC_IN_RGB_C_MAPPING_MASK 0x0000e000
|
||
|
-#define NV20TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
|
||
|
-#define NV20TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
|
||
|
-#define NV20TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
|
||
|
-#define NV20TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
|
||
|
-#define NV20TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
|
||
|
-#define NV20TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
|
||
|
-#define NV20TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
|
||
|
+#define NV20TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT 0x00002000
|
||
|
+#define NV20TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL 0x00004000
|
||
|
+#define NV20TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE 0x00006000
|
||
|
+#define NV20TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL 0x00008000
|
||
|
+#define NV20TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000
|
||
|
+#define NV20TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY 0x0000c000
|
||
|
+#define NV20TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE 0x0000e000
|
||
|
#define NV20TCL_RC_IN_RGB_B_INPUT_SHIFT 16
|
||
|
#define NV20TCL_RC_IN_RGB_B_INPUT_MASK 0x000f0000
|
||
|
#define NV20TCL_RC_IN_RGB_B_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0 0x00010000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1 0x00020000
|
||
|
#define NV20TCL_RC_IN_RGB_B_INPUT_FOG 0x00030000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR_NV 0x00040000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR_NV 0x00050000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE0_ARB 0x00080000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE1_ARB 0x00090000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE0_NV 0x000c0000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE1_NV 0x000d0000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_INPUT_E_TIMES_F_NV 0x000f0000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE2_ARB 0x000a0000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE3_ARB 0x000b0000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR 0x00040000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR 0x00050000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE0 0x00080000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE1 0x00090000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE0 0x000c0000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE1 0x000d0000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_INPUT_E_TIMES_F 0x000f0000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE2 0x000a0000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE3 0x000b0000
|
||
|
#define NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE (1 << 20)
|
||
|
#define NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000
|
||
|
#define NV20TCL_RC_IN_RGB_B_MAPPING_SHIFT 21
|
||
|
#define NV20TCL_RC_IN_RGB_B_MAPPING_MASK 0x00e00000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
|
||
|
-#define NV20TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT 0x00200000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL 0x00400000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE 0x00600000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL 0x00800000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY 0x00c00000
|
||
|
+#define NV20TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE 0x00e00000
|
||
|
#define NV20TCL_RC_IN_RGB_A_INPUT_SHIFT 24
|
||
|
#define NV20TCL_RC_IN_RGB_A_INPUT_MASK 0x0f000000
|
||
|
#define NV20TCL_RC_IN_RGB_A_INPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0 0x01000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1 0x02000000
|
||
|
#define NV20TCL_RC_IN_RGB_A_INPUT_FOG 0x03000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR_NV 0x04000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR_NV 0x05000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE0_ARB 0x08000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE1_ARB 0x09000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE0_NV 0x0c000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE1_NV 0x0d000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_INPUT_E_TIMES_F_NV 0x0f000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE2_ARB 0x0a000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE3_ARB 0x0b000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR 0x04000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR 0x05000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE0 0x08000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE1 0x09000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE0 0x0c000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE1 0x0d000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_INPUT_E_TIMES_F 0x0f000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE2 0x0a000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE3 0x0b000000
|
||
|
#define NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE (1 << 28)
|
||
|
#define NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000
|
||
|
#define NV20TCL_RC_IN_RGB_A_MAPPING_SHIFT 29
|
||
|
#define NV20TCL_RC_IN_RGB_A_MAPPING_MASK 0xe0000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
|
||
|
-#define NV20TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT 0x20000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL 0x40000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE 0x60000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL 0x80000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY 0xc0000000
|
||
|
+#define NV20TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE 0xe0000000
|
||
|
#define NV20TCL_VIEWPORT_SCALE_X 0x00000af0
|
||
|
#define NV20TCL_VIEWPORT_SCALE_Y 0x00000af4
|
||
|
#define NV20TCL_VIEWPORT_SCALE_Z 0x00000af8
|
||
|
@@ -4202,30 +4340,42 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_VP_UPLOAD_INST__SIZE 0x00000004
|
||
|
#define NV20TCL_VP_UPLOAD_CONST(x) (0x00000b80+((x)*4))
|
||
|
#define NV20TCL_VP_UPLOAD_CONST__SIZE 0x00000004
|
||
|
-#define NV20TCL_LIGHT_BACK_SIDE_PRODUCT_AMBIENT_R(x) (0x00000c00+((x)*64))
|
||
|
-#define NV20TCL_LIGHT_BACK_SIDE_PRODUCT_AMBIENT_R__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_BACK_SIDE_PRODUCT_AMBIENT_G(x) (0x00000c04+((x)*64))
|
||
|
-#define NV20TCL_LIGHT_BACK_SIDE_PRODUCT_AMBIENT_G__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_BACK_SIDE_PRODUCT_AMBIENT_B(x) (0x00000c08+((x)*64))
|
||
|
-#define NV20TCL_LIGHT_BACK_SIDE_PRODUCT_AMBIENT_B__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R(x) (0x00001000+((x)*128))
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_R__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G(x) (0x00001004+((x)*128))
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_G__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B(x) (0x00001008+((x)*128))
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_AMBIENT_B__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R(x) (0x0000100c+((x)*128))
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_R__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G(x) (0x00001010+((x)*128))
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_G__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B(x) (0x00001014+((x)*128))
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_DIFFUSE_B__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R(x) (0x00001018+((x)*128))
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_R__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G(x) (0x0000101c+((x)*128))
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_G__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B(x) (0x00001020+((x)*128))
|
||
|
-#define NV20TCL_LIGHT_FRONT_SIDE_PRODUCT_SPECULAR_B__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_BACK_AMBIENT_R(x) (0x00000c00+((x)*64))
|
||
|
+#define NV20TCL_LIGHT_BACK_AMBIENT_R__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_BACK_AMBIENT_G(x) (0x00000c04+((x)*64))
|
||
|
+#define NV20TCL_LIGHT_BACK_AMBIENT_G__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_BACK_AMBIENT_B(x) (0x00000c08+((x)*64))
|
||
|
+#define NV20TCL_LIGHT_BACK_AMBIENT_B__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_BACK_DIFFUSE_R(x) (0x00000c0c+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_BACK_DIFFUSE_R__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_BACK_DIFFUSE_G(x) (0x00000c10+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_BACK_DIFFUSE_G__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_BACK_DIFFUSE_B(x) (0x00000c14+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_BACK_DIFFUSE_B__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_BACK_SPECULAR_R(x) (0x00000c18+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_BACK_SPECULAR_R__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_BACK_SPECULAR_G(x) (0x00000c1c+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_BACK_SPECULAR_G__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_BACK_SPECULAR_B(x) (0x00000c20+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_BACK_SPECULAR_B__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_FRONT_AMBIENT_R(x) (0x00001000+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_FRONT_AMBIENT_R__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_FRONT_AMBIENT_G(x) (0x00001004+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_FRONT_AMBIENT_G__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_FRONT_AMBIENT_B(x) (0x00001008+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_FRONT_AMBIENT_B__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_FRONT_DIFFUSE_R(x) (0x0000100c+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_FRONT_DIFFUSE_R__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_FRONT_DIFFUSE_G(x) (0x00001010+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_FRONT_DIFFUSE_G__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_FRONT_DIFFUSE_B(x) (0x00001014+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_FRONT_DIFFUSE_B__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_FRONT_SPECULAR_R(x) (0x00001018+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_FRONT_SPECULAR_R__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_FRONT_SPECULAR_G(x) (0x0000101c+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_FRONT_SPECULAR_G__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_FRONT_SPECULAR_B(x) (0x00001020+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_FRONT_SPECULAR_B__SIZE 0x00000008
|
||
|
#define NV20TCL_LIGHT_HALF_VECTOR_X(x) (0x00001028+((x)*128))
|
||
|
#define NV20TCL_LIGHT_HALF_VECTOR_X__SIZE 0x00000008
|
||
|
#define NV20TCL_LIGHT_HALF_VECTOR_Y(x) (0x0000102c+((x)*128))
|
||
|
@@ -4238,18 +4388,32 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_LIGHT_DIRECTION_Y__SIZE 0x00000008
|
||
|
#define NV20TCL_LIGHT_DIRECTION_Z(x) (0x0000103c+((x)*128))
|
||
|
#define NV20TCL_LIGHT_DIRECTION_Z__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_SPOT_CUTOFF_A(x) (0x00001040+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_SPOT_CUTOFF_A__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_SPOT_CUTOFF_B(x) (0x00001044+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_SPOT_CUTOFF_B__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_SPOT_CUTOFF_C(x) (0x00001048+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_SPOT_CUTOFF_C__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_SPOT_DIR_X(x) (0x0000104c+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_SPOT_DIR_X__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_SPOT_DIR_Y(x) (0x00001050+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_SPOT_DIR_Y__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_SPOT_DIR_Z(x) (0x00001054+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_SPOT_DIR_Z__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_SPOT_CUTOFF_D(x) (0x00001058+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_SPOT_CUTOFF_D__SIZE 0x00000008
|
||
|
#define NV20TCL_LIGHT_POSITION_X(x) (0x0000105c+((x)*128))
|
||
|
#define NV20TCL_LIGHT_POSITION_X__SIZE 0x00000008
|
||
|
#define NV20TCL_LIGHT_POSITION_Y(x) (0x00001060+((x)*128))
|
||
|
#define NV20TCL_LIGHT_POSITION_Y__SIZE 0x00000008
|
||
|
#define NV20TCL_LIGHT_POSITION_Z(x) (0x00001064+((x)*128))
|
||
|
#define NV20TCL_LIGHT_POSITION_Z__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_CONSTANT_ATTENUATION(x) (0x00001068+((x)*128))
|
||
|
-#define NV20TCL_LIGHT_CONSTANT_ATTENUATION__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_LINEAR_ATTENUATION(x) (0x0000106c+((x)*128))
|
||
|
-#define NV20TCL_LIGHT_LINEAR_ATTENUATION__SIZE 0x00000008
|
||
|
-#define NV20TCL_LIGHT_QUADRATIC_ATTENUATION(x) (0x00001070+((x)*128))
|
||
|
-#define NV20TCL_LIGHT_QUADRATIC_ATTENUATION__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_ATTENUATION_CONSTANT(x) (0x00001068+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_ATTENUATION_CONSTANT__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_ATTENUATION_LINEAR(x) (0x0000106c+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_ATTENUATION_LINEAR__SIZE 0x00000008
|
||
|
+#define NV20TCL_LIGHT_ATTENUATION_QUADRATIC(x) (0x00001070+((x)*128))
|
||
|
+#define NV20TCL_LIGHT_ATTENUATION_QUADRATIC__SIZE 0x00000008
|
||
|
#define NV20TCL_POLYGON_STIPPLE_ENABLE 0x0000147c
|
||
|
#define NV20TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001480+((x)*4))
|
||
|
#define NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020
|
||
|
@@ -4409,13 +4573,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_VTXFMT_SIZE_MASK 0x000000f0
|
||
|
#define NV20TCL_VTXFMT_STRIDE_SHIFT 8
|
||
|
#define NV20TCL_VTXFMT_STRIDE_MASK 0x0000ff00
|
||
|
-#define NV20TCL_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_R 0x000017a0
|
||
|
-#define NV20TCL_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_G 0x000017a4
|
||
|
-#define NV20TCL_LIGHT_MODEL_BACK_SIDE_PRODUCT_AMBIENT_PLUS_EMISSION_B 0x000017a8
|
||
|
-#define NV20TCL_COLOR_MATERIAL_BACK_A 0x000017ac
|
||
|
-#define NV20TCL_COLOR_MATERIAL_BACK_R 0x000017b0
|
||
|
-#define NV20TCL_COLOR_MATERIAL_BACK_G 0x000017b4
|
||
|
-#define NV20TCL_COLOR_MATERIAL_BACK_B 0x000017b8
|
||
|
+#define NV20TCL_LIGHT_MODEL_BACK_AMBIENT_R 0x000017a0
|
||
|
+#define NV20TCL_LIGHT_MODEL_BACK_AMBIENT_G 0x000017a4
|
||
|
+#define NV20TCL_LIGHT_MODEL_BACK_AMBIENT_B 0x000017a8
|
||
|
+#define NV20TCL_MATERIAL_FACTOR_BACK_A 0x000017ac
|
||
|
+#define NV20TCL_MATERIAL_FACTOR_BACK_R 0x000017b0
|
||
|
+#define NV20TCL_MATERIAL_FACTOR_BACK_G 0x000017b4
|
||
|
+#define NV20TCL_MATERIAL_FACTOR_BACK_B 0x000017b8
|
||
|
#define NV20TCL_COLOR_LOGIC_OP_ENABLE 0x000017bc
|
||
|
#define NV20TCL_COLOR_LOGIC_OP_OP 0x000017c0
|
||
|
#define NV20TCL_COLOR_LOGIC_OP_OP_CLEAR 0x00001500
|
||
|
@@ -4501,6 +4665,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff
|
||
|
#define NV20TCL_VB_ELEMENT_U16_I1_SHIFT 16
|
||
|
#define NV20TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000
|
||
|
+#define NV20TCL_VB_ELEMENT_U32 0x00001808
|
||
|
#define NV20TCL_VB_VERTEX_BATCH 0x00001810
|
||
|
#define NV20TCL_VB_VERTEX_BATCH_OFFSET_SHIFT 0
|
||
|
#define NV20TCL_VB_VERTEX_BATCH_OFFSET_MASK 0x00ffffff
|
||
|
@@ -4693,63 +4858,63 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT 0
|
||
|
#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f
|
||
|
#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003
|
||
|
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0 0x00000008
|
||
|
+#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1 0x00000009
|
||
|
+#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0 0x0000000c
|
||
|
+#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1 0x0000000d
|
||
|
+#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3 0x0000000b
|
||
|
#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT 4
|
||
|
#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0
|
||
|
#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV 0x00000010
|
||
|
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV 0x00000020
|
||
|
+#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0 0x00000010
|
||
|
+#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1 0x00000020
|
||
|
#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030
|
||
|
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV 0x00000040
|
||
|
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV 0x00000050
|
||
|
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB 0x00000080
|
||
|
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB 0x00000090
|
||
|
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV 0x000000c0
|
||
|
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV 0x000000d0
|
||
|
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000000e0
|
||
|
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV 0x000000f0
|
||
|
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2_ARB 0x000000a0
|
||
|
-#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3_ARB 0x000000b0
|
||
|
+#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR 0x00000040
|
||
|
+#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR 0x00000050
|
||
|
+#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0 0x00000080
|
||
|
+#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1 0x00000090
|
||
|
+#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0 0x000000c0
|
||
|
+#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1 0x000000d0
|
||
|
+#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0
|
||
|
+#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F 0x000000f0
|
||
|
+#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2 0x000000a0
|
||
|
+#define NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3 0x000000b0
|
||
|
#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8
|
||
|
#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00
|
||
|
#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300
|
||
|
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0 0x00000800
|
||
|
+#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1 0x00000900
|
||
|
+#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0 0x00000c00
|
||
|
+#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1 0x00000d00
|
||
|
+#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3 0x00000b00
|
||
|
#define NV20TCL_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12)
|
||
|
#define NV20TCL_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13)
|
||
|
#define NV20TCL_RC_OUT_RGB_MUX_SUM (1 << 14)
|
||
|
#define NV20TCL_RC_OUT_RGB_BIAS (1 << 15)
|
||
|
#define NV20TCL_RC_OUT_RGB_BIAS_NONE 0x00000000
|
||
|
-#define NV20TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00008000
|
||
|
+#define NV20TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000
|
||
|
#define NV20TCL_RC_OUT_RGB_SCALE_SHIFT 17
|
||
|
#define NV20TCL_RC_OUT_RGB_SCALE_MASK 0x00000000
|
||
|
#define NV20TCL_RC_OUT_RGB_SCALE_NONE 0x00000000
|
||
|
-#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV 0x00020000
|
||
|
-#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV 0x00040000
|
||
|
-#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV 0x00060000
|
||
|
+#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO 0x00020000
|
||
|
+#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR 0x00040000
|
||
|
+#define NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF 0x00060000
|
||
|
#define NV20TCL_RC_ENABLE 0x00001e60
|
||
|
#define NV20TCL_RC_ENABLE_NUM_COMBINERS_SHIFT 0
|
||
|
#define NV20TCL_RC_ENABLE_NUM_COMBINERS_MASK 0x0000000f
|
||
|
@@ -4837,66 +5002,22 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV20TCL_VP_UPLOAD_CONST_ID 0x00001ea4
|
||
|
|
||
|
|
||
|
-#define NV17TCL 0x00000099
|
||
|
-
|
||
|
-#define NV17TCL_DMA_IN_MEMORY4 0x000001ac
|
||
|
-#define NV17TCL_DMA_IN_MEMORY5 0x000001b0
|
||
|
-#define NV17TCL_COLOR_MASK_ENABLE 0x000002bc
|
||
|
-#define NV17TCL_LMA_DEPTH_BUFFER_PITCH 0x00000d5c
|
||
|
-#define NV17TCL_LMA_DEPTH_BUFFER_OFFSET 0x00000d60
|
||
|
-#define NV17TCL_LMA_DEPTH_FILL_VALUE 0x00000d68
|
||
|
-#define NV17TCL_LMA_DEPTH_BUFFER_CLEAR 0x00000d6c
|
||
|
-#define NV17TCL_LMA_DEPTH_ENABLE 0x00001658
|
||
|
-
|
||
|
-
|
||
|
-#define NV20_SWIZZLED_SURFACE 0x0000009e
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV12_IMAGE_BLIT 0x0000009f
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV30_CONTEXT_SURFACES_2D 0x00000362
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV30_STRETCHED_IMAGE_FROM_CPU 0x00000366
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV30_TEXTURE_FROM_CPU 0x0000037b
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV30_SCALED_IMAGE_FROM_MEMORY 0x00000389
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV30_IMAGE_FROM_CPU 0x0000038a
|
||
|
+#define NV25TCL 0x00000597
|
||
|
|
||
|
+#define NV25TCL_DMA_IN_MEMORY4 0x0000019c
|
||
|
+#define NV25TCL_DMA_IN_MEMORY5 0x000001a0
|
||
|
+#define NV25TCL_DMA_IN_MEMORY8 0x000001ac
|
||
|
+#define NV25TCL_DMA_IN_MEMORY9 0x000001b0
|
||
|
|
||
|
|
||
|
#define NV30TCL 0x00000397
|
||
|
|
||
|
|
||
|
|
||
|
-#define NV30_SWIZZLED_SURFACE 0x0000039e
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
#define NV35TCL 0x00000497
|
||
|
|
||
|
|
||
|
|
||
|
-#define NV25TCL 0x00000597
|
||
|
-
|
||
|
-#define NV25TCL_DMA_IN_MEMORY4 0x0000019c
|
||
|
-#define NV25TCL_DMA_IN_MEMORY5 0x000001a0
|
||
|
-#define NV25TCL_DMA_IN_MEMORY8 0x000001ac
|
||
|
-#define NV25TCL_DMA_IN_MEMORY9 0x000001b0
|
||
|
-
|
||
|
-
|
||
|
#define NV34TCL 0x00000697
|
||
|
|
||
|
#define NV34TCL_NOP 0x00000100
|
||
|
@@ -4997,7 +5118,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV34TCL_ALPHA_FUNC_FUNC_EQUAL 0x00000202
|
||
|
#define NV34TCL_ALPHA_FUNC_FUNC_LEQUAL 0x00000203
|
||
|
#define NV34TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204
|
||
|
-#define NV34TCL_ALPHA_FUNC_FUNC_GREATER 0x00000204
|
||
|
#define NV34TCL_ALPHA_FUNC_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV34TCL_ALPHA_FUNC_FUNC_GEQUAL 0x00000206
|
||
|
#define NV34TCL_ALPHA_FUNC_FUNC_ALWAYS 0x00000207
|
||
|
@@ -5105,7 +5225,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV34TCL_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202
|
||
|
#define NV34TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203
|
||
|
#define NV34TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
|
||
|
-#define NV34TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
|
||
|
#define NV34TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV34TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206
|
||
|
#define NV34TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207
|
||
|
@@ -5146,7 +5265,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_EQUAL 0x00000202
|
||
|
#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_LEQUAL 0x00000203
|
||
|
#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204
|
||
|
-#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204
|
||
|
#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206
|
||
|
#define NV34TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207
|
||
|
@@ -5293,16 +5411,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV34TCL_SCISSOR_VERT_H_SHIFT 16
|
||
|
#define NV34TCL_SCISSOR_VERT_H_MASK 0xffff0000
|
||
|
#define NV34TCL_FOG_COORD_DIST 0x000008c8
|
||
|
-#define NV34TCL_FOG_COORD_DIST_COORD_FALSE 0x00000000
|
||
|
-#define NV34TCL_FOG_COORD_DIST_COORD_FRAGMENT_DEPTH_DISTANCE_EYE_RADIAL_NV 0x00000001
|
||
|
-#define NV34TCL_FOG_COORD_DIST_COORD_FRAGMENT_DEPTH_DISTANCE_EYE_PLANE_ABSOLUTE_NV 0x00000002
|
||
|
-#define NV34TCL_FOG_COORD_DIST_COORD_FOG 0x00000003
|
||
|
#define NV34TCL_FOG_MODE 0x000008cc
|
||
|
-#define NV34TCL_FOG_MODE_EXP 0x00000800
|
||
|
-#define NV34TCL_FOG_MODE_EXP_2 0x00000802
|
||
|
-#define NV34TCL_FOG_MODE_EXP2 0x00000803
|
||
|
-#define NV34TCL_FOG_MODE_LINEAR 0x00000804
|
||
|
-#define NV34TCL_FOG_MODE_LINEAR_2 0x00002601
|
||
|
#define NV34TCL_FOG_EQUATION_CONSTANT 0x000008d0
|
||
|
#define NV34TCL_FOG_EQUATION_LINEAR 0x000008d4
|
||
|
#define NV34TCL_FOG_EQUATION_QUADRATIC 0x000008d8
|
||
|
@@ -5333,208 +5442,208 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV34TCL_RC_FINAL0_D_INPUT_SHIFT 0
|
||
|
#define NV34TCL_RC_FINAL0_D_INPUT_MASK 0x0000000f
|
||
|
#define NV34TCL_RC_FINAL0_D_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV34TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV34TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV34TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV34TCL_RC_FINAL0_D_INPUT_FOG 0x00000003
|
||
|
-#define NV34TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV34TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV34TCL_RC_FINAL0_D_INPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV34TCL_RC_FINAL0_D_INPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV34TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV34TCL_RC_FINAL0_D_INPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV34TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV34TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE0 0x00000008
|
||
|
+#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE1 0x00000009
|
||
|
+#define NV34TCL_RC_FINAL0_D_INPUT_SPARE0 0x0000000c
|
||
|
+#define NV34TCL_RC_FINAL0_D_INPUT_SPARE1 0x0000000d
|
||
|
+#define NV34TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV34TCL_RC_FINAL0_D_INPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV34TCL_RC_FINAL0_D_INPUT_TEXTURE3 0x0000000b
|
||
|
#define NV34TCL_RC_FINAL0_D_COMPONENT_USAGE (1 << 4)
|
||
|
#define NV34TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV34TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA 0x00000010
|
||
|
#define NV34TCL_RC_FINAL0_D_MAPPING_SHIFT 5
|
||
|
#define NV34TCL_RC_FINAL0_D_MAPPING_MASK 0x000000e0
|
||
|
-#define NV34TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
|
||
|
-#define NV34TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
|
||
|
-#define NV34TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
|
||
|
-#define NV34TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
|
||
|
-#define NV34TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
|
||
|
-#define NV34TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
|
||
|
-#define NV34TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
|
||
|
+#define NV34TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT 0x00000020
|
||
|
+#define NV34TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL 0x00000040
|
||
|
+#define NV34TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE 0x00000060
|
||
|
+#define NV34TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL 0x00000080
|
||
|
+#define NV34TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0
|
||
|
+#define NV34TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY 0x000000c0
|
||
|
+#define NV34TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE 0x000000e0
|
||
|
#define NV34TCL_RC_FINAL0_C_INPUT_SHIFT 8
|
||
|
#define NV34TCL_RC_FINAL0_C_INPUT_MASK 0x00000f00
|
||
|
#define NV34TCL_RC_FINAL0_C_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV34TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV34TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV34TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV34TCL_RC_FINAL0_C_INPUT_FOG 0x00000300
|
||
|
-#define NV34TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV34TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV34TCL_RC_FINAL0_C_INPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV34TCL_RC_FINAL0_C_INPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV34TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV34TCL_RC_FINAL0_C_INPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV34TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV34TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE0 0x00000800
|
||
|
+#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE1 0x00000900
|
||
|
+#define NV34TCL_RC_FINAL0_C_INPUT_SPARE0 0x00000c00
|
||
|
+#define NV34TCL_RC_FINAL0_C_INPUT_SPARE1 0x00000d00
|
||
|
+#define NV34TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV34TCL_RC_FINAL0_C_INPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV34TCL_RC_FINAL0_C_INPUT_TEXTURE3 0x00000b00
|
||
|
#define NV34TCL_RC_FINAL0_C_COMPONENT_USAGE (1 << 12)
|
||
|
#define NV34TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV34TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA 0x00001000
|
||
|
#define NV34TCL_RC_FINAL0_C_MAPPING_SHIFT 13
|
||
|
#define NV34TCL_RC_FINAL0_C_MAPPING_MASK 0x0000e000
|
||
|
-#define NV34TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
|
||
|
-#define NV34TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
|
||
|
-#define NV34TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
|
||
|
-#define NV34TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
|
||
|
-#define NV34TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
|
||
|
-#define NV34TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
|
||
|
-#define NV34TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
|
||
|
+#define NV34TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT 0x00002000
|
||
|
+#define NV34TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL 0x00004000
|
||
|
+#define NV34TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE 0x00006000
|
||
|
+#define NV34TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL 0x00008000
|
||
|
+#define NV34TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000
|
||
|
+#define NV34TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY 0x0000c000
|
||
|
+#define NV34TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE 0x0000e000
|
||
|
#define NV34TCL_RC_FINAL0_B_INPUT_SHIFT 16
|
||
|
#define NV34TCL_RC_FINAL0_B_INPUT_MASK 0x000f0000
|
||
|
#define NV34TCL_RC_FINAL0_B_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
|
||
|
-#define NV34TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
|
||
|
+#define NV34TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0 0x00010000
|
||
|
+#define NV34TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1 0x00020000
|
||
|
#define NV34TCL_RC_FINAL0_B_INPUT_FOG 0x00030000
|
||
|
-#define NV34TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR_NV 0x00040000
|
||
|
-#define NV34TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR_NV 0x00050000
|
||
|
-#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE0_ARB 0x00080000
|
||
|
-#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE1_ARB 0x00090000
|
||
|
-#define NV34TCL_RC_FINAL0_B_INPUT_SPARE0_NV 0x000c0000
|
||
|
-#define NV34TCL_RC_FINAL0_B_INPUT_SPARE1_NV 0x000d0000
|
||
|
-#define NV34TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
|
||
|
-#define NV34TCL_RC_FINAL0_B_INPUT_E_TIMES_F_NV 0x000f0000
|
||
|
-#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE2_ARB 0x000a0000
|
||
|
-#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE3_ARB 0x000b0000
|
||
|
+#define NV34TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR 0x00040000
|
||
|
+#define NV34TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR 0x00050000
|
||
|
+#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE0 0x00080000
|
||
|
+#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE1 0x00090000
|
||
|
+#define NV34TCL_RC_FINAL0_B_INPUT_SPARE0 0x000c0000
|
||
|
+#define NV34TCL_RC_FINAL0_B_INPUT_SPARE1 0x000d0000
|
||
|
+#define NV34TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
|
||
|
+#define NV34TCL_RC_FINAL0_B_INPUT_E_TIMES_F 0x000f0000
|
||
|
+#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE2 0x000a0000
|
||
|
+#define NV34TCL_RC_FINAL0_B_INPUT_TEXTURE3 0x000b0000
|
||
|
#define NV34TCL_RC_FINAL0_B_COMPONENT_USAGE (1 << 20)
|
||
|
#define NV34TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV34TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA 0x00100000
|
||
|
#define NV34TCL_RC_FINAL0_B_MAPPING_SHIFT 21
|
||
|
#define NV34TCL_RC_FINAL0_B_MAPPING_MASK 0x00e00000
|
||
|
-#define NV34TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
|
||
|
-#define NV34TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
|
||
|
-#define NV34TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
|
||
|
-#define NV34TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
|
||
|
-#define NV34TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
|
||
|
-#define NV34TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
|
||
|
-#define NV34TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
|
||
|
+#define NV34TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT 0x00200000
|
||
|
+#define NV34TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL 0x00400000
|
||
|
+#define NV34TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE 0x00600000
|
||
|
+#define NV34TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL 0x00800000
|
||
|
+#define NV34TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000
|
||
|
+#define NV34TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY 0x00c00000
|
||
|
+#define NV34TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE 0x00e00000
|
||
|
#define NV34TCL_RC_FINAL0_A_INPUT_SHIFT 24
|
||
|
#define NV34TCL_RC_FINAL0_A_INPUT_MASK 0x0f000000
|
||
|
#define NV34TCL_RC_FINAL0_A_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0 0x01000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1 0x02000000
|
||
|
#define NV34TCL_RC_FINAL0_A_INPUT_FOG 0x03000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR_NV 0x04000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR_NV 0x05000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE0_ARB 0x08000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE1_ARB 0x09000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_INPUT_SPARE0_NV 0x0c000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_INPUT_SPARE1_NV 0x0d000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_INPUT_E_TIMES_F_NV 0x0f000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE2_ARB 0x0a000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE3_ARB 0x0b000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR 0x04000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR 0x05000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE0 0x08000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE1 0x09000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_INPUT_SPARE0 0x0c000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_INPUT_SPARE1 0x0d000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_INPUT_E_TIMES_F 0x0f000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE2 0x0a000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_INPUT_TEXTURE3 0x0b000000
|
||
|
#define NV34TCL_RC_FINAL0_A_COMPONENT_USAGE (1 << 28)
|
||
|
#define NV34TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV34TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA 0x10000000
|
||
|
#define NV34TCL_RC_FINAL0_A_MAPPING_SHIFT 29
|
||
|
#define NV34TCL_RC_FINAL0_A_MAPPING_MASK 0xe0000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
|
||
|
-#define NV34TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT 0x20000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL 0x40000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE 0x60000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL 0x80000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY 0xc0000000
|
||
|
+#define NV34TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE 0xe0000000
|
||
|
#define NV34TCL_RC_FINAL1 0x000008f8
|
||
|
#define NV34TCL_RC_FINAL1_COLOR_SUM_CLAMP (1 << 7)
|
||
|
#define NV34TCL_RC_FINAL1_G_INPUT_SHIFT 8
|
||
|
#define NV34TCL_RC_FINAL1_G_INPUT_MASK 0x00000f00
|
||
|
#define NV34TCL_RC_FINAL1_G_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV34TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV34TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV34TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV34TCL_RC_FINAL1_G_INPUT_FOG 0x00000300
|
||
|
-#define NV34TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV34TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV34TCL_RC_FINAL1_G_INPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV34TCL_RC_FINAL1_G_INPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV34TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV34TCL_RC_FINAL1_G_INPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV34TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV34TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE0 0x00000800
|
||
|
+#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE1 0x00000900
|
||
|
+#define NV34TCL_RC_FINAL1_G_INPUT_SPARE0 0x00000c00
|
||
|
+#define NV34TCL_RC_FINAL1_G_INPUT_SPARE1 0x00000d00
|
||
|
+#define NV34TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV34TCL_RC_FINAL1_G_INPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV34TCL_RC_FINAL1_G_INPUT_TEXTURE3 0x00000b00
|
||
|
#define NV34TCL_RC_FINAL1_G_COMPONENT_USAGE (1 << 12)
|
||
|
#define NV34TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV34TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA 0x00001000
|
||
|
#define NV34TCL_RC_FINAL1_G_MAPPING_SHIFT 13
|
||
|
#define NV34TCL_RC_FINAL1_G_MAPPING_MASK 0x0000e000
|
||
|
-#define NV34TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT_NV 0x00002000
|
||
|
-#define NV34TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL_NV 0x00004000
|
||
|
-#define NV34TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE_NV 0x00006000
|
||
|
-#define NV34TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
|
||
|
-#define NV34TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
|
||
|
-#define NV34TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
|
||
|
-#define NV34TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE_NV 0x0000e000
|
||
|
+#define NV34TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT 0x00002000
|
||
|
+#define NV34TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL 0x00004000
|
||
|
+#define NV34TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE 0x00006000
|
||
|
+#define NV34TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL 0x00008000
|
||
|
+#define NV34TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE 0x0000a000
|
||
|
+#define NV34TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY 0x0000c000
|
||
|
+#define NV34TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE 0x0000e000
|
||
|
#define NV34TCL_RC_FINAL1_F_INPUT_SHIFT 16
|
||
|
#define NV34TCL_RC_FINAL1_F_INPUT_MASK 0x000f0000
|
||
|
#define NV34TCL_RC_FINAL1_F_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0_NV 0x00010000
|
||
|
-#define NV34TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1_NV 0x00020000
|
||
|
+#define NV34TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0 0x00010000
|
||
|
+#define NV34TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1 0x00020000
|
||
|
#define NV34TCL_RC_FINAL1_F_INPUT_FOG 0x00030000
|
||
|
-#define NV34TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR_NV 0x00040000
|
||
|
-#define NV34TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR_NV 0x00050000
|
||
|
-#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE0_ARB 0x00080000
|
||
|
-#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE1_ARB 0x00090000
|
||
|
-#define NV34TCL_RC_FINAL1_F_INPUT_SPARE0_NV 0x000c0000
|
||
|
-#define NV34TCL_RC_FINAL1_F_INPUT_SPARE1_NV 0x000d0000
|
||
|
-#define NV34TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
|
||
|
-#define NV34TCL_RC_FINAL1_F_INPUT_E_TIMES_F_NV 0x000f0000
|
||
|
-#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE2_ARB 0x000a0000
|
||
|
-#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE3_ARB 0x000b0000
|
||
|
+#define NV34TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR 0x00040000
|
||
|
+#define NV34TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR 0x00050000
|
||
|
+#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE0 0x00080000
|
||
|
+#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE1 0x00090000
|
||
|
+#define NV34TCL_RC_FINAL1_F_INPUT_SPARE0 0x000c0000
|
||
|
+#define NV34TCL_RC_FINAL1_F_INPUT_SPARE1 0x000d0000
|
||
|
+#define NV34TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
|
||
|
+#define NV34TCL_RC_FINAL1_F_INPUT_E_TIMES_F 0x000f0000
|
||
|
+#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE2 0x000a0000
|
||
|
+#define NV34TCL_RC_FINAL1_F_INPUT_TEXTURE3 0x000b0000
|
||
|
#define NV34TCL_RC_FINAL1_F_COMPONENT_USAGE (1 << 20)
|
||
|
#define NV34TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV34TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA 0x00100000
|
||
|
#define NV34TCL_RC_FINAL1_F_MAPPING_SHIFT 21
|
||
|
#define NV34TCL_RC_FINAL1_F_MAPPING_MASK 0x00e00000
|
||
|
-#define NV34TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT_NV 0x00200000
|
||
|
-#define NV34TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL_NV 0x00400000
|
||
|
-#define NV34TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE_NV 0x00600000
|
||
|
-#define NV34TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
|
||
|
-#define NV34TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
|
||
|
-#define NV34TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
|
||
|
-#define NV34TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE_NV 0x00e00000
|
||
|
+#define NV34TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT 0x00200000
|
||
|
+#define NV34TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL 0x00400000
|
||
|
+#define NV34TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE 0x00600000
|
||
|
+#define NV34TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL 0x00800000
|
||
|
+#define NV34TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE 0x00a00000
|
||
|
+#define NV34TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY 0x00c00000
|
||
|
+#define NV34TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE 0x00e00000
|
||
|
#define NV34TCL_RC_FINAL1_E_INPUT_SHIFT 24
|
||
|
#define NV34TCL_RC_FINAL1_E_INPUT_MASK 0x0f000000
|
||
|
#define NV34TCL_RC_FINAL1_E_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0_NV 0x01000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1_NV 0x02000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0 0x01000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1 0x02000000
|
||
|
#define NV34TCL_RC_FINAL1_E_INPUT_FOG 0x03000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR_NV 0x04000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR_NV 0x05000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE0_ARB 0x08000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE1_ARB 0x09000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_INPUT_SPARE0_NV 0x0c000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_INPUT_SPARE1_NV 0x0d000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_INPUT_E_TIMES_F_NV 0x0f000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE2_ARB 0x0a000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE3_ARB 0x0b000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR 0x04000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR 0x05000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE0 0x08000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE1 0x09000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_INPUT_SPARE0 0x0c000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_INPUT_SPARE1 0x0d000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_INPUT_E_TIMES_F 0x0f000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE2 0x0a000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_INPUT_TEXTURE3 0x0b000000
|
||
|
#define NV34TCL_RC_FINAL1_E_COMPONENT_USAGE (1 << 28)
|
||
|
#define NV34TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV34TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA 0x10000000
|
||
|
#define NV34TCL_RC_FINAL1_E_MAPPING_SHIFT 29
|
||
|
#define NV34TCL_RC_FINAL1_E_MAPPING_MASK 0xe0000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT_NV 0x20000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL_NV 0x40000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE_NV 0x60000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
|
||
|
-#define NV34TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE_NV 0xe0000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT 0x20000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL 0x40000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE 0x60000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL 0x80000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE 0xa0000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY 0xc0000000
|
||
|
+#define NV34TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE 0xe0000000
|
||
|
#define NV34TCL_RC_ENABLE 0x000008fc
|
||
|
#define NV34TCL_RC_ENABLE_NUM_COMBINERS_SHIFT 0
|
||
|
#define NV34TCL_RC_ENABLE_NUM_COMBINERS_MASK 0x0000000f
|
||
|
@@ -5547,237 +5656,237 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV34TCL_RC_IN_ALPHA_D_INPUT_SHIFT 0
|
||
|
#define NV34TCL_RC_IN_ALPHA_D_INPUT_MASK 0x0000000f
|
||
|
#define NV34TCL_RC_IN_ALPHA_D_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV34TCL_RC_IN_ALPHA_D_INPUT_FOG 0x00000003
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0 0x00000008
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1 0x00000009
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_INPUT_SPARE0 0x0000000c
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_INPUT_SPARE1 0x0000000d
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3 0x0000000b
|
||
|
#define NV34TCL_RC_IN_ALPHA_D_COMPONENT_USAGE (1 << 4)
|
||
|
#define NV34TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE 0x00000000
|
||
|
#define NV34TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA 0x00000010
|
||
|
#define NV34TCL_RC_IN_ALPHA_D_MAPPING_SHIFT 5
|
||
|
#define NV34TCL_RC_IN_ALPHA_D_MAPPING_MASK 0x000000e0
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
|
||
|
-#define NV34TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT 0x00000020
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL 0x00000040
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE 0x00000060
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL 0x00000080
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY 0x000000c0
|
||
|
+#define NV34TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE 0x000000e0
|
||
|
#define NV34TCL_RC_IN_ALPHA_C_INPUT_SHIFT 8
|
||
|
#define NV34TCL_RC_IN_ALPHA_C_INPUT_MASK 0x00000f00
|
||
|
#define NV34TCL_RC_IN_ALPHA_C_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV34TCL_RC_IN_ALPHA_C_INPUT_FOG 0x00000300
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0 0x00000800
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1 0x00000900
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_INPUT_SPARE0 0x00000c00
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_INPUT_SPARE1 0x00000d00
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3 0x00000b00
|
||
|
#define NV34TCL_RC_IN_ALPHA_C_COMPONENT_USAGE (1 << 12)
|
||
|
#define NV34TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE 0x00000000
|
||
|
#define NV34TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA 0x00001000
|
||
|
#define NV34TCL_RC_IN_ALPHA_C_MAPPING_SHIFT 13
|
||
|
#define NV34TCL_RC_IN_ALPHA_C_MAPPING_MASK 0x0000e000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT 0x00002000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL 0x00004000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE 0x00006000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL 0x00008000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY 0x0000c000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE 0x0000e000
|
||
|
#define NV34TCL_RC_IN_ALPHA_B_INPUT_SHIFT 16
|
||
|
#define NV34TCL_RC_IN_ALPHA_B_INPUT_MASK 0x000f0000
|
||
|
#define NV34TCL_RC_IN_ALPHA_B_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0 0x00010000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1 0x00020000
|
||
|
#define NV34TCL_RC_IN_ALPHA_B_INPUT_FOG 0x00030000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR_NV 0x00040000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR_NV 0x00050000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0_ARB 0x00080000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1_ARB 0x00090000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_SPARE0_NV 0x000c0000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_SPARE1_NV 0x000d0000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F_NV 0x000f0000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2_ARB 0x000a0000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3_ARB 0x000b0000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR 0x00040000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR 0x00050000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0 0x00080000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1 0x00090000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_INPUT_SPARE0 0x000c0000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_INPUT_SPARE1 0x000d0000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F 0x000f0000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2 0x000a0000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3 0x000b0000
|
||
|
#define NV34TCL_RC_IN_ALPHA_B_COMPONENT_USAGE (1 << 20)
|
||
|
#define NV34TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE 0x00000000
|
||
|
#define NV34TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA 0x00100000
|
||
|
#define NV34TCL_RC_IN_ALPHA_B_MAPPING_SHIFT 21
|
||
|
#define NV34TCL_RC_IN_ALPHA_B_MAPPING_MASK 0x00e00000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT 0x00200000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL 0x00400000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE 0x00600000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL 0x00800000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY 0x00c00000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE 0x00e00000
|
||
|
#define NV34TCL_RC_IN_ALPHA_A_INPUT_SHIFT 24
|
||
|
#define NV34TCL_RC_IN_ALPHA_A_INPUT_MASK 0x0f000000
|
||
|
#define NV34TCL_RC_IN_ALPHA_A_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0 0x01000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1 0x02000000
|
||
|
#define NV34TCL_RC_IN_ALPHA_A_INPUT_FOG 0x03000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR_NV 0x04000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR_NV 0x05000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0_ARB 0x08000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1_ARB 0x09000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_SPARE0_NV 0x0c000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_SPARE1_NV 0x0d000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F_NV 0x0f000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2_ARB 0x0a000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3_ARB 0x0b000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR 0x04000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR 0x05000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0 0x08000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1 0x09000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_INPUT_SPARE0 0x0c000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_INPUT_SPARE1 0x0d000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F 0x0f000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2 0x0a000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3 0x0b000000
|
||
|
#define NV34TCL_RC_IN_ALPHA_A_COMPONENT_USAGE (1 << 28)
|
||
|
#define NV34TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE 0x00000000
|
||
|
#define NV34TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA 0x10000000
|
||
|
#define NV34TCL_RC_IN_ALPHA_A_MAPPING_SHIFT 29
|
||
|
#define NV34TCL_RC_IN_ALPHA_A_MAPPING_MASK 0xe0000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
|
||
|
-#define NV34TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT 0x20000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL 0x40000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE 0x60000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL 0x80000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY 0xc0000000
|
||
|
+#define NV34TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE 0xe0000000
|
||
|
#define NV34TCL_RC_IN_RGB(x) (0x00000904+((x)*32))
|
||
|
#define NV34TCL_RC_IN_RGB__SIZE 0x00000008
|
||
|
#define NV34TCL_RC_IN_RGB_D_INPUT_SHIFT 0
|
||
|
#define NV34TCL_RC_IN_RGB_D_INPUT_MASK 0x0000000f
|
||
|
#define NV34TCL_RC_IN_RGB_D_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV34TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV34TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV34TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV34TCL_RC_IN_RGB_D_INPUT_FOG 0x00000003
|
||
|
-#define NV34TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV34TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV34TCL_RC_IN_RGB_D_INPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV34TCL_RC_IN_RGB_D_INPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV34TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV34TCL_RC_IN_RGB_D_INPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV34TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV34TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE0 0x00000008
|
||
|
+#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE1 0x00000009
|
||
|
+#define NV34TCL_RC_IN_RGB_D_INPUT_SPARE0 0x0000000c
|
||
|
+#define NV34TCL_RC_IN_RGB_D_INPUT_SPARE1 0x0000000d
|
||
|
+#define NV34TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV34TCL_RC_IN_RGB_D_INPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV34TCL_RC_IN_RGB_D_INPUT_TEXTURE3 0x0000000b
|
||
|
#define NV34TCL_RC_IN_RGB_D_COMPONENT_USAGE (1 << 4)
|
||
|
#define NV34TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV34TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA 0x00000010
|
||
|
#define NV34TCL_RC_IN_RGB_D_MAPPING_SHIFT 5
|
||
|
#define NV34TCL_RC_IN_RGB_D_MAPPING_MASK 0x000000e0
|
||
|
-#define NV34TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT_NV 0x00000020
|
||
|
-#define NV34TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL_NV 0x00000040
|
||
|
-#define NV34TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE_NV 0x00000060
|
||
|
-#define NV34TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL_NV 0x00000080
|
||
|
-#define NV34TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE_NV 0x000000a0
|
||
|
-#define NV34TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY_NV 0x000000c0
|
||
|
-#define NV34TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE_NV 0x000000e0
|
||
|
+#define NV34TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT 0x00000020
|
||
|
+#define NV34TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL 0x00000040
|
||
|
+#define NV34TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE 0x00000060
|
||
|
+#define NV34TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL 0x00000080
|
||
|
+#define NV34TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE 0x000000a0
|
||
|
+#define NV34TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY 0x000000c0
|
||
|
+#define NV34TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE 0x000000e0
|
||
|
#define NV34TCL_RC_IN_RGB_C_INPUT_SHIFT 8
|
||
|
#define NV34TCL_RC_IN_RGB_C_INPUT_MASK 0x00000f00
|
||
|
#define NV34TCL_RC_IN_RGB_C_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV34TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV34TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV34TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV34TCL_RC_IN_RGB_C_INPUT_FOG 0x00000300
|
||
|
-#define NV34TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV34TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV34TCL_RC_IN_RGB_C_INPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV34TCL_RC_IN_RGB_C_INPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV34TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV34TCL_RC_IN_RGB_C_INPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV34TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV34TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE0 0x00000800
|
||
|
+#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE1 0x00000900
|
||
|
+#define NV34TCL_RC_IN_RGB_C_INPUT_SPARE0 0x00000c00
|
||
|
+#define NV34TCL_RC_IN_RGB_C_INPUT_SPARE1 0x00000d00
|
||
|
+#define NV34TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV34TCL_RC_IN_RGB_C_INPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV34TCL_RC_IN_RGB_C_INPUT_TEXTURE3 0x00000b00
|
||
|
#define NV34TCL_RC_IN_RGB_C_COMPONENT_USAGE (1 << 12)
|
||
|
#define NV34TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV34TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA 0x00001000
|
||
|
#define NV34TCL_RC_IN_RGB_C_MAPPING_SHIFT 13
|
||
|
#define NV34TCL_RC_IN_RGB_C_MAPPING_MASK 0x0000e000
|
||
|
-#define NV34TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT_NV 0x00002000
|
||
|
-#define NV34TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL_NV 0x00004000
|
||
|
-#define NV34TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE_NV 0x00006000
|
||
|
-#define NV34TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL_NV 0x00008000
|
||
|
-#define NV34TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE_NV 0x0000a000
|
||
|
-#define NV34TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY_NV 0x0000c000
|
||
|
-#define NV34TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE_NV 0x0000e000
|
||
|
+#define NV34TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT 0x00002000
|
||
|
+#define NV34TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL 0x00004000
|
||
|
+#define NV34TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE 0x00006000
|
||
|
+#define NV34TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL 0x00008000
|
||
|
+#define NV34TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE 0x0000a000
|
||
|
+#define NV34TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY 0x0000c000
|
||
|
+#define NV34TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE 0x0000e000
|
||
|
#define NV34TCL_RC_IN_RGB_B_INPUT_SHIFT 16
|
||
|
#define NV34TCL_RC_IN_RGB_B_INPUT_MASK 0x000f0000
|
||
|
#define NV34TCL_RC_IN_RGB_B_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0_NV 0x00010000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1_NV 0x00020000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0 0x00010000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1 0x00020000
|
||
|
#define NV34TCL_RC_IN_RGB_B_INPUT_FOG 0x00030000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR_NV 0x00040000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR_NV 0x00050000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE0_ARB 0x00080000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE1_ARB 0x00090000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_INPUT_SPARE0_NV 0x000c0000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_INPUT_SPARE1_NV 0x000d0000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000e0000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_INPUT_E_TIMES_F_NV 0x000f0000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE2_ARB 0x000a0000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE3_ARB 0x000b0000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR 0x00040000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR 0x00050000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE0 0x00080000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE1 0x00090000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_INPUT_SPARE0 0x000c0000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_INPUT_SPARE1 0x000d0000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000e0000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_INPUT_E_TIMES_F 0x000f0000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE2 0x000a0000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_INPUT_TEXTURE3 0x000b0000
|
||
|
#define NV34TCL_RC_IN_RGB_B_COMPONENT_USAGE (1 << 20)
|
||
|
#define NV34TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV34TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA 0x00100000
|
||
|
#define NV34TCL_RC_IN_RGB_B_MAPPING_SHIFT 21
|
||
|
#define NV34TCL_RC_IN_RGB_B_MAPPING_MASK 0x00e00000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT_NV 0x00200000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL_NV 0x00400000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE_NV 0x00600000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL_NV 0x00800000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE_NV 0x00a00000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY_NV 0x00c00000
|
||
|
-#define NV34TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE_NV 0x00e00000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT 0x00200000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL 0x00400000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE 0x00600000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL 0x00800000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE 0x00a00000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY 0x00c00000
|
||
|
+#define NV34TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE 0x00e00000
|
||
|
#define NV34TCL_RC_IN_RGB_A_INPUT_SHIFT 24
|
||
|
#define NV34TCL_RC_IN_RGB_A_INPUT_MASK 0x0f000000
|
||
|
#define NV34TCL_RC_IN_RGB_A_INPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0_NV 0x01000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1_NV 0x02000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0 0x01000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1 0x02000000
|
||
|
#define NV34TCL_RC_IN_RGB_A_INPUT_FOG 0x03000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR_NV 0x04000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR_NV 0x05000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE0_ARB 0x08000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE1_ARB 0x09000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_INPUT_SPARE0_NV 0x0c000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_INPUT_SPARE1_NV 0x0d000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0e000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_INPUT_E_TIMES_F_NV 0x0f000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE2_ARB 0x0a000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE3_ARB 0x0b000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR 0x04000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR 0x05000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE0 0x08000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE1 0x09000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_INPUT_SPARE0 0x0c000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_INPUT_SPARE1 0x0d000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0e000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_INPUT_E_TIMES_F 0x0f000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE2 0x0a000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_INPUT_TEXTURE3 0x0b000000
|
||
|
#define NV34TCL_RC_IN_RGB_A_COMPONENT_USAGE (1 << 28)
|
||
|
#define NV34TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB 0x00000000
|
||
|
#define NV34TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA 0x10000000
|
||
|
#define NV34TCL_RC_IN_RGB_A_MAPPING_SHIFT 29
|
||
|
#define NV34TCL_RC_IN_RGB_A_MAPPING_MASK 0xe0000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY_NV 0x00000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT_NV 0x20000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL_NV 0x40000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE_NV 0x60000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL_NV 0x80000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE_NV 0xa0000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY_NV 0xc0000000
|
||
|
-#define NV34TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE_NV 0xe0000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY 0x00000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT 0x20000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL 0x40000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE 0x60000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL 0x80000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE 0xa0000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY 0xc0000000
|
||
|
+#define NV34TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE 0xe0000000
|
||
|
#define NV34TCL_RC_CONSTANT_COLOR0(x) (0x00000908+((x)*32))
|
||
|
#define NV34TCL_RC_CONSTANT_COLOR0__SIZE 0x00000008
|
||
|
#define NV34TCL_RC_CONSTANT_COLOR0_B_SHIFT 0
|
||
|
@@ -5803,125 +5912,125 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT 0
|
||
|
#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK 0x0000000f
|
||
|
#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG 0x00000003
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0 0x00000008
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1 0x00000009
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0 0x0000000c
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1 0x0000000d
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3 0x0000000b
|
||
|
#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT 4
|
||
|
#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK 0x000000f0
|
||
|
#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0_NV 0x00000010
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1_NV 0x00000020
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0 0x00000010
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1 0x00000020
|
||
|
#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG 0x00000030
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR_NV 0x00000040
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR_NV 0x00000050
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0_ARB 0x00000080
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1_ARB 0x00000090
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_NV 0x000000c0
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1_NV 0x000000d0
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000000e0
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F_NV 0x000000f0
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2_ARB 0x000000a0
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3_ARB 0x000000b0
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR 0x00000040
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR 0x00000050
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0 0x00000080
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1 0x00000090
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0 0x000000c0
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1 0x000000d0
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F 0x000000f0
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2 0x000000a0
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3 0x000000b0
|
||
|
#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT 8
|
||
|
#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK 0x00000f00
|
||
|
#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG 0x00000300
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0 0x00000800
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1 0x00000900
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0 0x00000c00
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1 0x00000d00
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3 0x00000b00
|
||
|
#define NV34TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT (1 << 12)
|
||
|
#define NV34TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT (1 << 13)
|
||
|
#define NV34TCL_RC_OUT_ALPHA_MUX_SUM (1 << 14)
|
||
|
#define NV34TCL_RC_OUT_ALPHA_BIAS (1 << 15)
|
||
|
#define NV34TCL_RC_OUT_ALPHA_BIAS_NONE 0x00000000
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00008000
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000
|
||
|
#define NV34TCL_RC_OUT_ALPHA_SCALE_SHIFT 17
|
||
|
#define NV34TCL_RC_OUT_ALPHA_SCALE_MASK 0x00000000
|
||
|
#define NV34TCL_RC_OUT_ALPHA_SCALE_NONE 0x00000000
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO_NV 0x00020000
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR_NV 0x00040000
|
||
|
-#define NV34TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF_NV 0x00060000
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO 0x00020000
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR 0x00040000
|
||
|
+#define NV34TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF 0x00060000
|
||
|
#define NV34TCL_RC_OUT_RGB(x) (0x00000914+((x)*32))
|
||
|
#define NV34TCL_RC_OUT_RGB__SIZE 0x00000008
|
||
|
#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT 0
|
||
|
#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_MASK 0x0000000f
|
||
|
#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0_NV 0x00000001
|
||
|
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1_NV 0x00000002
|
||
|
+#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0 0x00000001
|
||
|
+#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1 0x00000002
|
||
|
#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_FOG 0x00000003
|
||
|
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR_NV 0x00000004
|
||
|
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR_NV 0x00000005
|
||
|
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0_ARB 0x00000008
|
||
|
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1_ARB 0x00000009
|
||
|
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_NV 0x0000000c
|
||
|
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1_NV 0x0000000d
|
||
|
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x0000000e
|
||
|
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F_NV 0x0000000f
|
||
|
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2_ARB 0x0000000a
|
||
|
-#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3_ARB 0x0000000b
|
||
|
+#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR 0x00000004
|
||
|
+#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR 0x00000005
|
||
|
+#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0 0x00000008
|
||
|
+#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1 0x00000009
|
||
|
+#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0 0x0000000c
|
||
|
+#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1 0x0000000d
|
||
|
+#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x0000000e
|
||
|
+#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F 0x0000000f
|
||
|
+#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2 0x0000000a
|
||
|
+#define NV34TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3 0x0000000b
|
||
|
#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT 4
|
||
|
#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_MASK 0x000000f0
|
||
|
#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0_NV 0x00000010
|
||
|
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1_NV 0x00000020
|
||
|
+#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0 0x00000010
|
||
|
+#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1 0x00000020
|
||
|
#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_FOG 0x00000030
|
||
|
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR_NV 0x00000040
|
||
|
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR_NV 0x00000050
|
||
|
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0_ARB 0x00000080
|
||
|
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1_ARB 0x00000090
|
||
|
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_NV 0x000000c0
|
||
|
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1_NV 0x000000d0
|
||
|
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x000000e0
|
||
|
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F_NV 0x000000f0
|
||
|
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2_ARB 0x000000a0
|
||
|
-#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3_ARB 0x000000b0
|
||
|
+#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR 0x00000040
|
||
|
+#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR 0x00000050
|
||
|
+#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0 0x00000080
|
||
|
+#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1 0x00000090
|
||
|
+#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0 0x000000c0
|
||
|
+#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1 0x000000d0
|
||
|
+#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x000000e0
|
||
|
+#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F 0x000000f0
|
||
|
+#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2 0x000000a0
|
||
|
+#define NV34TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3 0x000000b0
|
||
|
#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT 8
|
||
|
#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_MASK 0x00000f00
|
||
|
#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO 0x00000000
|
||
|
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0_NV 0x00000100
|
||
|
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1_NV 0x00000200
|
||
|
+#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0 0x00000100
|
||
|
+#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1 0x00000200
|
||
|
#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_FOG 0x00000300
|
||
|
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR_NV 0x00000400
|
||
|
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR_NV 0x00000500
|
||
|
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0_ARB 0x00000800
|
||
|
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1_ARB 0x00000900
|
||
|
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_NV 0x00000c00
|
||
|
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1_NV 0x00000d00
|
||
|
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR_NV 0x00000e00
|
||
|
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F_NV 0x00000f00
|
||
|
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2_ARB 0x00000a00
|
||
|
-#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3_ARB 0x00000b00
|
||
|
+#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR 0x00000400
|
||
|
+#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR 0x00000500
|
||
|
+#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0 0x00000800
|
||
|
+#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1 0x00000900
|
||
|
+#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0 0x00000c00
|
||
|
+#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1 0x00000d00
|
||
|
+#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR 0x00000e00
|
||
|
+#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F 0x00000f00
|
||
|
+#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2 0x00000a00
|
||
|
+#define NV34TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3 0x00000b00
|
||
|
#define NV34TCL_RC_OUT_RGB_CD_DOT_PRODUCT (1 << 12)
|
||
|
#define NV34TCL_RC_OUT_RGB_AB_DOT_PRODUCT (1 << 13)
|
||
|
#define NV34TCL_RC_OUT_RGB_MUX_SUM (1 << 14)
|
||
|
#define NV34TCL_RC_OUT_RGB_BIAS (1 << 15)
|
||
|
#define NV34TCL_RC_OUT_RGB_BIAS_NONE 0x00000000
|
||
|
-#define NV34TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF_NV 0x00008000
|
||
|
+#define NV34TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF 0x00008000
|
||
|
#define NV34TCL_RC_OUT_RGB_SCALE_SHIFT 17
|
||
|
#define NV34TCL_RC_OUT_RGB_SCALE_MASK 0x00000000
|
||
|
#define NV34TCL_RC_OUT_RGB_SCALE_NONE 0x00000000
|
||
|
-#define NV34TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO_NV 0x00020000
|
||
|
-#define NV34TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR_NV 0x00040000
|
||
|
-#define NV34TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF_NV 0x00060000
|
||
|
+#define NV34TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO 0x00020000
|
||
|
+#define NV34TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR 0x00040000
|
||
|
+#define NV34TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF 0x00060000
|
||
|
#define NV34TCL_VIEWPORT_HORIZ 0x00000a00
|
||
|
#define NV34TCL_VIEWPORT_HORIZ_X_SHIFT 0
|
||
|
#define NV34TCL_VIEWPORT_HORIZ_X_MASK 0x0000ffff
|
||
|
@@ -5952,7 +6061,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV34TCL_DEPTH_FUNC_EQUAL 0x00000202
|
||
|
#define NV34TCL_DEPTH_FUNC_LEQUAL 0x00000203
|
||
|
#define NV34TCL_DEPTH_FUNC_GREATER 0x00000204
|
||
|
-#define NV34TCL_DEPTH_FUNC_GREATER 0x00000204
|
||
|
#define NV34TCL_DEPTH_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV34TCL_DEPTH_FUNC_GEQUAL 0x00000206
|
||
|
#define NV34TCL_DEPTH_FUNC_ALWAYS 0x00000207
|
||
|
@@ -6095,6 +6203,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV34TCL_FRONT_MATERIAL_SHININESS(x) (0x00001400+((x)*4))
|
||
|
#define NV34TCL_FRONT_MATERIAL_SHININESS__SIZE 0x00000006
|
||
|
#define NV34TCL_ENABLED_LIGHTS 0x00001420
|
||
|
+#define NV34TCL_VERTEX_TWO_SIDE_ENABLE 0x0000142c
|
||
|
#define NV34TCL_FP_REG_CONTROL 0x00001450
|
||
|
#define NV34TCL_FP_REG_CONTROL_UNK1_SHIFT 16
|
||
|
#define NV34TCL_FP_REG_CONTROL_UNK1_MASK 0xffff0000
|
||
|
@@ -6510,30 +6619,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV34TCL_UNK1f80__SIZE 0x00000010
|
||
|
|
||
|
|
||
|
-#define NV40_CONTEXT_SURFACES_2D 0x00003062
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV40_STRETCHED_IMAGE_FROM_CPU 0x00003066
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV40_TEXTURE_FROM_CPU 0x0000307b
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV40_SCALED_IMAGE_FROM_MEMORY 0x00003089
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV40_IMAGE_FROM_CPU 0x0000308a
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NV40_SWIZZLED_SURFACE 0x0000309e
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
#define NV40TCL 0x00004097
|
||
|
|
||
|
#define NV40TCL_REF_CNT 0x00000050
|
||
|
@@ -6613,7 +6698,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV40TCL_ALPHA_TEST_FUNC_EQUAL 0x00000202
|
||
|
#define NV40TCL_ALPHA_TEST_FUNC_LEQUAL 0x00000203
|
||
|
#define NV40TCL_ALPHA_TEST_FUNC_GREATER 0x00000204
|
||
|
-#define NV40TCL_ALPHA_TEST_FUNC_GREATER 0x00000204
|
||
|
#define NV40TCL_ALPHA_TEST_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV40TCL_ALPHA_TEST_FUNC_GEQUAL 0x00000206
|
||
|
#define NV40TCL_ALPHA_TEST_FUNC_ALWAYS 0x00000207
|
||
|
@@ -6730,7 +6814,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_EQUAL 0x00000202
|
||
|
#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_LEQUAL 0x00000203
|
||
|
#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204
|
||
|
-#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204
|
||
|
#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206
|
||
|
#define NV40TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207
|
||
|
@@ -6771,7 +6854,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV40TCL_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202
|
||
|
#define NV40TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203
|
||
|
#define NV40TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
|
||
|
-#define NV40TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
|
||
|
#define NV40TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV40TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206
|
||
|
#define NV40TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207
|
||
|
@@ -6894,7 +6976,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV40TCL_DEPTH_FUNC_EQUAL 0x00000202
|
||
|
#define NV40TCL_DEPTH_FUNC_LEQUAL 0x00000203
|
||
|
#define NV40TCL_DEPTH_FUNC_GREATER 0x00000204
|
||
|
-#define NV40TCL_DEPTH_FUNC_GREATER 0x00000204
|
||
|
#define NV40TCL_DEPTH_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV40TCL_DEPTH_FUNC_GEQUAL 0x00000206
|
||
|
#define NV40TCL_DEPTH_FUNC_ALWAYS 0x00000207
|
||
|
@@ -6935,6 +7016,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV40TCL_UNK0B40__SIZE 0x00000008
|
||
|
#define NV40TCL_VP_UPLOAD_INST(x) (0x00000b80+((x)*4))
|
||
|
#define NV40TCL_VP_UPLOAD_INST__SIZE 0x00000004
|
||
|
+#define NV40TCL_VERTEX_TWO_SIDE_ENABLE 0x0000142c
|
||
|
#define NV40TCL_CLIP_PLANE_ENABLE 0x00001478
|
||
|
#define NV40TCL_CLIP_PLANE_ENABLE_PLANE0 (1 << 1)
|
||
|
#define NV40TCL_CLIP_PLANE_ENABLE_PLANE1 (1 << 5)
|
||
|
@@ -7311,42 +7393,67 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
|
||
|
#define NV50_2D_NOP 0x00000100
|
||
|
#define NV50_2D_NOTIFY 0x00000104
|
||
|
+#define NV50_2D_SERIALIZE 0x00000110
|
||
|
#define NV50_2D_DMA_NOTIFY 0x00000180
|
||
|
-#define NV50_2D_DMA_IN_MEMORY0 0x00000184
|
||
|
-#define NV50_2D_DMA_IN_MEMORY1 0x00000188
|
||
|
-#define NV50_2D_DMA_IN_MEMORY2 0x0000018c
|
||
|
+#define NV50_2D_DMA_DST 0x00000184
|
||
|
+#define NV50_2D_DMA_SRC 0x00000188
|
||
|
+#define NV50_2D_DMA_COND 0x0000018c
|
||
|
#define NV50_2D_DST_FORMAT 0x00000200
|
||
|
#define NV50_2D_DST_FORMAT_R32G32B32A32_FLOAT 0x000000c0
|
||
|
-#define NV50_2D_DST_FORMAT_R32G32B32_FLOAT 0x000000c3
|
||
|
+#define NV50_2D_DST_FORMAT_R32G32B32A32_SINT 0x000000c1
|
||
|
+#define NV50_2D_DST_FORMAT_R32G32B32A32_UINT 0x000000c2
|
||
|
+#define NV50_2D_DST_FORMAT_R32G32B32X32_FLOAT 0x000000c3
|
||
|
#define NV50_2D_DST_FORMAT_R16G16B16A16_UNORM 0x000000c6
|
||
|
#define NV50_2D_DST_FORMAT_R16G16B16A16_SNORM 0x000000c7
|
||
|
+#define NV50_2D_DST_FORMAT_R16G16B16A16_SINT 0x000000c8
|
||
|
+#define NV50_2D_DST_FORMAT_R16G16B16A16_UINT 0x000000c9
|
||
|
#define NV50_2D_DST_FORMAT_R16G16B16A16_FLOAT 0x000000ca
|
||
|
#define NV50_2D_DST_FORMAT_R32G32_FLOAT 0x000000cb
|
||
|
+#define NV50_2D_DST_FORMAT_R32G32_SINT 0x000000cc
|
||
|
+#define NV50_2D_DST_FORMAT_R32G32_UINT 0x000000cd
|
||
|
#define NV50_2D_DST_FORMAT_R16G16B16X16_FLOAT 0x000000ce
|
||
|
#define NV50_2D_DST_FORMAT_A8R8G8B8_UNORM 0x000000cf
|
||
|
+#define NV50_2D_DST_FORMAT_A8R8G8B8_SRGB 0x000000d0
|
||
|
#define NV50_2D_DST_FORMAT_A2B10G10R10_UNORM 0x000000d1
|
||
|
-#define NV50_2D_DST_FORMAT_A8B8G8R8_UNORM 0x000000d6
|
||
|
+#define NV50_2D_DST_FORMAT_A2B10G10R10_UINT 0x000000d2
|
||
|
+#define NV50_2D_DST_FORMAT_A8B8G8R8_UNORM 0x000000d5
|
||
|
+#define NV50_2D_DST_FORMAT_A8B8G8R8_SRGB 0x000000d6
|
||
|
#define NV50_2D_DST_FORMAT_A8B8G8R8_SNORM 0x000000d7
|
||
|
+#define NV50_2D_DST_FORMAT_A8B8G8R8_SINT 0x000000d8
|
||
|
+#define NV50_2D_DST_FORMAT_A8B8G8R8_UINT 0x000000d9
|
||
|
#define NV50_2D_DST_FORMAT_R16G16_UNORM 0x000000da
|
||
|
#define NV50_2D_DST_FORMAT_R16G16_SNORM 0x000000db
|
||
|
+#define NV50_2D_DST_FORMAT_R16G16_SINT 0x000000dc
|
||
|
+#define NV50_2D_DST_FORMAT_R16G16_UINT 0x000000dd
|
||
|
#define NV50_2D_DST_FORMAT_R16G16_FLOAT 0x000000de
|
||
|
#define NV50_2D_DST_FORMAT_A2R10G10B10_UNORM 0x000000df
|
||
|
#define NV50_2D_DST_FORMAT_B10G11R11_FLOAT 0x000000e0
|
||
|
#define NV50_2D_DST_FORMAT_R32_FLOAT 0x000000e5
|
||
|
#define NV50_2D_DST_FORMAT_X8R8G8B8_UNORM 0x000000e6
|
||
|
+#define NV50_2D_DST_FORMAT_X8R8G8B8_SRGB 0x000000e7
|
||
|
#define NV50_2D_DST_FORMAT_R5G6B5_UNORM 0x000000e8
|
||
|
-#define NV50_2D_DST_FORMAT_R16_FLOAT 0x000000e9
|
||
|
+#define NV50_2D_DST_FORMAT_A1R5G5B5_UNORM 0x000000e9
|
||
|
#define NV50_2D_DST_FORMAT_R8G8_UNORM 0x000000ea
|
||
|
#define NV50_2D_DST_FORMAT_R8G8_SNORM 0x000000eb
|
||
|
+#define NV50_2D_DST_FORMAT_R8G8_SINT 0x000000ec
|
||
|
+#define NV50_2D_DST_FORMAT_R8G8_UINT 0x000000ed
|
||
|
#define NV50_2D_DST_FORMAT_R16_UNORM 0x000000ee
|
||
|
#define NV50_2D_DST_FORMAT_R16_SNORM 0x000000ef
|
||
|
+#define NV50_2D_DST_FORMAT_R16_SINT 0x000000f0
|
||
|
+#define NV50_2D_DST_FORMAT_R16_UINT 0x000000f1
|
||
|
+#define NV50_2D_DST_FORMAT_R16_FLOAT 0x000000f2
|
||
|
#define NV50_2D_DST_FORMAT_R8_UNORM 0x000000f3
|
||
|
-#define NV50_2D_DST_FORMAT_R32_BOOLEAN 0x000000f6
|
||
|
+#define NV50_2D_DST_FORMAT_R8_SNORM 0x000000f4
|
||
|
+#define NV50_2D_DST_FORMAT_R8_SINT 0x000000f5
|
||
|
+#define NV50_2D_DST_FORMAT_R8_UINT 0x000000f6
|
||
|
#define NV50_2D_DST_FORMAT_A8_UNORM 0x000000f7
|
||
|
-#define NV50_2D_DST_FORMAT_X1B5G5R5_UNORM 0x000000f8
|
||
|
+#define NV50_2D_DST_FORMAT_X1R5G5B5_UNORM 0x000000f8
|
||
|
#define NV50_2D_DST_FORMAT_X8B8G8R8_UNORM 0x000000f9
|
||
|
+#define NV50_2D_DST_FORMAT_X8B8G8R8_SRGB 0x000000fa
|
||
|
#define NV50_2D_DST_LINEAR 0x00000204
|
||
|
#define NV50_2D_DST_TILE_MODE 0x00000208
|
||
|
+#define NV50_2D_DST_DEPTH 0x0000020c
|
||
|
+#define NV50_2D_DST_LAYER 0x00000210
|
||
|
#define NV50_2D_DST_PITCH 0x00000214
|
||
|
#define NV50_2D_DST_WIDTH 0x00000218
|
||
|
#define NV50_2D_DST_HEIGHT 0x0000021c
|
||
|
@@ -7354,45 +7461,88 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50_2D_DST_ADDRESS_LOW 0x00000224
|
||
|
#define NV50_2D_SRC_FORMAT 0x00000230
|
||
|
#define NV50_2D_SRC_FORMAT_R32G32B32A32_FLOAT 0x000000c0
|
||
|
-#define NV50_2D_SRC_FORMAT_R32G32B32_FLOAT 0x000000c3
|
||
|
+#define NV50_2D_SRC_FORMAT_R32G32B32A32_SINT 0x000000c1
|
||
|
+#define NV50_2D_SRC_FORMAT_R32G32B32A32_UINT 0x000000c2
|
||
|
+#define NV50_2D_SRC_FORMAT_R32G32B32X32_FLOAT 0x000000c3
|
||
|
#define NV50_2D_SRC_FORMAT_R16G16B16A16_UNORM 0x000000c6
|
||
|
#define NV50_2D_SRC_FORMAT_R16G16B16A16_SNORM 0x000000c7
|
||
|
+#define NV50_2D_SRC_FORMAT_R16G16B16A16_SINT 0x000000c8
|
||
|
+#define NV50_2D_SRC_FORMAT_R16G16B16A16_UINT 0x000000c9
|
||
|
#define NV50_2D_SRC_FORMAT_R16G16B16A16_FLOAT 0x000000ca
|
||
|
#define NV50_2D_SRC_FORMAT_R32G32_FLOAT 0x000000cb
|
||
|
+#define NV50_2D_SRC_FORMAT_R32G32_SINT 0x000000cc
|
||
|
+#define NV50_2D_SRC_FORMAT_R32G32_UINT 0x000000cd
|
||
|
#define NV50_2D_SRC_FORMAT_R16G16B16X16_FLOAT 0x000000ce
|
||
|
#define NV50_2D_SRC_FORMAT_A8R8G8B8_UNORM 0x000000cf
|
||
|
+#define NV50_2D_SRC_FORMAT_A8R8G8B8_SRGB 0x000000d0
|
||
|
#define NV50_2D_SRC_FORMAT_A2B10G10R10_UNORM 0x000000d1
|
||
|
-#define NV50_2D_SRC_FORMAT_A8B8G8R8_UNORM 0x000000d6
|
||
|
+#define NV50_2D_SRC_FORMAT_A2B10G10R10_UINT 0x000000d2
|
||
|
+#define NV50_2D_SRC_FORMAT_A8B8G8R8_UNORM 0x000000d5
|
||
|
+#define NV50_2D_SRC_FORMAT_A8B8G8R8_SRGB 0x000000d6
|
||
|
#define NV50_2D_SRC_FORMAT_A8B8G8R8_SNORM 0x000000d7
|
||
|
+#define NV50_2D_SRC_FORMAT_A8B8G8R8_SINT 0x000000d8
|
||
|
+#define NV50_2D_SRC_FORMAT_A8B8G8R8_UINT 0x000000d9
|
||
|
#define NV50_2D_SRC_FORMAT_R16G16_UNORM 0x000000da
|
||
|
#define NV50_2D_SRC_FORMAT_R16G16_SNORM 0x000000db
|
||
|
+#define NV50_2D_SRC_FORMAT_R16G16_SINT 0x000000dc
|
||
|
+#define NV50_2D_SRC_FORMAT_R16G16_UINT 0x000000dd
|
||
|
#define NV50_2D_SRC_FORMAT_R16G16_FLOAT 0x000000de
|
||
|
#define NV50_2D_SRC_FORMAT_A2R10G10B10_UNORM 0x000000df
|
||
|
#define NV50_2D_SRC_FORMAT_B10G11R11_FLOAT 0x000000e0
|
||
|
#define NV50_2D_SRC_FORMAT_R32_FLOAT 0x000000e5
|
||
|
#define NV50_2D_SRC_FORMAT_X8R8G8B8_UNORM 0x000000e6
|
||
|
+#define NV50_2D_SRC_FORMAT_X8R8G8B8_SRGB 0x000000e7
|
||
|
#define NV50_2D_SRC_FORMAT_R5G6B5_UNORM 0x000000e8
|
||
|
-#define NV50_2D_SRC_FORMAT_R16_FLOAT 0x000000e9
|
||
|
+#define NV50_2D_SRC_FORMAT_A1R5G5B5_UNORM 0x000000e9
|
||
|
#define NV50_2D_SRC_FORMAT_R8G8_UNORM 0x000000ea
|
||
|
#define NV50_2D_SRC_FORMAT_R8G8_SNORM 0x000000eb
|
||
|
+#define NV50_2D_SRC_FORMAT_R8G8_SINT 0x000000ec
|
||
|
+#define NV50_2D_SRC_FORMAT_R8G8_UINT 0x000000ed
|
||
|
#define NV50_2D_SRC_FORMAT_R16_UNORM 0x000000ee
|
||
|
#define NV50_2D_SRC_FORMAT_R16_SNORM 0x000000ef
|
||
|
+#define NV50_2D_SRC_FORMAT_R16_SINT 0x000000f0
|
||
|
+#define NV50_2D_SRC_FORMAT_R16_UINT 0x000000f1
|
||
|
+#define NV50_2D_SRC_FORMAT_R16_FLOAT 0x000000f2
|
||
|
#define NV50_2D_SRC_FORMAT_R8_UNORM 0x000000f3
|
||
|
-#define NV50_2D_SRC_FORMAT_R32_BOOLEAN 0x000000f6
|
||
|
+#define NV50_2D_SRC_FORMAT_R8_SNORM 0x000000f4
|
||
|
+#define NV50_2D_SRC_FORMAT_R8_SINT 0x000000f5
|
||
|
+#define NV50_2D_SRC_FORMAT_R8_UINT 0x000000f6
|
||
|
#define NV50_2D_SRC_FORMAT_A8_UNORM 0x000000f7
|
||
|
-#define NV50_2D_SRC_FORMAT_X1B5G5R5_UNORM 0x000000f8
|
||
|
+#define NV50_2D_SRC_FORMAT_X1R5G5B5_UNORM 0x000000f8
|
||
|
#define NV50_2D_SRC_FORMAT_X8B8G8R8_UNORM 0x000000f9
|
||
|
+#define NV50_2D_SRC_FORMAT_X8B8G8R8_SRGB 0x000000fa
|
||
|
#define NV50_2D_SRC_LINEAR 0x00000234
|
||
|
#define NV50_2D_SRC_TILE_MODE 0x00000238
|
||
|
+#define NV50_2D_SRC_DEPTH 0x0000023c
|
||
|
+#define NV50_2D_SRC_LAYER 0x00000240
|
||
|
#define NV50_2D_SRC_PITCH 0x00000244
|
||
|
#define NV50_2D_SRC_WIDTH 0x00000248
|
||
|
#define NV50_2D_SRC_HEIGHT 0x0000024c
|
||
|
#define NV50_2D_SRC_ADDRESS_HIGH 0x00000250
|
||
|
#define NV50_2D_SRC_ADDRESS_LOW 0x00000254
|
||
|
+#define NV50_2D_COND_ADDRESS_HIGH 0x00000264
|
||
|
+#define NV50_2D_COND_ADDRESS_LOW 0x00000268
|
||
|
+#define NV50_2D_COND_MODE 0x0000026c
|
||
|
+#define NV50_2D_COND_MODE_NEVER 0x00000000
|
||
|
+#define NV50_2D_COND_MODE_ALWAYS 0x00000001
|
||
|
+#define NV50_2D_COND_MODE_RES 0x00000002
|
||
|
+#define NV50_2D_COND_MODE_NOT_RES_AND_NOT_ID 0x00000003
|
||
|
+#define NV50_2D_COND_MODE_RES_OR_ID 0x00000004
|
||
|
#define NV50_2D_CLIP_X 0x00000280
|
||
|
#define NV50_2D_CLIP_Y 0x00000284
|
||
|
-#define NV50_2D_CLIP_Z 0x00000288
|
||
|
-#define NV50_2D_CLIP_W 0x0000028c
|
||
|
+#define NV50_2D_CLIP_W 0x00000288
|
||
|
+#define NV50_2D_CLIP_H 0x0000028c
|
||
|
+#define NV50_2D_CLIP_ENABLE 0x00000290
|
||
|
+#define NV50_2D_COLOR_KEY_FORMAT 0x00000294
|
||
|
+#define NV50_2D_COLOR_KEY_FORMAT_16BPP 0x00000000
|
||
|
+#define NV50_2D_COLOR_KEY_FORMAT_15BPP 0x00000001
|
||
|
+#define NV50_2D_COLOR_KEY_FORMAT_24BPP 0x00000002
|
||
|
+#define NV50_2D_COLOR_KEY_FORMAT_30BPP 0x00000003
|
||
|
+#define NV50_2D_COLOR_KEY_FORMAT_8BPP 0x00000004
|
||
|
+#define NV50_2D_COLOR_KEY_FORMAT_16BPP2 0x00000005
|
||
|
+#define NV50_2D_COLOR_KEY_FORMAT_32BPP 0x00000006
|
||
|
+#define NV50_2D_COLOR_KEY 0x00000298
|
||
|
+#define NV50_2D_COLOR_KEY_ENABLE 0x0000029c
|
||
|
#define NV50_2D_ROP 0x000002a0
|
||
|
#define NV50_2D_OPERATION 0x000002ac
|
||
|
#define NV50_2D_OPERATION_SRCCOPY_AND 0x00000000
|
||
|
@@ -7410,122 +7560,180 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50_2D_PATTERN_COLOR__SIZE 0x00000002
|
||
|
#define NV50_2D_PATTERN_BITMAP(x) (0x000002f8+((x)*4))
|
||
|
#define NV50_2D_PATTERN_BITMAP__SIZE 0x00000002
|
||
|
-#define NV50_2D_RECT_FORMAT 0x00000584
|
||
|
-#define NV50_2D_RECT_FORMAT_R32G32B32A32_FLOAT 0x000000c0
|
||
|
-#define NV50_2D_RECT_FORMAT_R32G32B32_FLOAT 0x000000c3
|
||
|
-#define NV50_2D_RECT_FORMAT_R16G16B16A16_UNORM 0x000000c6
|
||
|
-#define NV50_2D_RECT_FORMAT_R16G16B16A16_SNORM 0x000000c7
|
||
|
-#define NV50_2D_RECT_FORMAT_R16G16B16A16_FLOAT 0x000000ca
|
||
|
-#define NV50_2D_RECT_FORMAT_R32G32_FLOAT 0x000000cb
|
||
|
-#define NV50_2D_RECT_FORMAT_R16G16B16X16_FLOAT 0x000000ce
|
||
|
-#define NV50_2D_RECT_FORMAT_A8R8G8B8_UNORM 0x000000cf
|
||
|
-#define NV50_2D_RECT_FORMAT_A2B10G10R10_UNORM 0x000000d1
|
||
|
-#define NV50_2D_RECT_FORMAT_A8B8G8R8_UNORM 0x000000d6
|
||
|
-#define NV50_2D_RECT_FORMAT_A8B8G8R8_SNORM 0x000000d7
|
||
|
-#define NV50_2D_RECT_FORMAT_R16G16_UNORM 0x000000da
|
||
|
-#define NV50_2D_RECT_FORMAT_R16G16_SNORM 0x000000db
|
||
|
-#define NV50_2D_RECT_FORMAT_R16G16_FLOAT 0x000000de
|
||
|
-#define NV50_2D_RECT_FORMAT_A2R10G10B10_UNORM 0x000000df
|
||
|
-#define NV50_2D_RECT_FORMAT_B10G11R11_FLOAT 0x000000e0
|
||
|
-#define NV50_2D_RECT_FORMAT_R32_FLOAT 0x000000e5
|
||
|
-#define NV50_2D_RECT_FORMAT_X8R8G8B8_UNORM 0x000000e6
|
||
|
-#define NV50_2D_RECT_FORMAT_R5G6B5_UNORM 0x000000e8
|
||
|
-#define NV50_2D_RECT_FORMAT_R16_FLOAT 0x000000e9
|
||
|
-#define NV50_2D_RECT_FORMAT_R8G8_UNORM 0x000000ea
|
||
|
-#define NV50_2D_RECT_FORMAT_R8G8_SNORM 0x000000eb
|
||
|
-#define NV50_2D_RECT_FORMAT_R16_UNORM 0x000000ee
|
||
|
-#define NV50_2D_RECT_FORMAT_R16_SNORM 0x000000ef
|
||
|
-#define NV50_2D_RECT_FORMAT_R8_UNORM 0x000000f3
|
||
|
-#define NV50_2D_RECT_FORMAT_R32_BOOLEAN 0x000000f6
|
||
|
-#define NV50_2D_RECT_FORMAT_A8_UNORM 0x000000f7
|
||
|
-#define NV50_2D_RECT_FORMAT_X1B5G5R5_UNORM 0x000000f8
|
||
|
-#define NV50_2D_RECT_FORMAT_X8B8G8R8_UNORM 0x000000f9
|
||
|
-#define NV50_2D_RECT_COLOR 0x00000588
|
||
|
-#define NV50_2D_RECT_X1 0x00000600
|
||
|
-#define NV50_2D_RECT_Y1 0x00000604
|
||
|
-#define NV50_2D_RECT_X2 0x00000608
|
||
|
-#define NV50_2D_RECT_Y2 0x0000060c
|
||
|
-#define NV50_2D_SIFC_UNK0800 0x00000800
|
||
|
+#define NV50_2D_DRAW_SHAPE 0x00000580
|
||
|
+#define NV50_2D_DRAW_SHAPE_POINTS 0x00000000
|
||
|
+#define NV50_2D_DRAW_SHAPE_LINES 0x00000001
|
||
|
+#define NV50_2D_DRAW_SHAPE_LINE_STRIP 0x00000002
|
||
|
+#define NV50_2D_DRAW_SHAPE_TRIANGLES 0x00000003
|
||
|
+#define NV50_2D_DRAW_SHAPE_RECTANGLES 0x00000004
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT 0x00000584
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R32G32B32A32_FLOAT 0x000000c0
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R32G32B32A32_SINT 0x000000c1
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R32G32B32A32_UINT 0x000000c2
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R32G32B32X32_FLOAT 0x000000c3
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_UNORM 0x000000c6
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_SNORM 0x000000c7
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_SINT 0x000000c8
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_UINT 0x000000c9
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16A16_FLOAT 0x000000ca
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R32G32_FLOAT 0x000000cb
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R32G32_SINT 0x000000cc
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R32G32_UINT 0x000000cd
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16G16B16X16_FLOAT 0x000000ce
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_A8R8G8B8_UNORM 0x000000cf
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_A8R8G8B8_SRGB 0x000000d0
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_A2B10G10R10_UNORM 0x000000d1
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_A2B10G10R10_UINT 0x000000d2
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_UNORM 0x000000d5
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_SRGB 0x000000d6
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_SNORM 0x000000d7
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_SINT 0x000000d8
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_A8B8G8R8_UINT 0x000000d9
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_UNORM 0x000000da
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_SNORM 0x000000db
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_SINT 0x000000dc
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_UINT 0x000000dd
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16G16_FLOAT 0x000000de
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_A2R10G10B10_UNORM 0x000000df
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_B10G11R11_FLOAT 0x000000e0
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R32_FLOAT 0x000000e5
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_X8R8G8B8_UNORM 0x000000e6
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_X8R8G8B8_SRGB 0x000000e7
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R5G6B5_UNORM 0x000000e8
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_A1R5G5B5_UNORM 0x000000e9
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R8G8_UNORM 0x000000ea
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R8G8_SNORM 0x000000eb
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R8G8_SINT 0x000000ec
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R8G8_UINT 0x000000ed
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16_UNORM 0x000000ee
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16_SNORM 0x000000ef
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16_SINT 0x000000f0
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16_UINT 0x000000f1
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R16_FLOAT 0x000000f2
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R8_UNORM 0x000000f3
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R8_SNORM 0x000000f4
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R8_SINT 0x000000f5
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_R8_UINT 0x000000f6
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_A8_UNORM 0x000000f7
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_X1R5G5B5_UNORM 0x000000f8
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_X8B8G8R8_UNORM 0x000000f9
|
||
|
+#define NV50_2D_DRAW_COLOR_FORMAT_X8B8G8R8_SRGB 0x000000fa
|
||
|
+#define NV50_2D_DRAW_COLOR 0x00000588
|
||
|
+#define NV50_2D_DRAW_POINT16 0x000005e0
|
||
|
+#define NV50_2D_DRAW_POINT16_X_SHIFT 0
|
||
|
+#define NV50_2D_DRAW_POINT16_X_MASK 0x0000ffff
|
||
|
+#define NV50_2D_DRAW_POINT16_Y_SHIFT 16
|
||
|
+#define NV50_2D_DRAW_POINT16_Y_MASK 0xffff0000
|
||
|
+#define NV50_2D_DRAW_POINT32_X(x) (0x00000600+((x)*8))
|
||
|
+#define NV50_2D_DRAW_POINT32_X__SIZE 0x00000040
|
||
|
+#define NV50_2D_DRAW_POINT32_Y(x) (0x00000604+((x)*8))
|
||
|
+#define NV50_2D_DRAW_POINT32_Y__SIZE 0x00000040
|
||
|
+#define NV50_2D_SIFC_BITMAP_ENABLE 0x00000800
|
||
|
#define NV50_2D_SIFC_FORMAT 0x00000804
|
||
|
#define NV50_2D_SIFC_FORMAT_R32G32B32A32_FLOAT 0x000000c0
|
||
|
-#define NV50_2D_SIFC_FORMAT_R32G32B32_FLOAT 0x000000c3
|
||
|
+#define NV50_2D_SIFC_FORMAT_R32G32B32A32_SINT 0x000000c1
|
||
|
+#define NV50_2D_SIFC_FORMAT_R32G32B32A32_UINT 0x000000c2
|
||
|
+#define NV50_2D_SIFC_FORMAT_R32G32B32X32_FLOAT 0x000000c3
|
||
|
#define NV50_2D_SIFC_FORMAT_R16G16B16A16_UNORM 0x000000c6
|
||
|
#define NV50_2D_SIFC_FORMAT_R16G16B16A16_SNORM 0x000000c7
|
||
|
+#define NV50_2D_SIFC_FORMAT_R16G16B16A16_SINT 0x000000c8
|
||
|
+#define NV50_2D_SIFC_FORMAT_R16G16B16A16_UINT 0x000000c9
|
||
|
#define NV50_2D_SIFC_FORMAT_R16G16B16A16_FLOAT 0x000000ca
|
||
|
#define NV50_2D_SIFC_FORMAT_R32G32_FLOAT 0x000000cb
|
||
|
+#define NV50_2D_SIFC_FORMAT_R32G32_SINT 0x000000cc
|
||
|
+#define NV50_2D_SIFC_FORMAT_R32G32_UINT 0x000000cd
|
||
|
#define NV50_2D_SIFC_FORMAT_R16G16B16X16_FLOAT 0x000000ce
|
||
|
#define NV50_2D_SIFC_FORMAT_A8R8G8B8_UNORM 0x000000cf
|
||
|
+#define NV50_2D_SIFC_FORMAT_A8R8G8B8_SRGB 0x000000d0
|
||
|
#define NV50_2D_SIFC_FORMAT_A2B10G10R10_UNORM 0x000000d1
|
||
|
-#define NV50_2D_SIFC_FORMAT_A8B8G8R8_UNORM 0x000000d6
|
||
|
+#define NV50_2D_SIFC_FORMAT_A2B10G10R10_UINT 0x000000d2
|
||
|
+#define NV50_2D_SIFC_FORMAT_A8B8G8R8_UNORM 0x000000d5
|
||
|
+#define NV50_2D_SIFC_FORMAT_A8B8G8R8_SRGB 0x000000d6
|
||
|
#define NV50_2D_SIFC_FORMAT_A8B8G8R8_SNORM 0x000000d7
|
||
|
+#define NV50_2D_SIFC_FORMAT_A8B8G8R8_SINT 0x000000d8
|
||
|
+#define NV50_2D_SIFC_FORMAT_A8B8G8R8_UINT 0x000000d9
|
||
|
#define NV50_2D_SIFC_FORMAT_R16G16_UNORM 0x000000da
|
||
|
#define NV50_2D_SIFC_FORMAT_R16G16_SNORM 0x000000db
|
||
|
+#define NV50_2D_SIFC_FORMAT_R16G16_SINT 0x000000dc
|
||
|
+#define NV50_2D_SIFC_FORMAT_R16G16_UINT 0x000000dd
|
||
|
#define NV50_2D_SIFC_FORMAT_R16G16_FLOAT 0x000000de
|
||
|
#define NV50_2D_SIFC_FORMAT_A2R10G10B10_UNORM 0x000000df
|
||
|
#define NV50_2D_SIFC_FORMAT_B10G11R11_FLOAT 0x000000e0
|
||
|
#define NV50_2D_SIFC_FORMAT_R32_FLOAT 0x000000e5
|
||
|
#define NV50_2D_SIFC_FORMAT_X8R8G8B8_UNORM 0x000000e6
|
||
|
+#define NV50_2D_SIFC_FORMAT_X8R8G8B8_SRGB 0x000000e7
|
||
|
#define NV50_2D_SIFC_FORMAT_R5G6B5_UNORM 0x000000e8
|
||
|
-#define NV50_2D_SIFC_FORMAT_R16_FLOAT 0x000000e9
|
||
|
+#define NV50_2D_SIFC_FORMAT_A1R5G5B5_UNORM 0x000000e9
|
||
|
#define NV50_2D_SIFC_FORMAT_R8G8_UNORM 0x000000ea
|
||
|
#define NV50_2D_SIFC_FORMAT_R8G8_SNORM 0x000000eb
|
||
|
+#define NV50_2D_SIFC_FORMAT_R8G8_SINT 0x000000ec
|
||
|
+#define NV50_2D_SIFC_FORMAT_R8G8_UINT 0x000000ed
|
||
|
#define NV50_2D_SIFC_FORMAT_R16_UNORM 0x000000ee
|
||
|
#define NV50_2D_SIFC_FORMAT_R16_SNORM 0x000000ef
|
||
|
+#define NV50_2D_SIFC_FORMAT_R16_SINT 0x000000f0
|
||
|
+#define NV50_2D_SIFC_FORMAT_R16_UINT 0x000000f1
|
||
|
+#define NV50_2D_SIFC_FORMAT_R16_FLOAT 0x000000f2
|
||
|
#define NV50_2D_SIFC_FORMAT_R8_UNORM 0x000000f3
|
||
|
-#define NV50_2D_SIFC_FORMAT_R32_BOOLEAN 0x000000f6
|
||
|
+#define NV50_2D_SIFC_FORMAT_R8_SNORM 0x000000f4
|
||
|
+#define NV50_2D_SIFC_FORMAT_R8_SINT 0x000000f5
|
||
|
+#define NV50_2D_SIFC_FORMAT_R8_UINT 0x000000f6
|
||
|
#define NV50_2D_SIFC_FORMAT_A8_UNORM 0x000000f7
|
||
|
-#define NV50_2D_SIFC_FORMAT_X1B5G5R5_UNORM 0x000000f8
|
||
|
+#define NV50_2D_SIFC_FORMAT_X1R5G5B5_UNORM 0x000000f8
|
||
|
#define NV50_2D_SIFC_FORMAT_X8B8G8R8_UNORM 0x000000f9
|
||
|
+#define NV50_2D_SIFC_FORMAT_X8B8G8R8_SRGB 0x000000fa
|
||
|
+#define NV50_2D_SIFC_BITMAP_UNK808 0x00000808
|
||
|
+#define NV50_2D_SIFC_BITMAP_LSB_FIRST 0x0000080c
|
||
|
+#define NV50_2D_SIFC_BITMAP_LINE_PACK_MODE 0x00000810
|
||
|
+#define NV50_2D_SIFC_BITMAP_LINE_PACK_MODE_PACKED 0x00000000
|
||
|
+#define NV50_2D_SIFC_BITMAP_LINE_PACK_MODE_ALIGN_BYTE 0x00000001
|
||
|
+#define NV50_2D_SIFC_BITMAP_LINE_PACK_MODE_ALIGN_WORD 0x00000002
|
||
|
+#define NV50_2D_SIFC_BITMAP_COLOR_BIT0 0x00000814
|
||
|
+#define NV50_2D_SIFC_BITMAP_COLOR_BIT1 0x00000818
|
||
|
+#define NV50_2D_SIFC_BITMAP_WRITE_BIT0_ENABLE 0x0000081c
|
||
|
#define NV50_2D_SIFC_WIDTH 0x00000838
|
||
|
#define NV50_2D_SIFC_HEIGHT 0x0000083c
|
||
|
-#define NV50_2D_SIFC_SCALE_UNK0840 0x00000840
|
||
|
-#define NV50_2D_SIFC_SCALE_UNK0844 0x00000844
|
||
|
-#define NV50_2D_SIFC_SCALE_UNK0848 0x00000848
|
||
|
-#define NV50_2D_SIFC_SCALE_UNK084C 0x0000084c
|
||
|
-#define NV50_2D_SIFC_UNK0850 0x00000850
|
||
|
-#define NV50_2D_SIFC_DST_X 0x00000854
|
||
|
-#define NV50_2D_SIFC_UNK0858 0x00000858
|
||
|
-#define NV50_2D_SIFC_DST_Y 0x0000085c
|
||
|
+#define NV50_2D_SIFC_DX_DU_FRACT 0x00000840
|
||
|
+#define NV50_2D_SIFC_DX_DU_INT 0x00000844
|
||
|
+#define NV50_2D_SIFC_DY_DV_FRACT 0x00000848
|
||
|
+#define NV50_2D_SIFC_DY_DV_INT 0x0000084c
|
||
|
+#define NV50_2D_SIFC_DST_X_FRACT 0x00000850
|
||
|
+#define NV50_2D_SIFC_DST_X_INT 0x00000854
|
||
|
+#define NV50_2D_SIFC_DST_Y_FRACT 0x00000858
|
||
|
+#define NV50_2D_SIFC_DST_Y_INT 0x0000085c
|
||
|
#define NV50_2D_SIFC_DATA 0x00000860
|
||
|
#define NV50_2D_BLIT_DST_X 0x000008b0
|
||
|
#define NV50_2D_BLIT_DST_Y 0x000008b4
|
||
|
#define NV50_2D_BLIT_DST_W 0x000008b8
|
||
|
#define NV50_2D_BLIT_DST_H 0x000008bc
|
||
|
-#define NV50_2D_BLIT_SRC_X 0x000008d4
|
||
|
-#define NV50_2D_BLIT_SRC_Y 0x000008dc
|
||
|
-
|
||
|
-
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
|
||
|
-
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_IN 0x00000200
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_IN 0x00000204
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_IN 0x00000208
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_IN 0x0000020c
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN 0x00000218
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_OUT 0x0000021c
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_OUT 0x00000220
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_OUT 0x00000224
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_OUT 0x00000228
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT 0x00000234
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT 0x00000310
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_PITCH_IN 0x00000314
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT 0x00000318
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN 0x0000031c
|
||
|
-#define NV50_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT 0x00000320
|
||
|
+#define NV50_2D_BLIT_DU_DX_FRACT 0x000008c0
|
||
|
+#define NV50_2D_BLIT_DU_DX_INT 0x000008c4
|
||
|
+#define NV50_2D_BLIT_DV_DY_FRACT 0x000008c8
|
||
|
+#define NV50_2D_BLIT_DV_DY_INT 0x000008cc
|
||
|
+#define NV50_2D_BLIT_SRC_X_FRACT 0x000008d0
|
||
|
+#define NV50_2D_BLIT_SRC_X_INT 0x000008d4
|
||
|
+#define NV50_2D_BLIT_SRC_Y_FRACT 0x000008d8
|
||
|
+#define NV50_2D_BLIT_SRC_Y_INT 0x000008dc
|
||
|
|
||
|
|
||
|
#define NV50TCL 0x00005097
|
||
|
|
||
|
#define NV50TCL_NOP 0x00000100
|
||
|
#define NV50TCL_NOTIFY 0x00000104
|
||
|
+#define NV50TCL_SERIALIZE 0x00000110
|
||
|
#define NV50TCL_DMA_NOTIFY 0x00000180
|
||
|
-#define NV50TCL_DMA_UNK0(x) (0x00000184+((x)*4))
|
||
|
-#define NV50TCL_DMA_UNK0__SIZE 0x0000000b
|
||
|
-#define NV50TCL_DMA_UNK1(x) (0x000001c0+((x)*4))
|
||
|
-#define NV50TCL_DMA_UNK1__SIZE 0x00000008
|
||
|
+#define NV50TCL_DMA_ZETA 0x00000184
|
||
|
+#define NV50TCL_DMA_QUERY 0x00000188
|
||
|
+#define NV50TCL_DMA_VTXBUF0 0x0000018c
|
||
|
+#define NV50TCL_DMA_LOCAL 0x00000190
|
||
|
+#define NV50TCL_DMA_STACK 0x00000194
|
||
|
+#define NV50TCL_DMA_CODE_CB 0x00000198
|
||
|
+#define NV50TCL_DMA_TSC 0x0000019c
|
||
|
+#define NV50TCL_DMA_TIC 0x000001a0
|
||
|
+#define NV50TCL_DMA_TEXTURE 0x000001a4
|
||
|
+#define NV50TCL_DMA_STRMOUT 0x000001a8
|
||
|
+#define NV50TCL_DMA_UNK01AC 0x000001ac
|
||
|
+#define NV50TCL_DMA_COLOR(x) (0x000001c0+((x)*4))
|
||
|
+#define NV50TCL_DMA_COLOR__SIZE 0x00000008
|
||
|
#define NV50TCL_RT_ADDRESS_HIGH(x) (0x00000200+((x)*32))
|
||
|
#define NV50TCL_RT_ADDRESS_HIGH__SIZE 0x00000008
|
||
|
#define NV50TCL_RT_ADDRESS_LOW(x) (0x00000204+((x)*32))
|
||
|
@@ -7533,40 +7741,68 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_RT_FORMAT(x) (0x00000208+((x)*32))
|
||
|
#define NV50TCL_RT_FORMAT__SIZE 0x00000008
|
||
|
#define NV50TCL_RT_FORMAT_R32G32B32A32_FLOAT 0x000000c0
|
||
|
-#define NV50TCL_RT_FORMAT_R32G32B32_FLOAT 0x000000c3
|
||
|
+#define NV50TCL_RT_FORMAT_R32G32B32A32_SINT 0x000000c1
|
||
|
+#define NV50TCL_RT_FORMAT_R32G32B32A32_UINT 0x000000c2
|
||
|
+#define NV50TCL_RT_FORMAT_R32G32B32X32_FLOAT 0x000000c3
|
||
|
#define NV50TCL_RT_FORMAT_R16G16B16A16_UNORM 0x000000c6
|
||
|
#define NV50TCL_RT_FORMAT_R16G16B16A16_SNORM 0x000000c7
|
||
|
+#define NV50TCL_RT_FORMAT_R16G16B16A16_SINT 0x000000c8
|
||
|
+#define NV50TCL_RT_FORMAT_R16G16B16A16_UINT 0x000000c9
|
||
|
#define NV50TCL_RT_FORMAT_R16G16B16A16_FLOAT 0x000000ca
|
||
|
#define NV50TCL_RT_FORMAT_R32G32_FLOAT 0x000000cb
|
||
|
+#define NV50TCL_RT_FORMAT_R32G32_SINT 0x000000cc
|
||
|
+#define NV50TCL_RT_FORMAT_R32G32_UINT 0x000000cd
|
||
|
#define NV50TCL_RT_FORMAT_R16G16B16X16_FLOAT 0x000000ce
|
||
|
#define NV50TCL_RT_FORMAT_A8R8G8B8_UNORM 0x000000cf
|
||
|
+#define NV50TCL_RT_FORMAT_A8R8G8B8_SRGB 0x000000d0
|
||
|
#define NV50TCL_RT_FORMAT_A2B10G10R10_UNORM 0x000000d1
|
||
|
-#define NV50TCL_RT_FORMAT_A8B8G8R8_UNORM 0x000000d6
|
||
|
+#define NV50TCL_RT_FORMAT_A2B10G10R10_UINT 0x000000d2
|
||
|
+#define NV50TCL_RT_FORMAT_A8B8G8R8_UNORM 0x000000d5
|
||
|
+#define NV50TCL_RT_FORMAT_A8B8G8R8_SRGB 0x000000d6
|
||
|
#define NV50TCL_RT_FORMAT_A8B8G8R8_SNORM 0x000000d7
|
||
|
+#define NV50TCL_RT_FORMAT_A8B8G8R8_SINT 0x000000d8
|
||
|
+#define NV50TCL_RT_FORMAT_A8B8G8R8_UINT 0x000000d9
|
||
|
#define NV50TCL_RT_FORMAT_R16G16_UNORM 0x000000da
|
||
|
#define NV50TCL_RT_FORMAT_R16G16_SNORM 0x000000db
|
||
|
+#define NV50TCL_RT_FORMAT_R16G16_SINT 0x000000dc
|
||
|
+#define NV50TCL_RT_FORMAT_R16G16_UINT 0x000000dd
|
||
|
#define NV50TCL_RT_FORMAT_R16G16_FLOAT 0x000000de
|
||
|
#define NV50TCL_RT_FORMAT_A2R10G10B10_UNORM 0x000000df
|
||
|
#define NV50TCL_RT_FORMAT_B10G11R11_FLOAT 0x000000e0
|
||
|
#define NV50TCL_RT_FORMAT_R32_FLOAT 0x000000e5
|
||
|
#define NV50TCL_RT_FORMAT_X8R8G8B8_UNORM 0x000000e6
|
||
|
+#define NV50TCL_RT_FORMAT_X8R8G8B8_SRGB 0x000000e7
|
||
|
#define NV50TCL_RT_FORMAT_R5G6B5_UNORM 0x000000e8
|
||
|
-#define NV50TCL_RT_FORMAT_R16_FLOAT 0x000000e9
|
||
|
+#define NV50TCL_RT_FORMAT_A1R5G5B5_UNORM 0x000000e9
|
||
|
#define NV50TCL_RT_FORMAT_R8G8_UNORM 0x000000ea
|
||
|
#define NV50TCL_RT_FORMAT_R8G8_SNORM 0x000000eb
|
||
|
+#define NV50TCL_RT_FORMAT_R8G8_SINT 0x000000ec
|
||
|
+#define NV50TCL_RT_FORMAT_R8G8_UINT 0x000000ed
|
||
|
#define NV50TCL_RT_FORMAT_R16_UNORM 0x000000ee
|
||
|
#define NV50TCL_RT_FORMAT_R16_SNORM 0x000000ef
|
||
|
+#define NV50TCL_RT_FORMAT_R16_SINT 0x000000f0
|
||
|
+#define NV50TCL_RT_FORMAT_R16_UINT 0x000000f1
|
||
|
+#define NV50TCL_RT_FORMAT_R16_FLOAT 0x000000f2
|
||
|
#define NV50TCL_RT_FORMAT_R8_UNORM 0x000000f3
|
||
|
-#define NV50TCL_RT_FORMAT_R32_BOOLEAN 0x000000f6
|
||
|
+#define NV50TCL_RT_FORMAT_R8_SNORM 0x000000f4
|
||
|
+#define NV50TCL_RT_FORMAT_R8_SINT 0x000000f5
|
||
|
+#define NV50TCL_RT_FORMAT_R8_UINT 0x000000f6
|
||
|
#define NV50TCL_RT_FORMAT_A8_UNORM 0x000000f7
|
||
|
-#define NV50TCL_RT_FORMAT_X1B5G5R5_UNORM 0x000000f8
|
||
|
+#define NV50TCL_RT_FORMAT_X1R5G5B5_UNORM 0x000000f8
|
||
|
#define NV50TCL_RT_FORMAT_X8B8G8R8_UNORM 0x000000f9
|
||
|
+#define NV50TCL_RT_FORMAT_X8B8G8R8_SRGB 0x000000fa
|
||
|
#define NV50TCL_RT_TILE_MODE(x) (0x0000020c+((x)*32))
|
||
|
#define NV50TCL_RT_TILE_MODE__SIZE 0x00000008
|
||
|
-#define NV50TCL_RT_UNK4(x) (0x00000210+((x)*32))
|
||
|
-#define NV50TCL_RT_UNK4__SIZE 0x00000008
|
||
|
+#define NV50TCL_RT_LAYER_STRIDE(x) (0x00000210+((x)*32))
|
||
|
+#define NV50TCL_RT_LAYER_STRIDE__SIZE 0x00000008
|
||
|
#define NV50TCL_VTX_ATTR_1F(x) (0x00000300+((x)*4))
|
||
|
#define NV50TCL_VTX_ATTR_1F__SIZE 0x00000010
|
||
|
+#define NV50TCL_VTX_ATTR_2H(x) (0x00000340+((x)*4))
|
||
|
+#define NV50TCL_VTX_ATTR_2H__SIZE 0x00000010
|
||
|
+#define NV50TCL_VTX_ATTR_2H_X_SHIFT 0
|
||
|
+#define NV50TCL_VTX_ATTR_2H_X_MASK 0x0000ffff
|
||
|
+#define NV50TCL_VTX_ATTR_2H_Y_SHIFT 16
|
||
|
+#define NV50TCL_VTX_ATTR_2H_Y_MASK 0xffff0000
|
||
|
#define NV50TCL_VTX_ATTR_2F_X(x) (0x00000380+((x)*8))
|
||
|
#define NV50TCL_VTX_ATTR_2F_X__SIZE 0x00000010
|
||
|
#define NV50TCL_VTX_ATTR_2F_Y(x) (0x00000384+((x)*8))
|
||
|
@@ -7577,8 +7813,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_VTX_ATTR_3F_Y__SIZE 0x00000010
|
||
|
#define NV50TCL_VTX_ATTR_3F_Z(x) (0x00000408+((x)*16))
|
||
|
#define NV50TCL_VTX_ATTR_3F_Z__SIZE 0x00000010
|
||
|
-#define NV50TCL_VTX_ATTR_3F_W(x) (0x0000040c+((x)*16))
|
||
|
-#define NV50TCL_VTX_ATTR_3F_W__SIZE 0x00000010
|
||
|
#define NV50TCL_VTX_ATTR_4F_X(x) (0x00000500+((x)*16))
|
||
|
#define NV50TCL_VTX_ATTR_4F_X__SIZE 0x00000010
|
||
|
#define NV50TCL_VTX_ATTR_4F_Y(x) (0x00000504+((x)*16))
|
||
|
@@ -7587,12 +7821,30 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_VTX_ATTR_4F_Z__SIZE 0x00000010
|
||
|
#define NV50TCL_VTX_ATTR_4F_W(x) (0x0000050c+((x)*16))
|
||
|
#define NV50TCL_VTX_ATTR_4F_W__SIZE 0x00000010
|
||
|
+#define NV50TCL_VTX_ATTR_4H_0(x) (0x00000600+((x)*8))
|
||
|
+#define NV50TCL_VTX_ATTR_4H_0__SIZE 0x00000010
|
||
|
+#define NV50TCL_VTX_ATTR_4H_0_X_SHIFT 0
|
||
|
+#define NV50TCL_VTX_ATTR_4H_0_X_MASK 0x0000ffff
|
||
|
+#define NV50TCL_VTX_ATTR_4H_0_Y_SHIFT 16
|
||
|
+#define NV50TCL_VTX_ATTR_4H_0_Y_MASK 0xffff0000
|
||
|
+#define NV50TCL_VTX_ATTR_4H_1(x) (0x00000604+((x)*8))
|
||
|
+#define NV50TCL_VTX_ATTR_4H_1__SIZE 0x00000010
|
||
|
+#define NV50TCL_VTX_ATTR_4H_1_Z_SHIFT 0
|
||
|
+#define NV50TCL_VTX_ATTR_4H_1_Z_MASK 0x0000ffff
|
||
|
+#define NV50TCL_VTX_ATTR_4H_1_W_SHIFT 16
|
||
|
+#define NV50TCL_VTX_ATTR_4H_1_W_MASK 0xffff0000
|
||
|
#define NV50TCL_VTX_ATTR_2I(x) (0x00000680+((x)*4))
|
||
|
#define NV50TCL_VTX_ATTR_2I__SIZE 0x00000010
|
||
|
#define NV50TCL_VTX_ATTR_2I_X_SHIFT 0
|
||
|
#define NV50TCL_VTX_ATTR_2I_X_MASK 0x0000ffff
|
||
|
#define NV50TCL_VTX_ATTR_2I_Y_SHIFT 16
|
||
|
#define NV50TCL_VTX_ATTR_2I_Y_MASK 0xffff0000
|
||
|
+#define NV50TCL_VTX_ATTR_2NI(x) (0x000006c0+((x)*4))
|
||
|
+#define NV50TCL_VTX_ATTR_2NI__SIZE 0x00000010
|
||
|
+#define NV50TCL_VTX_ATTR_2NI_X_SHIFT 0
|
||
|
+#define NV50TCL_VTX_ATTR_2NI_X_MASK 0x0000ffff
|
||
|
+#define NV50TCL_VTX_ATTR_2NI_Y_SHIFT 16
|
||
|
+#define NV50TCL_VTX_ATTR_2NI_Y_MASK 0xffff0000
|
||
|
#define NV50TCL_VTX_ATTR_4I_0(x) (0x00000700+((x)*8))
|
||
|
#define NV50TCL_VTX_ATTR_4I_0__SIZE 0x00000010
|
||
|
#define NV50TCL_VTX_ATTR_4I_0_X_SHIFT 0
|
||
|
@@ -7617,30 +7869,83 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_VTX_ATTR_4NI_1_Z_MASK 0x0000ffff
|
||
|
#define NV50TCL_VTX_ATTR_4NI_1_W_SHIFT 16
|
||
|
#define NV50TCL_VTX_ATTR_4NI_1_W_MASK 0xffff0000
|
||
|
+#define NV50TCL_VTX_ATTR_4UB(x) (0x00000800+((x)*4))
|
||
|
+#define NV50TCL_VTX_ATTR_4UB__SIZE 0x00000010
|
||
|
+#define NV50TCL_VTX_ATTR_4UB_X_SHIFT 0
|
||
|
+#define NV50TCL_VTX_ATTR_4UB_X_MASK 0x000000ff
|
||
|
+#define NV50TCL_VTX_ATTR_4UB_Y_SHIFT 8
|
||
|
+#define NV50TCL_VTX_ATTR_4UB_Y_MASK 0x0000ff00
|
||
|
+#define NV50TCL_VTX_ATTR_4UB_Z_SHIFT 16
|
||
|
+#define NV50TCL_VTX_ATTR_4UB_Z_MASK 0x00ff0000
|
||
|
+#define NV50TCL_VTX_ATTR_4UB_W_SHIFT 24
|
||
|
+#define NV50TCL_VTX_ATTR_4UB_W_MASK 0xff000000
|
||
|
+#define NV50TCL_VTX_ATTR_4B(x) (0x00000840+((x)*4))
|
||
|
+#define NV50TCL_VTX_ATTR_4B__SIZE 0x00000010
|
||
|
+#define NV50TCL_VTX_ATTR_4B_X_SHIFT 0
|
||
|
+#define NV50TCL_VTX_ATTR_4B_X_MASK 0x000000ff
|
||
|
+#define NV50TCL_VTX_ATTR_4B_Y_SHIFT 8
|
||
|
+#define NV50TCL_VTX_ATTR_4B_Y_MASK 0x0000ff00
|
||
|
+#define NV50TCL_VTX_ATTR_4B_Z_SHIFT 16
|
||
|
+#define NV50TCL_VTX_ATTR_4B_Z_MASK 0x00ff0000
|
||
|
+#define NV50TCL_VTX_ATTR_4B_W_SHIFT 24
|
||
|
+#define NV50TCL_VTX_ATTR_4B_W_MASK 0xff000000
|
||
|
+#define NV50TCL_VTX_ATTR_4NUB(x) (0x00000880+((x)*4))
|
||
|
+#define NV50TCL_VTX_ATTR_4NUB__SIZE 0x00000010
|
||
|
+#define NV50TCL_VTX_ATTR_4NUB_X_SHIFT 0
|
||
|
+#define NV50TCL_VTX_ATTR_4NUB_X_MASK 0x000000ff
|
||
|
+#define NV50TCL_VTX_ATTR_4NUB_Y_SHIFT 8
|
||
|
+#define NV50TCL_VTX_ATTR_4NUB_Y_MASK 0x0000ff00
|
||
|
+#define NV50TCL_VTX_ATTR_4NUB_Z_SHIFT 16
|
||
|
+#define NV50TCL_VTX_ATTR_4NUB_Z_MASK 0x00ff0000
|
||
|
+#define NV50TCL_VTX_ATTR_4NUB_W_SHIFT 24
|
||
|
+#define NV50TCL_VTX_ATTR_4NUB_W_MASK 0xff000000
|
||
|
+#define NV50TCL_VTX_ATTR_4NB(x) (0x000008c0+((x)*4))
|
||
|
+#define NV50TCL_VTX_ATTR_4NB__SIZE 0x00000010
|
||
|
+#define NV50TCL_VTX_ATTR_4NB_X_SHIFT 0
|
||
|
+#define NV50TCL_VTX_ATTR_4NB_X_MASK 0x000000ff
|
||
|
+#define NV50TCL_VTX_ATTR_4NB_Y_SHIFT 8
|
||
|
+#define NV50TCL_VTX_ATTR_4NB_Y_MASK 0x0000ff00
|
||
|
+#define NV50TCL_VTX_ATTR_4NB_Z_SHIFT 16
|
||
|
+#define NV50TCL_VTX_ATTR_4NB_Z_MASK 0x00ff0000
|
||
|
+#define NV50TCL_VTX_ATTR_4NB_W_SHIFT 24
|
||
|
+#define NV50TCL_VTX_ATTR_4NB_W_MASK 0xff000000
|
||
|
#define NV50TCL_VERTEX_ARRAY_FORMAT(x) (0x00000900+((x)*16))
|
||
|
#define NV50TCL_VERTEX_ARRAY_FORMAT__SIZE 0x00000010
|
||
|
#define NV50TCL_VERTEX_ARRAY_FORMAT_STRIDE_SHIFT 0
|
||
|
-#define NV50TCL_VERTEX_ARRAY_FORMAT_STRIDE_MASK 0x000000ff
|
||
|
-#define NV50TCL_UNK0904_OFFSET_HIGH(x) (0x00000904+((x)*16))
|
||
|
-#define NV50TCL_UNK0904_OFFSET_HIGH__SIZE 0x00000010
|
||
|
-#define NV50TCL_UNK0904_OFFSET_LOW(x) (0x00000908+((x)*16))
|
||
|
-#define NV50TCL_UNK0904_OFFSET_LOW__SIZE 0x00000010
|
||
|
-#define NV50TCL_VIEWPORT_SCALE(x) (0x00000a00+((x)*4))
|
||
|
-#define NV50TCL_VIEWPORT_SCALE__SIZE 0x00000003
|
||
|
-#define NV50TCL_VIEWPORT_TRANSLATE(x) (0x00000a0c+((x)*4))
|
||
|
-#define NV50TCL_VIEWPORT_TRANSLATE__SIZE 0x00000003
|
||
|
-#define NV50TCL_VIEWPORT_HORIZ 0x00000c00
|
||
|
+#define NV50TCL_VERTEX_ARRAY_FORMAT_STRIDE_MASK 0x00000fff
|
||
|
+#define NV50TCL_VERTEX_ARRAY_FORMAT_ENABLE (1 << 29)
|
||
|
+#define NV50TCL_VERTEX_ARRAY_START_HIGH(x) (0x00000904+((x)*16))
|
||
|
+#define NV50TCL_VERTEX_ARRAY_START_HIGH__SIZE 0x00000010
|
||
|
+#define NV50TCL_VERTEX_ARRAY_START_LOW(x) (0x00000908+((x)*16))
|
||
|
+#define NV50TCL_VERTEX_ARRAY_START_LOW__SIZE 0x00000010
|
||
|
+#define NV50TCL_VIEWPORT_SCALE_X(x) (0x00000a00+((x)*32))
|
||
|
+#define NV50TCL_VIEWPORT_SCALE_X__SIZE 0x00000010
|
||
|
+#define NV50TCL_VIEWPORT_SCALE_Y(x) (0x00000a04+((x)*32))
|
||
|
+#define NV50TCL_VIEWPORT_SCALE_Y__SIZE 0x00000010
|
||
|
+#define NV50TCL_VIEWPORT_SCALE_Z(x) (0x00000a08+((x)*32))
|
||
|
+#define NV50TCL_VIEWPORT_SCALE_Z__SIZE 0x00000010
|
||
|
+#define NV50TCL_VIEWPORT_TRANSLATE_X(x) (0x00000a0c+((x)*32))
|
||
|
+#define NV50TCL_VIEWPORT_TRANSLATE_X__SIZE 0x00000010
|
||
|
+#define NV50TCL_VIEWPORT_TRANSLATE_Y(x) (0x00000a10+((x)*32))
|
||
|
+#define NV50TCL_VIEWPORT_TRANSLATE_Y__SIZE 0x00000010
|
||
|
+#define NV50TCL_VIEWPORT_TRANSLATE_Z(x) (0x00000a14+((x)*32))
|
||
|
+#define NV50TCL_VIEWPORT_TRANSLATE_Z__SIZE 0x00000010
|
||
|
+#define NV50TCL_VIEWPORT_HORIZ(x) (0x00000c00+((x)*16))
|
||
|
+#define NV50TCL_VIEWPORT_HORIZ__SIZE 0x00000010
|
||
|
#define NV50TCL_VIEWPORT_HORIZ_X_SHIFT 0
|
||
|
#define NV50TCL_VIEWPORT_HORIZ_X_MASK 0x0000ffff
|
||
|
#define NV50TCL_VIEWPORT_HORIZ_W_SHIFT 16
|
||
|
#define NV50TCL_VIEWPORT_HORIZ_W_MASK 0xffff0000
|
||
|
-#define NV50TCL_VIEWPORT_VERT 0x00000c04
|
||
|
+#define NV50TCL_VIEWPORT_VERT(x) (0x00000c04+((x)*16))
|
||
|
+#define NV50TCL_VIEWPORT_VERT__SIZE 0x00000010
|
||
|
#define NV50TCL_VIEWPORT_VERT_Y_SHIFT 0
|
||
|
#define NV50TCL_VIEWPORT_VERT_Y_MASK 0x0000ffff
|
||
|
#define NV50TCL_VIEWPORT_VERT_H_SHIFT 16
|
||
|
#define NV50TCL_VIEWPORT_VERT_H_MASK 0xffff0000
|
||
|
-#define NV50TCL_DEPTH_RANGE_NEAR 0x00000c08
|
||
|
-#define NV50TCL_DEPTH_RANGE_FAR 0x00000c0c
|
||
|
+#define NV50TCL_DEPTH_RANGE_NEAR(x) (0x00000c08+((x)*16))
|
||
|
+#define NV50TCL_DEPTH_RANGE_NEAR__SIZE 0x00000010
|
||
|
+#define NV50TCL_DEPTH_RANGE_FAR(x) (0x00000c0c+((x)*16))
|
||
|
+#define NV50TCL_DEPTH_RANGE_FAR__SIZE 0x00000010
|
||
|
#define NV50TCL_VIEWPORT_CLIP_HORIZ(x) (0x00000d00+((x)*8))
|
||
|
#define NV50TCL_VIEWPORT_CLIP_HORIZ__SIZE 0x00000008
|
||
|
#define NV50TCL_VIEWPORT_CLIP_VERT(x) (0x00000d04+((x)*8))
|
||
|
@@ -7650,8 +7955,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_CLEAR_COLOR(x) (0x00000d80+((x)*4))
|
||
|
#define NV50TCL_CLEAR_COLOR__SIZE 0x00000004
|
||
|
#define NV50TCL_CLEAR_DEPTH 0x00000d90
|
||
|
+#define NV50TCL_STACK_ADDRESS_HIGH 0x00000d94
|
||
|
+#define NV50TCL_STACK_ADDRESS_LOW 0x00000d98
|
||
|
#define NV50TCL_CLEAR_STENCIL 0x00000da0
|
||
|
-#define NV50TCL_STRMOUT_UNK0DA8 0x00000da8
|
||
|
+#define NV50TCL_STRMOUT_PRIMITIVE_COUNT 0x00000da8
|
||
|
#define NV50TCL_POLYGON_MODE_FRONT 0x00000dac
|
||
|
#define NV50TCL_POLYGON_MODE_FRONT_POINT 0x00001b00
|
||
|
#define NV50TCL_POLYGON_MODE_FRONT_LINE 0x00001b01
|
||
|
@@ -7664,29 +7971,33 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000dc0
|
||
|
#define NV50TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000dc4
|
||
|
#define NV50TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000dc8
|
||
|
-#define NV50TCL_WINDOW_LEFT 0x00000df8
|
||
|
-#define NV50TCL_WINDOW_BOTTOM 0x00000dfc
|
||
|
-#define NV50TCL_SCISSOR_ENABLE 0x00000e00
|
||
|
-#define NV50TCL_SCISSOR_HORIZ 0x00000e04
|
||
|
-#define NV50TCL_SCISSOR_HORIZ_L_SHIFT 0
|
||
|
-#define NV50TCL_SCISSOR_HORIZ_L_MASK 0x0000ffff
|
||
|
-#define NV50TCL_SCISSOR_HORIZ_R_SHIFT 16
|
||
|
-#define NV50TCL_SCISSOR_HORIZ_R_MASK 0xffff0000
|
||
|
-#define NV50TCL_SCISSOR_VERT 0x00000e08
|
||
|
-#define NV50TCL_SCISSOR_VERT_B_SHIFT 0
|
||
|
-#define NV50TCL_SCISSOR_VERT_B_MASK 0x0000ffff
|
||
|
-#define NV50TCL_SCISSOR_VERT_T_SHIFT 16
|
||
|
-#define NV50TCL_SCISSOR_VERT_T_MASK 0xffff0000
|
||
|
+#define NV50TCL_WATCHDOG_TIMER 0x00000de4
|
||
|
+#define NV50TCL_WINDOW_OFFSET_X 0x00000df8
|
||
|
+#define NV50TCL_WINDOW_OFFSET_Y 0x00000dfc
|
||
|
+#define NV50TCL_SCISSOR_ENABLE(x) (0x00000e00+((x)*16))
|
||
|
+#define NV50TCL_SCISSOR_ENABLE__SIZE 0x00000010
|
||
|
+#define NV50TCL_SCISSOR_HORIZ(x) (0x00000e04+((x)*16))
|
||
|
+#define NV50TCL_SCISSOR_HORIZ__SIZE 0x00000010
|
||
|
+#define NV50TCL_SCISSOR_HORIZ_MIN_SHIFT 0
|
||
|
+#define NV50TCL_SCISSOR_HORIZ_MIN_MASK 0x0000ffff
|
||
|
+#define NV50TCL_SCISSOR_HORIZ_MAX_SHIFT 16
|
||
|
+#define NV50TCL_SCISSOR_HORIZ_MAX_MASK 0xffff0000
|
||
|
+#define NV50TCL_SCISSOR_VERT(x) (0x00000e08+((x)*16))
|
||
|
+#define NV50TCL_SCISSOR_VERT__SIZE 0x00000010
|
||
|
+#define NV50TCL_SCISSOR_VERT_MIN_SHIFT 0
|
||
|
+#define NV50TCL_SCISSOR_VERT_MIN_MASK 0x0000ffff
|
||
|
+#define NV50TCL_SCISSOR_VERT_MAX_SHIFT 16
|
||
|
+#define NV50TCL_SCISSOR_VERT_MAX_MASK 0xffff0000
|
||
|
#define NV50TCL_CB_ADDR 0x00000f00
|
||
|
#define NV50TCL_CB_ADDR_ID_SHIFT 8
|
||
|
-#define NV50TCL_CB_ADDR_ID_MASK 0xffffff00
|
||
|
+#define NV50TCL_CB_ADDR_ID_MASK 0x003fff00
|
||
|
#define NV50TCL_CB_ADDR_BUFFER_SHIFT 0
|
||
|
-#define NV50TCL_CB_ADDR_BUFFER_MASK 0x000000ff
|
||
|
+#define NV50TCL_CB_ADDR_BUFFER_MASK 0x0000007f
|
||
|
#define NV50TCL_CB_DATA(x) (0x00000f04+((x)*4))
|
||
|
#define NV50TCL_CB_DATA__SIZE 0x00000010
|
||
|
-#define NV50TCL_STENCIL_FRONT_FUNC_REF 0x00000f54
|
||
|
-#define NV50TCL_STENCIL_FRONT_MASK 0x00000f58
|
||
|
-#define NV50TCL_STENCIL_FRONT_FUNC_MASK 0x00000f5c
|
||
|
+#define NV50TCL_STENCIL_BACK_FUNC_REF 0x00000f54
|
||
|
+#define NV50TCL_STENCIL_BACK_MASK 0x00000f58
|
||
|
+#define NV50TCL_STENCIL_BACK_FUNC_MASK 0x00000f5c
|
||
|
#define NV50TCL_GP_ADDRESS_HIGH 0x00000f70
|
||
|
#define NV50TCL_GP_ADDRESS_LOW 0x00000f74
|
||
|
#define NV50TCL_VP_ADDRESS_HIGH 0x00000f7c
|
||
|
@@ -7703,12 +8014,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_ZETA_ADDRESS_LOW 0x00000fe4
|
||
|
#define NV50TCL_ZETA_FORMAT 0x00000fe8
|
||
|
#define NV50TCL_ZETA_FORMAT_Z32_FLOAT 0x0000000a
|
||
|
+#define NV50TCL_ZETA_FORMAT_Z16_UNORM 0x00000013
|
||
|
#define NV50TCL_ZETA_FORMAT_Z24S8_UNORM 0x00000014
|
||
|
#define NV50TCL_ZETA_FORMAT_X8Z24_UNORM 0x00000015
|
||
|
#define NV50TCL_ZETA_FORMAT_S8Z24_UNORM 0x00000016
|
||
|
#define NV50TCL_ZETA_FORMAT_Z32_FLOAT_X24S8_UNORM 0x00000019
|
||
|
#define NV50TCL_ZETA_TILE_MODE 0x00000fec
|
||
|
-#define NV50TCL_ZETA_UNK 0x00000ff0
|
||
|
+#define NV50TCL_ZETA_LAYER_STRIDE 0x00000ff0
|
||
|
#define NV50TCL_SCREEN_SCISSOR_HORIZ 0x00000ff4
|
||
|
#define NV50TCL_SCREEN_SCISSOR_HORIZ_W_SHIFT 16
|
||
|
#define NV50TCL_SCREEN_SCISSOR_HORIZ_W_MASK 0xffff0000
|
||
|
@@ -7719,12 +8031,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_SCREEN_SCISSOR_VERT_H_MASK 0xffff0000
|
||
|
#define NV50TCL_SCREEN_SCISSOR_VERT_Y_SHIFT 0
|
||
|
#define NV50TCL_SCREEN_SCISSOR_VERT_Y_MASK 0x0000ffff
|
||
|
-#define NV50TCL_UNK1080_OFFSET_HIGH(x) (0x00001080+((x)*8))
|
||
|
-#define NV50TCL_UNK1080_OFFSET_HIGH__SIZE 0x00000010
|
||
|
-#define NV50TCL_UNK1080_OFFSET_LOW(x) (0x00001084+((x)*8))
|
||
|
-#define NV50TCL_UNK1080_OFFSET_LOW__SIZE 0x00000010
|
||
|
+#define NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(x) (0x00001080+((x)*8))
|
||
|
+#define NV50TCL_VERTEX_ARRAY_LIMIT_HIGH__SIZE 0x00000010
|
||
|
+#define NV50TCL_VERTEX_ARRAY_LIMIT_LOW(x) (0x00001084+((x)*8))
|
||
|
+#define NV50TCL_VERTEX_ARRAY_LIMIT_LOW__SIZE 0x00000010
|
||
|
+#define NV50TCL_RT_CONTROL 0x0000121c
|
||
|
+#define NV50TCL_RT_CONTROL_COUNT_SHIFT 0
|
||
|
+#define NV50TCL_RT_CONTROL_COUNT_MASK 0x0000000f
|
||
|
+#define NV50TCL_RT_CONTROL_MAP0_SHIFT 4
|
||
|
+#define NV50TCL_RT_CONTROL_MAP0_MASK 0x00000070
|
||
|
+#define NV50TCL_RT_CONTROL_MAP1_SHIFT 7
|
||
|
+#define NV50TCL_RT_CONTROL_MAP1_MASK 0x00000380
|
||
|
+#define NV50TCL_RT_CONTROL_MAP2_SHIFT 10
|
||
|
+#define NV50TCL_RT_CONTROL_MAP2_MASK 0x00001c00
|
||
|
+#define NV50TCL_RT_CONTROL_MAP3_SHIFT 13
|
||
|
+#define NV50TCL_RT_CONTROL_MAP3_MASK 0x0000e000
|
||
|
+#define NV50TCL_RT_CONTROL_MAP4_SHIFT 16
|
||
|
+#define NV50TCL_RT_CONTROL_MAP4_MASK 0x00070000
|
||
|
+#define NV50TCL_RT_CONTROL_MAP5_SHIFT 19
|
||
|
+#define NV50TCL_RT_CONTROL_MAP5_MASK 0x00380000
|
||
|
+#define NV50TCL_RT_CONTROL_MAP6_SHIFT 22
|
||
|
+#define NV50TCL_RT_CONTROL_MAP6_MASK 0x01c00000
|
||
|
+#define NV50TCL_RT_CONTROL_MAP7_SHIFT 25
|
||
|
+#define NV50TCL_RT_CONTROL_MAP7_MASK 0x0e000000
|
||
|
+#define NV50TCL_RT_ARRAY_MODE 0x00001224
|
||
|
+#define NV50TCL_RT_ARRAY_MODE_LAYERS_SHIFT 0
|
||
|
+#define NV50TCL_RT_ARRAY_MODE_LAYERS_MASK 0x0000ffff
|
||
|
+#define NV50TCL_RT_ARRAY_MODE_VOLUME (1 << 16)
|
||
|
#define NV50TCL_ZETA_HORIZ 0x00001228
|
||
|
#define NV50TCL_ZETA_VERT 0x0000122c
|
||
|
+#define NV50TCL_ZETA_ARRAY_MODE 0x00001230
|
||
|
+#define NV50TCL_ZETA_ARRAY_MODE_LAYERS_SHIFT 0
|
||
|
+#define NV50TCL_ZETA_ARRAY_MODE_LAYERS_MASK 0x0000ffff
|
||
|
+#define NV50TCL_ZETA_ARRAY_MODE_UNK (1 << 16)
|
||
|
+#define NV50TCL_LINKED_TSC 0x00001234
|
||
|
#define NV50TCL_RT_HORIZ(x) (0x00001240+((x)*8))
|
||
|
#define NV50TCL_RT_HORIZ__SIZE 0x00000008
|
||
|
#define NV50TCL_RT_VERT(x) (0x00001244+((x)*8))
|
||
|
@@ -7735,7 +8075,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_CB_DEF_SET_SIZE_SHIFT 0
|
||
|
#define NV50TCL_CB_DEF_SET_SIZE_MASK 0x0000ffff
|
||
|
#define NV50TCL_CB_DEF_SET_BUFFER_SHIFT 16
|
||
|
-#define NV50TCL_CB_DEF_SET_BUFFER_MASK 0xffff0000
|
||
|
+#define NV50TCL_CB_DEF_SET_BUFFER_MASK 0x007f0000
|
||
|
#define NV50TCL_STRMOUT_BUFFERS_CTRL 0x00001294
|
||
|
#define NV50TCL_STRMOUT_BUFFERS_CTRL_INTERLEAVED (1 << 0)
|
||
|
#define NV50TCL_STRMOUT_BUFFERS_CTRL_SEPARATE_SHIFT 4
|
||
|
@@ -7747,15 +8087,33 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_SHADE_MODEL 0x000012d4
|
||
|
#define NV50TCL_SHADE_MODEL_FLAT 0x00001d00
|
||
|
#define NV50TCL_SHADE_MODEL_SMOOTH 0x00001d01
|
||
|
+#define NV50TCL_LOCAL_BASE_HIGH 0x000012d8
|
||
|
+#define NV50TCL_LOCAL_BASE_LOW 0x000012dc
|
||
|
+#define NV50TCL_LOCAL_SIZE_LOG 0x000012e0
|
||
|
#define NV50TCL_DEPTH_WRITE_ENABLE 0x000012e8
|
||
|
#define NV50TCL_ALPHA_TEST_ENABLE 0x000012ec
|
||
|
+#define NV50TCL_PM_SET(x) (0x000012f0+((x)*4))
|
||
|
+#define NV50TCL_PM_SET__SIZE 0x00000004
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_SETUP 0x00001300
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_SETUP_OFFSET_SHIFT 30
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_SETUP_OFFSET_MASK 0xc0000000
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_SETUP_COUNT_SHIFT 0
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_SETUP_COUNT_MASK 0x3fffffff
|
||
|
+#define NV50TCL_VB_ELEMENT_U8 0x00001304
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_I0_SHIFT 0
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_I0_MASK 0x000000ff
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_I1_SHIFT 8
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_I1_MASK 0x0000ff00
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_I2_SHIFT 16
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_I2_MASK 0x00ff0000
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_I3_SHIFT 24
|
||
|
+#define NV50TCL_VB_ELEMENT_U8_I3_MASK 0xff000000
|
||
|
#define NV50TCL_DEPTH_TEST_FUNC 0x0000130c
|
||
|
#define NV50TCL_DEPTH_TEST_FUNC_NEVER 0x00000200
|
||
|
#define NV50TCL_DEPTH_TEST_FUNC_LESS 0x00000201
|
||
|
#define NV50TCL_DEPTH_TEST_FUNC_EQUAL 0x00000202
|
||
|
#define NV50TCL_DEPTH_TEST_FUNC_LEQUAL 0x00000203
|
||
|
#define NV50TCL_DEPTH_TEST_FUNC_GREATER 0x00000204
|
||
|
-#define NV50TCL_DEPTH_TEST_FUNC_GREATER 0x00000204
|
||
|
#define NV50TCL_DEPTH_TEST_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV50TCL_DEPTH_TEST_FUNC_GEQUAL 0x00000206
|
||
|
#define NV50TCL_DEPTH_TEST_FUNC_ALWAYS 0x00000207
|
||
|
@@ -7766,12 +8124,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_ALPHA_TEST_FUNC_EQUAL 0x00000202
|
||
|
#define NV50TCL_ALPHA_TEST_FUNC_LEQUAL 0x00000203
|
||
|
#define NV50TCL_ALPHA_TEST_FUNC_GREATER 0x00000204
|
||
|
-#define NV50TCL_ALPHA_TEST_FUNC_GREATER 0x00000204
|
||
|
#define NV50TCL_ALPHA_TEST_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV50TCL_ALPHA_TEST_FUNC_GEQUAL 0x00000206
|
||
|
#define NV50TCL_ALPHA_TEST_FUNC_ALWAYS 0x00000207
|
||
|
#define NV50TCL_BLEND_COLOR(x) (0x0000131c+((x)*4))
|
||
|
#define NV50TCL_BLEND_COLOR__SIZE 0x00000004
|
||
|
+#define NV50TCL_TIC_FLUSH 0x00001330
|
||
|
+#define NV50TCL_TSC_FLUSH 0x00001334
|
||
|
+#define NV50TCL_TEX_CACHE_CTL 0x00001338
|
||
|
#define NV50TCL_BLEND_EQUATION_RGB 0x00001340
|
||
|
#define NV50TCL_BLEND_EQUATION_RGB_FUNC_ADD 0x00008006
|
||
|
#define NV50TCL_BLEND_EQUATION_RGB_MIN 0x00008007
|
||
|
@@ -7850,83 +8210,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x00008004
|
||
|
#define NV50TCL_BLEND_ENABLE(x) (0x00001360+((x)*4))
|
||
|
#define NV50TCL_BLEND_ENABLE__SIZE 0x00000008
|
||
|
-#define NV50TCL_STENCIL_BACK_ENABLE 0x00001380
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_FAIL 0x00001384
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_FAIL_ZERO 0x00000000
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_FAIL_INVERT 0x0000150a
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_FAIL_KEEP 0x00001e00
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_FAIL_REPLACE 0x00001e01
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_FAIL_INCR 0x00001e02
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_FAIL_DECR 0x00001e03
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_FAIL_INCR_WRAP 0x00008507
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_FAIL_DECR_WRAP 0x00008508
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL 0x00001388
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_ZERO 0x00000000
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INVERT 0x0000150a
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_KEEP 0x00001e00
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_REPLACE 0x00001e01
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INCR 0x00001e02
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_DECR 0x00001e03
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INCR_WRAP 0x00008507
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZFAIL_DECR_WRAP 0x00008508
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZPASS 0x0000138c
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_ZERO 0x00000000
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_INVERT 0x0000150a
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_KEEP 0x00001e00
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_REPLACE 0x00001e01
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_INCR 0x00001e02
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_DECR 0x00001e03
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_INCR_WRAP 0x00008507
|
||
|
-#define NV50TCL_STENCIL_BACK_OP_ZPASS_DECR_WRAP 0x00008508
|
||
|
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC 0x00001390
|
||
|
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_NEVER 0x00000200
|
||
|
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_LESS 0x00000201
|
||
|
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202
|
||
|
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203
|
||
|
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
|
||
|
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
|
||
|
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205
|
||
|
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206
|
||
|
-#define NV50TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207
|
||
|
-#define NV50TCL_STENCIL_BACK_FUNC_REF 0x00001394
|
||
|
-#define NV50TCL_STENCIL_BACK_MASK 0x00001398
|
||
|
-#define NV50TCL_STENCIL_BACK_FUNC_MASK 0x0000139c
|
||
|
-#define NV50TCL_FRAG_COLOR_CLAMP_EN 0x000013a8
|
||
|
-#define NV50TCL_LINE_WIDTH 0x000013b0
|
||
|
-#define NV50TCL_POINT_COORD_REPLACE_MAP(x) (0x000013c0+((x)*4))
|
||
|
-#define NV50TCL_POINT_COORD_REPLACE_MAP__SIZE 0x00000008
|
||
|
-#define NV50TCL_VP_START_ID 0x0000140c
|
||
|
-#define NV50TCL_GP_START_ID 0x00001410
|
||
|
-#define NV50TCL_FP_START_ID 0x00001414
|
||
|
-#define NV50TCL_GP_VERTEX_OUTPUT_COUNT 0x00001420
|
||
|
-#define NV50TCL_SET_SAMPLER_TEX 0x00001458
|
||
|
-#define NV50TCL_SET_SAMPLER_TEX_SAMPLER_SHIFT 1
|
||
|
-#define NV50TCL_SET_SAMPLER_TEX_SAMPLER_MASK 0x000001fe
|
||
|
-#define NV50TCL_SET_SAMPLER_TEX_TIC_SHIFT 9
|
||
|
-#define NV50TCL_SET_SAMPLER_TEX_TIC_MASK 0x0001fe00
|
||
|
-#define NV50TCL_SET_SAMPLER_TEX_VALID (1 << 0)
|
||
|
-#define NV50TCL_STRMOUT_MAP(x) (0x00001480+((x)*4))
|
||
|
-#define NV50TCL_STRMOUT_MAP__SIZE 0x00000020
|
||
|
-#define NV50TCL_VP_CLIP_DISTANCE_ENABLE 0x00001510
|
||
|
-#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_0 (1 << 0)
|
||
|
-#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_1 (1 << 1)
|
||
|
-#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_2 (1 << 2)
|
||
|
-#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_3 (1 << 3)
|
||
|
-#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_4 (1 << 4)
|
||
|
-#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_5 (1 << 5)
|
||
|
-#define NV50TCL_POINT_SIZE 0x00001518
|
||
|
-#define NV50TCL_POINT_SPRITE_ENABLE 0x00001520
|
||
|
-#define NV50TCL_MULTISAMPLE_CTRL 0x0000153c
|
||
|
-#define NV50TCL_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE (1 << 0)
|
||
|
-#define NV50TCL_MULTISAMPLE_CTRL_ALPHA_TO_ONE (1 << 4)
|
||
|
-#define NV50TCL_TSC_ADDRESS_HIGH 0x0000155c
|
||
|
-#define NV50TCL_TSC_ADDRESS_LOW 0x00001560
|
||
|
-#define NV50TCL_POLYGON_OFFSET_FACTOR 0x0000156c
|
||
|
-#define NV50TCL_LINE_SMOOTH_ENABLE 0x00001570
|
||
|
-#define NV50TCL_TIC_ADDRESS_HIGH 0x00001574
|
||
|
-#define NV50TCL_TIC_ADDRESS_LOW 0x00001578
|
||
|
-#define NV50TCL_STENCIL_FRONT_ENABLE 0x00001594
|
||
|
-#define NV50TCL_STENCIL_FRONT_OP_FAIL 0x00001598
|
||
|
+#define NV50TCL_STENCIL_FRONT_ENABLE 0x00001380
|
||
|
+#define NV50TCL_STENCIL_FRONT_OP_FAIL 0x00001384
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_FAIL_ZERO 0x00000000
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_FAIL_INVERT 0x0000150a
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_FAIL_KEEP 0x00001e00
|
||
|
@@ -7935,7 +8220,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_FAIL_DECR 0x00001e03
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_FAIL_INCR_WRAP 0x00008507
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_FAIL_DECR_WRAP 0x00008508
|
||
|
-#define NV50TCL_STENCIL_FRONT_OP_ZFAIL 0x0000159c
|
||
|
+#define NV50TCL_STENCIL_FRONT_OP_ZFAIL 0x00001388
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_ZERO 0x00000000
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_INVERT 0x0000150a
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_KEEP 0x00001e00
|
||
|
@@ -7944,7 +8229,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_DECR 0x00001e03
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_INCR_WRAP 0x00008507
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_ZFAIL_DECR_WRAP 0x00008508
|
||
|
-#define NV50TCL_STENCIL_FRONT_OP_ZPASS 0x000015a0
|
||
|
+#define NV50TCL_STENCIL_FRONT_OP_ZPASS 0x0000138c
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_ZPASS_ZERO 0x00000000
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_ZPASS_INVERT 0x0000150a
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_ZPASS_KEEP 0x00001e00
|
||
|
@@ -7953,17 +8238,135 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_ZPASS_DECR 0x00001e03
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_ZPASS_INCR_WRAP 0x00008507
|
||
|
#define NV50TCL_STENCIL_FRONT_OP_ZPASS_DECR_WRAP 0x00008508
|
||
|
-#define NV50TCL_STENCIL_FRONT_FUNC_FUNC 0x000015a4
|
||
|
+#define NV50TCL_STENCIL_FRONT_FUNC_FUNC 0x00001390
|
||
|
#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_NEVER 0x00000200
|
||
|
#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_LESS 0x00000201
|
||
|
#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_EQUAL 0x00000202
|
||
|
#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_LEQUAL 0x00000203
|
||
|
#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204
|
||
|
-#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_GREATER 0x00000204
|
||
|
#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_NOTEQUAL 0x00000205
|
||
|
#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206
|
||
|
#define NV50TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207
|
||
|
+#define NV50TCL_STENCIL_FRONT_FUNC_REF 0x00001394
|
||
|
+#define NV50TCL_STENCIL_FRONT_MASK 0x00001398
|
||
|
+#define NV50TCL_STENCIL_FRONT_FUNC_MASK 0x0000139c
|
||
|
+#define NV50TCL_FRAG_COLOR_CLAMP_EN 0x000013a8
|
||
|
+#define NV50TCL_Y_ORIGIN_BOTTOM 0x000013ac
|
||
|
+#define NV50TCL_LINE_WIDTH 0x000013b0
|
||
|
+#define NV50TCL_TEX_LIMITS(x) (0x000013b4+((x)*4))
|
||
|
+#define NV50TCL_TEX_LIMITS__SIZE 0x00000003
|
||
|
+#define NV50TCL_TEX_LIMITS_SAMPLERS_LOG2_SHIFT 0
|
||
|
+#define NV50TCL_TEX_LIMITS_SAMPLERS_LOG2_MASK 0x0000000f
|
||
|
+#define NV50TCL_TEX_LIMITS_TEXTURES_LOG2_SHIFT 4
|
||
|
+#define NV50TCL_TEX_LIMITS_TEXTURES_LOG2_MASK 0x000000f0
|
||
|
+#define NV50TCL_POINT_COORD_REPLACE_MAP(x) (0x000013c0+((x)*4))
|
||
|
+#define NV50TCL_POINT_COORD_REPLACE_MAP__SIZE 0x00000008
|
||
|
+#define NV50TCL_VP_START_ID 0x0000140c
|
||
|
+#define NV50TCL_GP_START_ID 0x00001410
|
||
|
+#define NV50TCL_FP_START_ID 0x00001414
|
||
|
+#define NV50TCL_GP_VERTEX_OUTPUT_COUNT 0x00001420
|
||
|
+#define NV50TCL_VB_ELEMENT_BASE 0x00001434
|
||
|
+#define NV50TCL_CODE_CB_FLUSH 0x00001440
|
||
|
+#define NV50TCL_BIND_TSC(x) (0x00001444+((x)*8))
|
||
|
+#define NV50TCL_BIND_TSC__SIZE 0x00000003
|
||
|
+#define NV50TCL_BIND_TSC_VALID (1 << 0)
|
||
|
+#define NV50TCL_BIND_TSC_SAMPLER_SHIFT 4
|
||
|
+#define NV50TCL_BIND_TSC_SAMPLER_MASK 0x000000f0
|
||
|
+#define NV50TCL_BIND_TSC_TSC_SHIFT 12
|
||
|
+#define NV50TCL_BIND_TSC_TSC_MASK 0x001ff000
|
||
|
+#define NV50TCL_BIND_TIC(x) (0x00001448+((x)*8))
|
||
|
+#define NV50TCL_BIND_TIC__SIZE 0x00000003
|
||
|
+#define NV50TCL_BIND_TIC_VALID (1 << 0)
|
||
|
+#define NV50TCL_BIND_TIC_TEXTURE_SHIFT 1
|
||
|
+#define NV50TCL_BIND_TIC_TEXTURE_MASK 0x000001fe
|
||
|
+#define NV50TCL_BIND_TIC_TIC_SHIFT 9
|
||
|
+#define NV50TCL_BIND_TIC_TIC_MASK 0x7ffffe00
|
||
|
+#define NV50TCL_STRMOUT_MAP(x) (0x00001480+((x)*4))
|
||
|
+#define NV50TCL_STRMOUT_MAP__SIZE 0x00000020
|
||
|
+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE 0x00001510
|
||
|
+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_0 (1 << 0)
|
||
|
+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_1 (1 << 1)
|
||
|
+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_2 (1 << 2)
|
||
|
+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_3 (1 << 3)
|
||
|
+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_4 (1 << 4)
|
||
|
+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_5 (1 << 5)
|
||
|
+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_6 (1 << 6)
|
||
|
+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_7 (1 << 7)
|
||
|
+#define NV50TCL_SAMPLECNT_ENABLE 0x00001514
|
||
|
+#define NV50TCL_POINT_SIZE 0x00001518
|
||
|
+#define NV50TCL_POINT_SPRITE_ENABLE 0x00001520
|
||
|
+#define NV50TCL_SAMPLECNT_RESET 0x00001530
|
||
|
+#define NV50TCL_ZETA_ENABLE 0x00001538
|
||
|
+#define NV50TCL_MULTISAMPLE_CTRL 0x0000153c
|
||
|
+#define NV50TCL_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE (1 << 0)
|
||
|
+#define NV50TCL_MULTISAMPLE_CTRL_ALPHA_TO_ONE (1 << 4)
|
||
|
+#define NV50TCL_NOPERSPECTIVE_BITMAP(x) (0x00001540+((x)*4))
|
||
|
+#define NV50TCL_NOPERSPECTIVE_BITMAP__SIZE 0x00000004
|
||
|
+#define NV50TCL_COND_ADDRESS_HIGH 0x00001550
|
||
|
+#define NV50TCL_COND_ADDRESS_LOW 0x00001554
|
||
|
+#define NV50TCL_COND_MODE 0x00001558
|
||
|
+#define NV50TCL_COND_MODE_NEVER 0x00000000
|
||
|
+#define NV50TCL_COND_MODE_ALWAYS 0x00000001
|
||
|
+#define NV50TCL_COND_MODE_RES 0x00000002
|
||
|
+#define NV50TCL_COND_MODE_NOT_RES_AND_NOT_ID 0x00000003
|
||
|
+#define NV50TCL_COND_MODE_RES_OR_ID 0x00000004
|
||
|
+#define NV50TCL_TSC_ADDRESS_HIGH 0x0000155c
|
||
|
+#define NV50TCL_TSC_ADDRESS_LOW 0x00001560
|
||
|
+#define NV50TCL_TSC_LIMIT 0x00001564
|
||
|
+#define NV50TCL_POLYGON_OFFSET_FACTOR 0x0000156c
|
||
|
+#define NV50TCL_LINE_SMOOTH_ENABLE 0x00001570
|
||
|
+#define NV50TCL_TIC_ADDRESS_HIGH 0x00001574
|
||
|
+#define NV50TCL_TIC_ADDRESS_LOW 0x00001578
|
||
|
+#define NV50TCL_TIC_LIMIT 0x0000157c
|
||
|
+#define NV50TCL_PM_CONTROL(x) (0x00001580+((x)*4))
|
||
|
+#define NV50TCL_PM_CONTROL__SIZE 0x00000004
|
||
|
+#define NV50TCL_PM_CONTROL_UNK0 (1 << 0)
|
||
|
+#define NV50TCL_PM_CONTROL_UNK1_SHIFT 4
|
||
|
+#define NV50TCL_PM_CONTROL_UNK1_MASK 0x00000070
|
||
|
+#define NV50TCL_PM_CONTROL_UNK2_SHIFT 8
|
||
|
+#define NV50TCL_PM_CONTROL_UNK2_MASK 0xffffff00
|
||
|
+#define NV50TCL_STENCIL_BACK_ENABLE 0x00001594
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_FAIL 0x00001598
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_FAIL_ZERO 0x00000000
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_FAIL_INVERT 0x0000150a
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_FAIL_KEEP 0x00001e00
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_FAIL_REPLACE 0x00001e01
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_FAIL_INCR 0x00001e02
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_FAIL_DECR 0x00001e03
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_FAIL_INCR_WRAP 0x00008507
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_FAIL_DECR_WRAP 0x00008508
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZFAIL 0x0000159c
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZFAIL_ZERO 0x00000000
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INVERT 0x0000150a
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZFAIL_KEEP 0x00001e00
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZFAIL_REPLACE 0x00001e01
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INCR 0x00001e02
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZFAIL_DECR 0x00001e03
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZFAIL_INCR_WRAP 0x00008507
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZFAIL_DECR_WRAP 0x00008508
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZPASS 0x000015a0
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZPASS_ZERO 0x00000000
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZPASS_INVERT 0x0000150a
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZPASS_KEEP 0x00001e00
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZPASS_REPLACE 0x00001e01
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZPASS_INCR 0x00001e02
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZPASS_DECR 0x00001e03
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZPASS_INCR_WRAP 0x00008507
|
||
|
+#define NV50TCL_STENCIL_BACK_OP_ZPASS_DECR_WRAP 0x00008508
|
||
|
+#define NV50TCL_STENCIL_BACK_FUNC_FUNC 0x000015a4
|
||
|
+#define NV50TCL_STENCIL_BACK_FUNC_FUNC_NEVER 0x00000200
|
||
|
+#define NV50TCL_STENCIL_BACK_FUNC_FUNC_LESS 0x00000201
|
||
|
+#define NV50TCL_STENCIL_BACK_FUNC_FUNC_EQUAL 0x00000202
|
||
|
+#define NV50TCL_STENCIL_BACK_FUNC_FUNC_LEQUAL 0x00000203
|
||
|
+#define NV50TCL_STENCIL_BACK_FUNC_FUNC_GREATER 0x00000204
|
||
|
+#define NV50TCL_STENCIL_BACK_FUNC_FUNC_NOTEQUAL 0x00000205
|
||
|
+#define NV50TCL_STENCIL_BACK_FUNC_FUNC_GEQUAL 0x00000206
|
||
|
+#define NV50TCL_STENCIL_BACK_FUNC_FUNC_ALWAYS 0x00000207
|
||
|
+#define NV50TCL_FRAMEBUFFER_SRGB 0x000015b8
|
||
|
#define NV50TCL_POLYGON_OFFSET_UNITS 0x000015bc
|
||
|
+#define NV50TCL_GP_BUILTIN_RESULT_EN 0x000015cc
|
||
|
+#define NV50TCL_GP_BUILTIN_RESULT_EN_VPORT_IDX (1 << 0)
|
||
|
+#define NV50TCL_GP_BUILTIN_RESULT_EN_LAYER_IDX (1 << 16)
|
||
|
#define NV50TCL_MULTISAMPLE_SAMPLES_LOG2 0x000015d0
|
||
|
#define NV50TCL_VERTEX_BEGIN 0x000015dc
|
||
|
#define NV50TCL_VERTEX_BEGIN_POINTS 0x00000000
|
||
|
@@ -7981,9 +8384,26 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_VERTEX_BEGIN_TRIANGLES_ADJACENCY 0x0000000c
|
||
|
#define NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP_ADJACENCY 0x0000000d
|
||
|
#define NV50TCL_VERTEX_END 0x000015e0
|
||
|
+#define NV50TCL_EDGEFLAG_ENABLE 0x000015e4
|
||
|
+#define NV50TCL_VB_ELEMENT_U32 0x000015e8
|
||
|
+#define NV50TCL_VB_ELEMENT_U16_SETUP 0x000015ec
|
||
|
+#define NV50TCL_VB_ELEMENT_U16_SETUP_OFFSET_SHIFT 30
|
||
|
+#define NV50TCL_VB_ELEMENT_U16_SETUP_OFFSET_MASK 0xc0000000
|
||
|
+#define NV50TCL_VB_ELEMENT_U16_SETUP_COUNT_SHIFT 0
|
||
|
+#define NV50TCL_VB_ELEMENT_U16_SETUP_COUNT_MASK 0x3fffffff
|
||
|
+#define NV50TCL_VB_ELEMENT_U16 0x000015f0
|
||
|
+#define NV50TCL_VB_ELEMENT_U16_I0_SHIFT 0
|
||
|
+#define NV50TCL_VB_ELEMENT_U16_I0_MASK 0x0000ffff
|
||
|
+#define NV50TCL_VB_ELEMENT_U16_I1_SHIFT 16
|
||
|
+#define NV50TCL_VB_ELEMENT_U16_I1_MASK 0xffff0000
|
||
|
#define NV50TCL_VERTEX_DATA 0x00001640
|
||
|
#define NV50TCL_PRIM_RESTART_ENABLE 0x00001644
|
||
|
#define NV50TCL_PRIM_RESTART_INDEX 0x00001648
|
||
|
+#define NV50TCL_VP_GP_BUILTIN_ATTR_EN 0x0000164c
|
||
|
+#define NV50TCL_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID (1 << 0)
|
||
|
+#define NV50TCL_VP_GP_BUILTIN_ATTR_EN_INSTANCE_ID (1 << 4)
|
||
|
+#define NV50TCL_VP_GP_BUILTIN_ATTR_EN_PRIMITIVE_ID (1 << 8)
|
||
|
+#define NV50TCL_VP_GP_BUILTIN_ATTR_EN_UNK12 (1 << 12)
|
||
|
#define NV50TCL_VP_ATTR_EN_0 0x00001650
|
||
|
#define NV50TCL_VP_ATTR_EN_0_7_SHIFT 28
|
||
|
#define NV50TCL_VP_ATTR_EN_0_7_MASK 0xf0000000
|
||
|
@@ -8277,6 +8697,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_POINT_SPRITE_CTRL 0x00001660
|
||
|
#define NV50TCL_LINE_STIPPLE_ENABLE 0x0000166c
|
||
|
#define NV50TCL_LINE_STIPPLE_PATTERN 0x00001680
|
||
|
+#define NV50TCL_PROVOKING_VERTEX_LAST 0x00001684
|
||
|
#define NV50TCL_VERTEX_TWO_SIDE_ENABLE 0x00001688
|
||
|
#define NV50TCL_POLYGON_STIPPLE_ENABLE 0x0000168c
|
||
|
#define NV50TCL_SET_PROGRAM_CB 0x00001694
|
||
|
@@ -8288,13 +8709,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_SET_PROGRAM_CB_INDEX_SHIFT 8
|
||
|
#define NV50TCL_SET_PROGRAM_CB_INDEX_MASK 0x00000f00
|
||
|
#define NV50TCL_SET_PROGRAM_CB_BUFFER_SHIFT 12
|
||
|
-#define NV50TCL_SET_PROGRAM_CB_BUFFER_MASK 0x000ff000
|
||
|
+#define NV50TCL_SET_PROGRAM_CB_BUFFER_MASK 0x0007f000
|
||
|
#define NV50TCL_SET_PROGRAM_CB_VALID (1 << 0)
|
||
|
#define NV50TCL_VP_RESULT_MAP_SIZE 0x000016ac
|
||
|
#define NV50TCL_VP_REG_ALLOC_TEMP 0x000016b0
|
||
|
#define NV50TCL_VP_REG_ALLOC_RESULT 0x000016b8
|
||
|
#define NV50TCL_VP_RESULT_MAP(x) (0x000016bc+((x)*4))
|
||
|
-#define NV50TCL_VP_RESULT_MAP__SIZE 0x00000008
|
||
|
+#define NV50TCL_VP_RESULT_MAP__SIZE 0x00000010
|
||
|
#define NV50TCL_VP_RESULT_MAP_0_SHIFT 0
|
||
|
#define NV50TCL_VP_RESULT_MAP_0_MASK 0x000000ff
|
||
|
#define NV50TCL_VP_RESULT_MAP_1_SHIFT 8
|
||
|
@@ -8314,8 +8735,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_LINE_STRIP 0x00000002
|
||
|
#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_TRIANGLE_STRIP 0x00000003
|
||
|
#define NV50TCL_RASTERIZE_ENABLE 0x000017b4
|
||
|
+#define NV50TCL_STRMOUT_ENABLE 0x000017b8
|
||
|
#define NV50TCL_GP_RESULT_MAP(x) (0x000017fc+((x)*4))
|
||
|
-#define NV50TCL_GP_RESULT_MAP__SIZE 0x00000008
|
||
|
+#define NV50TCL_GP_RESULT_MAP__SIZE 0x00000020
|
||
|
#define NV50TCL_GP_RESULT_MAP_0_SHIFT 0
|
||
|
#define NV50TCL_GP_RESULT_MAP_0_MASK 0x000000ff
|
||
|
#define NV50TCL_GP_RESULT_MAP_1_SHIFT 8
|
||
|
@@ -8338,23 +8760,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_MAP_SEMANTIC_1_CLIP_LO_MASK 0x000000ff
|
||
|
#define NV50TCL_MAP_SEMANTIC_1_CLIP_HI_SHIFT 8
|
||
|
#define NV50TCL_MAP_SEMANTIC_1_CLIP_HI_MASK 0x0000ff00
|
||
|
-#define NV50TCL_MAP_SEMANTIC_1_UNKN_02_SHIFT 16
|
||
|
-#define NV50TCL_MAP_SEMANTIC_1_UNKN_02_MASK 0x00ff0000
|
||
|
-#define NV50TCL_MAP_SEMANTIC_1_UNKN_03_SHIFT 24
|
||
|
-#define NV50TCL_MAP_SEMANTIC_1_UNKN_03_MASK 0xff000000
|
||
|
#define NV50TCL_MAP_SEMANTIC_2 0x0000190c
|
||
|
-#define NV50TCL_MAP_SEMANTIC_2_UNKN_00_SHIFT 0
|
||
|
-#define NV50TCL_MAP_SEMANTIC_2_UNKN_00_MASK 0x000000ff
|
||
|
-#define NV50TCL_MAP_SEMANTIC_2_UNKN_01_SHIFT 8
|
||
|
-#define NV50TCL_MAP_SEMANTIC_2_UNKN_01_MASK 0x0000ff00
|
||
|
-#define NV50TCL_MAP_SEMANTIC_2_UNKN_02_SHIFT 16
|
||
|
-#define NV50TCL_MAP_SEMANTIC_2_UNKN_02_MASK 0x00ff0000
|
||
|
-#define NV50TCL_MAP_SEMANTIC_2_UNKN_03_SHIFT 24
|
||
|
-#define NV50TCL_MAP_SEMANTIC_2_UNKN_03_MASK 0xff000000
|
||
|
+#define NV50TCL_MAP_SEMANTIC_2_LAYER_ID_SHIFT 0
|
||
|
+#define NV50TCL_MAP_SEMANTIC_2_LAYER_ID_MASK 0x000000ff
|
||
|
#define NV50TCL_MAP_SEMANTIC_3 0x00001910
|
||
|
#define NV50TCL_MAP_SEMANTIC_3_PTSZ_EN (1 << 0)
|
||
|
#define NV50TCL_MAP_SEMANTIC_3_PTSZ_ID_SHIFT 4
|
||
|
#define NV50TCL_MAP_SEMANTIC_3_PTSZ_ID_MASK 0x00000ff0
|
||
|
+#define NV50TCL_MAP_SEMANTIC_4 0x00001914
|
||
|
+#define NV50TCL_MAP_SEMANTIC_4_PRIM_ID_SHIFT 0
|
||
|
+#define NV50TCL_MAP_SEMANTIC_4_PRIM_ID_MASK 0x000000ff
|
||
|
#define NV50TCL_CULL_FACE_ENABLE 0x00001918
|
||
|
#define NV50TCL_FRONT_FACE 0x0000191c
|
||
|
#define NV50TCL_FRONT_FACE_CW 0x00000900
|
||
|
@@ -8385,16 +8800,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNZW 0x0d000000
|
||
|
#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYZW 0x0e000000
|
||
|
#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYZW 0x0f000000
|
||
|
-#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_SHIFT 16
|
||
|
-#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_MASK 0x00ff0000
|
||
|
+#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_NONFLAT_SHIFT 16
|
||
|
+#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_NONFLAT_MASK 0x00ff0000
|
||
|
#define NV50TCL_FP_INTERPOLANT_CTRL_OFFSET_SHIFT 8
|
||
|
#define NV50TCL_FP_INTERPOLANT_CTRL_OFFSET_MASK 0x0000ff00
|
||
|
-#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_UNK_SHIFT 0
|
||
|
-#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_UNK_MASK 0x000000ff
|
||
|
+#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_SHIFT 0
|
||
|
+#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_MASK 0x000000ff
|
||
|
#define NV50TCL_FP_REG_ALLOC_TEMP 0x0000198c
|
||
|
-#define NV50TCL_FP_CTRL_UNK19A8 0x000019a8
|
||
|
-#define NV50TCL_FP_CTRL_UNK19A8_DEP (1 << 20)
|
||
|
-#define NV50TCL_FP_CTRL_UNK19A8_KIL (1 << 8)
|
||
|
+#define NV50TCL_WARP_HALVES 0x000019a0
|
||
|
+#define NV50TCL_FP_CONTROL 0x000019a8
|
||
|
+#define NV50TCL_FP_CONTROL_MULTIPLE_RESULTS (1 << 0)
|
||
|
+#define NV50TCL_FP_CONTROL_EXPORTS_Z (1 << 8)
|
||
|
+#define NV50TCL_FP_CONTROL_USES_KIL (1 << 20)
|
||
|
#define NV50TCL_DEPTH_BOUNDS_EN 0x000019bc
|
||
|
#define NV50TCL_LOGIC_OP_ENABLE 0x000019c4
|
||
|
#define NV50TCL_LOGIC_OP 0x000019c8
|
||
|
@@ -8415,6 +8832,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_LOGIC_OP_NAND 0x0000150e
|
||
|
#define NV50TCL_LOGIC_OP_SET 0x0000150f
|
||
|
#define NV50TCL_CLEAR_BUFFERS 0x000019d0
|
||
|
+#define NV50TCL_CLEAR_BUFFERS_Z (1 << 0)
|
||
|
+#define NV50TCL_CLEAR_BUFFERS_S (1 << 1)
|
||
|
+#define NV50TCL_CLEAR_BUFFERS_R (1 << 2)
|
||
|
+#define NV50TCL_CLEAR_BUFFERS_G (1 << 3)
|
||
|
+#define NV50TCL_CLEAR_BUFFERS_B (1 << 4)
|
||
|
+#define NV50TCL_CLEAR_BUFFERS_A (1 << 5)
|
||
|
+#define NV50TCL_CLEAR_BUFFERS_RT_SHIFT 6
|
||
|
+#define NV50TCL_CLEAR_BUFFERS_RT_MASK 0x000003c0
|
||
|
+#define NV50TCL_CLEAR_BUFFERS_LAYER_SHIFT 10
|
||
|
+#define NV50TCL_CLEAR_BUFFERS_LAYER_MASK 0x0007fc00
|
||
|
#define NV50TCL_COLOR_MASK(x) (0x00001a00+((x)*4))
|
||
|
#define NV50TCL_COLOR_MASK__SIZE 0x00000008
|
||
|
#define NV50TCL_COLOR_MASK_R_SHIFT 0
|
||
|
@@ -8434,23 +8861,26 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_VERTEX_ARRAY_ATTRIB(x) (0x00001ac0+((x)*4))
|
||
|
#define NV50TCL_VERTEX_ARRAY_ATTRIB__SIZE 0x00000010
|
||
|
#define NV50TCL_VERTEX_ARRAY_ATTRIB_BUFFER_SHIFT 0
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_BUFFER_MASK 0x000000ff
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_SHIFT 16
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_MASK 0x00ff0000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32_32_32_32 0x00080000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32_32_32 0x00100000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32_32 0x00200000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32 0x00900000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16_16_16_16 0x00180000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16_16_16 0x00280000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16_16 0x00780000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16 0x00d80000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8_8_8_8 0x00500000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8_8_8 0x00980000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8_8 0x00c00000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8 0x00e80000
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SHIFT 24
|
||
|
-#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_MASK 0xff000000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_BUFFER_MASK 0x0000000f
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_CONST (1 << 4)
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_OFFSET_SHIFT 5
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_OFFSET_MASK 0x0007ffe0
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_SHIFT 19
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_MASK 0x01f80000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 0x00080000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32 0x00100000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16_16 0x00180000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32_32 0x00200000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16_16 0x00280000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8_8 0x00500000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16_16 0x00780000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_32 0x00900000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8_8 0x00980000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8_8 0x00c00000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_16 0x00d80000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_FORMAT_8 0x00e80000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SHIFT 25
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_MASK 0x7e000000
|
||
|
#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT 0x7e000000
|
||
|
#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UNORM 0x24000000
|
||
|
#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SNORM 0x12000000
|
||
|
@@ -8458,58 +8888,154 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SSCALED 0x6c000000
|
||
|
#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UINT 0x48000000
|
||
|
#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SINT 0x36000000
|
||
|
+#define NV50TCL_VERTEX_ARRAY_ATTRIB_BGRA (1 << 31)
|
||
|
#define NV50TCL_QUERY_ADDRESS_HIGH 0x00001b00
|
||
|
#define NV50TCL_QUERY_ADDRESS_LOW 0x00001b04
|
||
|
#define NV50TCL_QUERY_COUNTER 0x00001b08
|
||
|
#define NV50TCL_QUERY_GET 0x00001b0c
|
||
|
|
||
|
|
||
|
+#define NV84TCL 0x00008297
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
+#define NVA0TCL 0x00008397
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
+#define NVA8TCL 0x00008597
|
||
|
+
|
||
|
+
|
||
|
+
|
||
|
#define NV50_COMPUTE 0x000050c0
|
||
|
|
||
|
-#define NV50_COMPUTE_DMA_UNK0 0x000001a0
|
||
|
-#define NV50_COMPUTE_DMA_STATUS 0x000001a4
|
||
|
-#define NV50_COMPUTE_DMA_UNK1 0x000001b8
|
||
|
-#define NV50_COMPUTE_DMA_UNK2 0x000001bc
|
||
|
-#define NV50_COMPUTE_DMA_UNK3 0x000001c0
|
||
|
-#define NV50_COMPUTE_UNK4_HIGH 0x00000210
|
||
|
-#define NV50_COMPUTE_UNK4_LOW 0x00000214
|
||
|
-#define NV50_COMPUTE_UNK5_HIGH 0x00000218
|
||
|
-#define NV50_COMPUTE_UNK5_LOW 0x0000021c
|
||
|
-#define NV50_COMPUTE_UNK6_HIGH 0x00000294
|
||
|
-#define NV50_COMPUTE_UNK6_LOW 0x00000298
|
||
|
-#define NV50_COMPUTE_CONST_BASE_HIGH 0x000002a4
|
||
|
-#define NV50_COMPUTE_CONST_BASE_LO 0x000002a8
|
||
|
-#define NV50_COMPUTE_CONST_SIZE_SEG 0x000002ac
|
||
|
-#define NV50_COMPUTE_REG_COUNT 0x000002c0
|
||
|
-#define NV50_COMPUTE_STATUS_HIGH 0x00000310
|
||
|
-#define NV50_COMPUTE_STATUS_LOW 0x00000314
|
||
|
-#define NV50_COMPUTE_EXECUTE 0x0000031c
|
||
|
+#define NV50_COMPUTE_NOP 0x00000100
|
||
|
+#define NV50_COMPUTE_NOTIFY 0x00000104
|
||
|
+#define NV50_COMPUTE_SERIALIZE 0x00000110
|
||
|
+#define NV50_COMPUTE_DMA_NOTIFY 0x00000180
|
||
|
+#define NV50_COMPUTE_DMA_GLOBAL 0x000001a0
|
||
|
+#define NV50_COMPUTE_DMA_QUERY 0x000001a4
|
||
|
+#define NV50_COMPUTE_DMA_LOCAL 0x000001b8
|
||
|
+#define NV50_COMPUTE_DMA_STACK 0x000001bc
|
||
|
+#define NV50_COMPUTE_DMA_CODE_CB 0x000001c0
|
||
|
+#define NV50_COMPUTE_DMA_TSC 0x000001c4
|
||
|
+#define NV50_COMPUTE_DMA_TIC 0x000001c8
|
||
|
+#define NV50_COMPUTE_DMA_TEXTURE 0x000001cc
|
||
|
+#define NV50_COMPUTE_CP_ADDRESS_HIGH 0x00000210
|
||
|
+#define NV50_COMPUTE_CP_ADDRESS_LOW 0x00000214
|
||
|
+#define NV50_COMPUTE_STACK_ADDRESS_HIGH 0x00000218
|
||
|
+#define NV50_COMPUTE_STACK_ADDRESS_LOW 0x0000021c
|
||
|
+#define NV50_COMPUTE_TSC_ADDRESS_HIGH 0x0000022c
|
||
|
+#define NV50_COMPUTE_TSC_ADDRESS_LOW 0x00000230
|
||
|
+#define NV50_COMPUTE_TSC_LIMIT 0x00000234
|
||
|
+#define NV50_COMPUTE_CB_ADDR 0x00000238
|
||
|
+#define NV50_COMPUTE_CB_ADDR_ID_SHIFT 8
|
||
|
+#define NV50_COMPUTE_CB_ADDR_ID_MASK 0x003fff00
|
||
|
+#define NV50_COMPUTE_CB_ADDR_BUFFER_SHIFT 0
|
||
|
+#define NV50_COMPUTE_CB_ADDR_BUFFER_MASK 0x0000007f
|
||
|
+#define NV50_COMPUTE_CB_DATA(x) (0x0000023c+((x)*4))
|
||
|
+#define NV50_COMPUTE_CB_DATA__SIZE 0x00000010
|
||
|
+#define NV50_COMPUTE_DELAY1 0x00000284
|
||
|
+#define NV50_COMPUTE_WATCHDOG_TIMER 0x00000288
|
||
|
+#define NV50_COMPUTE_DELAY2 0x0000028c
|
||
|
+#define NV50_COMPUTE_LOCAL_BASE_HIGH 0x00000294
|
||
|
+#define NV50_COMPUTE_LOCAL_BASE_LOW 0x00000298
|
||
|
+#define NV50_COMPUTE_LOCAL_SIZE_LOG 0x0000029c
|
||
|
+#define NV50_COMPUTE_CB_DEF_ADDRESS_HIGH 0x000002a4
|
||
|
+#define NV50_COMPUTE_CB_DEF_ADDRESS_LOW 0x000002a8
|
||
|
+#define NV50_COMPUTE_CB_DEF_SET 0x000002ac
|
||
|
+#define NV50_COMPUTE_CB_DEF_SET_SIZE_SHIFT 0
|
||
|
+#define NV50_COMPUTE_CB_DEF_SET_SIZE_MASK 0x0000ffff
|
||
|
+#define NV50_COMPUTE_CB_DEF_SET_BUFFER_SHIFT 16
|
||
|
+#define NV50_COMPUTE_CB_DEF_SET_BUFFER_MASK 0x007f0000
|
||
|
+#define NV50_COMPUTE_BLOCK_ALLOC 0x000002b4
|
||
|
+#define NV50_COMPUTE_BLOCK_ALLOC_THREADS_SHIFT 0
|
||
|
+#define NV50_COMPUTE_BLOCK_ALLOC_THREADS_MASK 0x0000ffff
|
||
|
+#define NV50_COMPUTE_BLOCK_ALLOC_BARRIERS_SHIFT 16
|
||
|
+#define NV50_COMPUTE_BLOCK_ALLOC_BARRIERS_MASK 0xffff0000
|
||
|
+#define NV50_COMPUTE_CP_REG_ALLOC_TEMP 0x000002c0
|
||
|
+#define NV50_COMPUTE_TIC_ADDRESS_HIGH 0x000002c4
|
||
|
+#define NV50_COMPUTE_TIC_ADDRESS_LOW 0x000002c8
|
||
|
+#define NV50_COMPUTE_TIC_LIMIT 0x000002cc
|
||
|
+#define NV50_COMPUTE_PM_SET(x) (0x000002d0+((x)*4))
|
||
|
+#define NV50_COMPUTE_PM_SET__SIZE 0x00000004
|
||
|
+#define NV50_COMPUTE_PM_CONTROL(x) (0x000002e0+((x)*4))
|
||
|
+#define NV50_COMPUTE_PM_CONTROL__SIZE 0x00000004
|
||
|
+#define NV50_COMPUTE_PM_CONTROL_UNK0 (1 << 0)
|
||
|
+#define NV50_COMPUTE_PM_CONTROL_UNK1_SHIFT 4
|
||
|
+#define NV50_COMPUTE_PM_CONTROL_UNK1_MASK 0x00000070
|
||
|
+#define NV50_COMPUTE_PM_CONTROL_UNK2_SHIFT 8
|
||
|
+#define NV50_COMPUTE_PM_CONTROL_UNK2_MASK 0xffffff00
|
||
|
+#define NV50_COMPUTE_QUERY_ADDRESS_HIGH 0x00000310
|
||
|
+#define NV50_COMPUTE_QUERY_ADDRESS_LOW 0x00000314
|
||
|
+#define NV50_COMPUTE_QUERY_COUNTER 0x00000318
|
||
|
+#define NV50_COMPUTE_QUERY_GET 0x0000031c
|
||
|
+#define NV50_COMPUTE_COND_ADDRESS_HIGH 0x00000320
|
||
|
+#define NV50_COMPUTE_COND_ADDRESS_LOW 0x00000324
|
||
|
+#define NV50_COMPUTE_COND_MODE 0x00000328
|
||
|
+#define NV50_COMPUTE_COND_MODE_NEVER 0x00000000
|
||
|
+#define NV50_COMPUTE_COND_MODE_ALWAYS 0x00000001
|
||
|
+#define NV50_COMPUTE_COND_MODE_RES 0x00000002
|
||
|
+#define NV50_COMPUTE_COND_MODE_NOT_RES_AND_NOT_ID 0x00000003
|
||
|
+#define NV50_COMPUTE_COND_MODE_RES_OR_ID 0x00000004
|
||
|
+#define NV50_COMPUTE_LAUNCH 0x00000368
|
||
|
#define NV50_COMPUTE_USER_PARAM_COUNT 0x00000374
|
||
|
-#define NV50_COMPUTE_GRIDDIM_YX 0x000003a4
|
||
|
+#define NV50_COMPUTE_USER_PARAM_COUNT_COUNT_SHIFT 8
|
||
|
+#define NV50_COMPUTE_USER_PARAM_COUNT_COUNT_MASK 0x0000ff00
|
||
|
+#define NV50_COMPUTE_LINKED_TSC 0x00000378
|
||
|
+#define NV50_COMPUTE_CODE_CB_FLUSH 0x00000380
|
||
|
+#define NV50_COMPUTE_GRIDDIM 0x000003a4
|
||
|
+#define NV50_COMPUTE_GRIDDIM_X_SHIFT 0
|
||
|
+#define NV50_COMPUTE_GRIDDIM_X_MASK 0x0000ffff
|
||
|
+#define NV50_COMPUTE_GRIDDIM_Y_SHIFT 16
|
||
|
+#define NV50_COMPUTE_GRIDDIM_Y_MASK 0xffff0000
|
||
|
#define NV50_COMPUTE_SHARED_SIZE 0x000003a8
|
||
|
#define NV50_COMPUTE_BLOCKDIM_YX 0x000003ac
|
||
|
+#define NV50_COMPUTE_BLOCKDIM_YX_X_SHIFT 0
|
||
|
+#define NV50_COMPUTE_BLOCKDIM_YX_X_MASK 0x0000ffff
|
||
|
+#define NV50_COMPUTE_BLOCKDIM_YX_Y_SHIFT 16
|
||
|
+#define NV50_COMPUTE_BLOCKDIM_YX_Y_MASK 0xffff0000
|
||
|
#define NV50_COMPUTE_BLOCKDIM_Z 0x000003b0
|
||
|
-#define NV50_COMPUTE_CALL_ADDRESS 0x000003b4
|
||
|
+#define NV50_COMPUTE_CP_START_ID 0x000003b4
|
||
|
+#define NV50_COMPUTE_WARP_HALVES 0x000003b8
|
||
|
+#define NV50_COMPUTE_TEX_LIMITS 0x000003bc
|
||
|
+#define NV50_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2_SHIFT 0
|
||
|
+#define NV50_COMPUTE_TEX_LIMITS_SAMPLERS_LOG2_MASK 0x0000000f
|
||
|
+#define NV50_COMPUTE_TEX_LIMITS_TEXTURES_LOG2_SHIFT 4
|
||
|
+#define NV50_COMPUTE_TEX_LIMITS_TEXTURES_LOG2_MASK 0x000000f0
|
||
|
+#define NV50_COMPUTE_BIND_TSC 0x000003c0
|
||
|
+#define NV50_COMPUTE_BIND_TSC_VALID (1 << 0)
|
||
|
+#define NV50_COMPUTE_BIND_TSC_SAMPLER_SHIFT 4
|
||
|
+#define NV50_COMPUTE_BIND_TSC_SAMPLER_MASK 0x000000f0
|
||
|
+#define NV50_COMPUTE_BIND_TSC_TSC_SHIFT 12
|
||
|
+#define NV50_COMPUTE_BIND_TSC_TSC_MASK 0x001ff000
|
||
|
+#define NV50_COMPUTE_BIND_TIC 0x000003c4
|
||
|
+#define NV50_COMPUTE_BIND_TIC_VALID (1 << 0)
|
||
|
+#define NV50_COMPUTE_BIND_TIC_TEXTURE_SHIFT 1
|
||
|
+#define NV50_COMPUTE_BIND_TIC_TEXTURE_MASK 0x000001fe
|
||
|
+#define NV50_COMPUTE_BIND_TIC_TIC_SHIFT 9
|
||
|
+#define NV50_COMPUTE_BIND_TIC_TIC_MASK 0x7ffffe00
|
||
|
+#define NV50_COMPUTE_SET_PROGRAM_CB 0x000003c8
|
||
|
+#define NV50_COMPUTE_SET_PROGRAM_CB_INDEX_SHIFT 8
|
||
|
+#define NV50_COMPUTE_SET_PROGRAM_CB_INDEX_MASK 0x00000f00
|
||
|
+#define NV50_COMPUTE_SET_PROGRAM_CB_BUFFER_SHIFT 12
|
||
|
+#define NV50_COMPUTE_SET_PROGRAM_CB_BUFFER_MASK 0x0007f000
|
||
|
+#define NV50_COMPUTE_SET_PROGRAM_CB_VALID (1 << 0)
|
||
|
#define NV50_COMPUTE_GLOBAL_BASE_HIGH(x) (0x00000400+((x)*32))
|
||
|
#define NV50_COMPUTE_GLOBAL_BASE_HIGH__SIZE 0x00000010
|
||
|
#define NV50_COMPUTE_GLOBAL_BASE_LOW(x) (0x00000404+((x)*32))
|
||
|
#define NV50_COMPUTE_GLOBAL_BASE_LOW__SIZE 0x00000010
|
||
|
-#define NV50_COMPUTE_GLOBAL_LIMIT_HIGH(x) (0x00000408+((x)*32))
|
||
|
-#define NV50_COMPUTE_GLOBAL_LIMIT_HIGH__SIZE 0x00000010
|
||
|
-#define NV50_COMPUTE_GLOBAL_LIMIT_LOW(x) (0x0000040c+((x)*32))
|
||
|
-#define NV50_COMPUTE_GLOBAL_LIMIT_LOW__SIZE 0x00000010
|
||
|
-#define NV50_COMPUTE_GLOBAL_UNK(x) (0x00000410+((x)*32))
|
||
|
-#define NV50_COMPUTE_GLOBAL_UNK__SIZE 0x00000010
|
||
|
+#define NV50_COMPUTE_GLOBAL_PITCH(x) (0x00000408+((x)*32))
|
||
|
+#define NV50_COMPUTE_GLOBAL_PITCH__SIZE 0x00000010
|
||
|
+#define NV50_COMPUTE_GLOBAL_LIMIT(x) (0x0000040c+((x)*32))
|
||
|
+#define NV50_COMPUTE_GLOBAL_LIMIT__SIZE 0x00000010
|
||
|
+#define NV50_COMPUTE_GLOBAL_MODE(x) (0x00000410+((x)*32))
|
||
|
+#define NV50_COMPUTE_GLOBAL_MODE__SIZE 0x00000010
|
||
|
+#define NV50_COMPUTE_GLOBAL_MODE_LINEAR (1 << 0)
|
||
|
+#define NV50_COMPUTE_GLOBAL_MODE_TILE_MODE_SHIFT 8
|
||
|
+#define NV50_COMPUTE_GLOBAL_MODE_TILE_MODE_MASK 0x00000f00
|
||
|
#define NV50_COMPUTE_USER_PARAM(x) (0x00000600+((x)*4))
|
||
|
#define NV50_COMPUTE_USER_PARAM__SIZE 0x00000040
|
||
|
|
||
|
|
||
|
-#define NV54TCL 0x00008297
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
-#define NVA0TCL 0x00008397
|
||
|
-
|
||
|
-
|
||
|
-
|
||
|
#endif /* NOUVEAU_REG_H */
|
||
|
diff --git a/nouveau/nouveau_private.h b/nouveau/nouveau_private.h
|
||
|
index 784afc9..39758d1 100644
|
||
|
--- a/nouveau/nouveau_private.h
|
||
|
+++ b/nouveau/nouveau_private.h
|
||
|
@@ -64,6 +64,8 @@ struct nouveau_pushbuf_priv {
|
||
|
|
||
|
int
|
||
|
nouveau_pushbuf_init(struct nouveau_channel *);
|
||
|
+void
|
||
|
+nouveau_pushbuf_fini(struct nouveau_channel *);
|
||
|
|
||
|
struct nouveau_channel_priv {
|
||
|
struct nouveau_channel base;
|
||
|
diff --git a/nouveau/nouveau_pushbuf.c b/nouveau/nouveau_pushbuf.c
|
||
|
index b90e923..7da3a47 100644
|
||
|
--- a/nouveau/nouveau_pushbuf.c
|
||
|
+++ b/nouveau/nouveau_pushbuf.c
|
||
|
@@ -80,13 +80,13 @@ nouveau_pushbuf_space(struct nouveau_channel *chan, unsigned min)
|
||
|
nvpb->pushbuf = NULL;
|
||
|
}
|
||
|
|
||
|
- nvpb->size = min < PB_MIN_USER_DWORDS ? PB_MIN_USER_DWORDS : min;
|
||
|
+ nvpb->size = min < PB_MIN_USER_DWORDS ? PB_MIN_USER_DWORDS : min;
|
||
|
nvpb->pushbuf = malloc(sizeof(uint32_t) * nvpb->size);
|
||
|
|
||
|
nvpb->base.channel = chan;
|
||
|
nvpb->base.remaining = nvpb->size;
|
||
|
nvpb->base.cur = nvpb->pushbuf;
|
||
|
-
|
||
|
+
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
@@ -165,11 +165,21 @@ nouveau_pushbuf_init(struct nouveau_channel *chan)
|
||
|
sizeof(struct drm_nouveau_gem_pushbuf_bo));
|
||
|
nvpb->relocs = calloc(NOUVEAU_GEM_MAX_RELOCS,
|
||
|
sizeof(struct drm_nouveau_gem_pushbuf_reloc));
|
||
|
-
|
||
|
+
|
||
|
chan->pushbuf = &nvpb->base;
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
+void
|
||
|
+nouveau_pushbuf_fini(struct nouveau_channel *chan)
|
||
|
+{
|
||
|
+ struct nouveau_channel_priv *nvchan = nouveau_channel(chan);
|
||
|
+ struct nouveau_pushbuf_priv *nvpb = &nvchan->pb;
|
||
|
+ nouveau_pushbuf_fini_call(chan);
|
||
|
+ free(nvpb->buffers);
|
||
|
+ free(nvpb->relocs);
|
||
|
+}
|
||
|
+
|
||
|
int
|
||
|
nouveau_pushbuf_flush(struct nouveau_channel *chan, unsigned min)
|
||
|
{
|
||
|
diff --git a/nouveau/nouveau_pushbuf.h b/nouveau/nouveau_pushbuf.h
|
||
|
index c7ac8c4..46982af 100644
|
||
|
--- a/nouveau/nouveau_pushbuf.h
|
||
|
+++ b/nouveau/nouveau_pushbuf.h
|
||
|
@@ -111,6 +111,14 @@ BEGIN_RING(struct nouveau_channel *chan, struct nouveau_grobj *gr,
|
||
|
chan->pushbuf->remaining -= (size + 1);
|
||
|
}
|
||
|
|
||
|
+/* non-incrementing BEGIN_RING */
|
||
|
+static __inline__ void
|
||
|
+BEGIN_RING_NI(struct nouveau_channel *chan, struct nouveau_grobj *gr,
|
||
|
+ unsigned mthd, unsigned size)
|
||
|
+{
|
||
|
+ BEGIN_RING(chan, gr, mthd | 0x40000000, size);
|
||
|
+}
|
||
|
+
|
||
|
static __inline__ void
|
||
|
FIRE_RING(struct nouveau_channel *chan)
|
||
|
{
|
||
|
diff --git a/nouveau/nouveau_resource.c b/nouveau/nouveau_resource.c
|
||
|
index 6bef756..7acaf7d 100644
|
||
|
--- a/nouveau/nouveau_resource.c
|
||
|
+++ b/nouveau/nouveau_resource.c
|
||
|
@@ -41,6 +41,15 @@ nouveau_resource_init(struct nouveau_resource **heap,
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
+void
|
||
|
+nouveau_resource_destroy(struct nouveau_resource **heap)
|
||
|
+{
|
||
|
+ if (!*heap)
|
||
|
+ return;
|
||
|
+ free(*heap);
|
||
|
+ *heap = NULL;
|
||
|
+}
|
||
|
+
|
||
|
int
|
||
|
nouveau_resource_alloc(struct nouveau_resource *heap, unsigned size, void *priv,
|
||
|
struct nouveau_resource **res)
|
||
|
diff --git a/nouveau/nouveau_resource.h b/nouveau/nouveau_resource.h
|
||
|
index 988d246..b760dfb 100644
|
||
|
--- a/nouveau/nouveau_resource.h
|
||
|
+++ b/nouveau/nouveau_resource.h
|
||
|
@@ -38,6 +38,9 @@ int
|
||
|
nouveau_resource_init(struct nouveau_resource **heap, unsigned start,
|
||
|
unsigned size);
|
||
|
|
||
|
+void
|
||
|
+nouveau_resource_destroy(struct nouveau_resource **heap);
|
||
|
+
|
||
|
int
|
||
|
nouveau_resource_alloc(struct nouveau_resource *heap, unsigned size, void *priv,
|
||
|
struct nouveau_resource **);
|
||
|
diff --git a/radeon/libdrm_radeon.pc.in b/radeon/libdrm_radeon.pc.in
|
||
|
index 3306844..ab703e1 100644
|
||
|
--- a/radeon/libdrm_radeon.pc.in
|
||
|
+++ b/radeon/libdrm_radeon.pc.in
|
||
|
@@ -5,6 +5,6 @@ includedir=@includedir@
|
||
|
|
||
|
Name: libdrm_radeon
|
||
|
Description: Userspace interface to kernel DRM services for radeon
|
||
|
-Version: 1.0.1
|
||
|
+Version: @PACKAGE_VERSION@
|
||
|
Libs: -L${libdir} -ldrm_radeon
|
||
|
Cflags: -I${includedir} -I${includedir}/drm
|
||
|
diff --git a/radeon/radeon_bo.c b/radeon/radeon_bo.c
|
||
|
index eb3a1bc..6a0f8e7 100644
|
||
|
--- a/radeon/radeon_bo.c
|
||
|
+++ b/radeon/radeon_bo.c
|
||
|
@@ -1,8 +1,38 @@
|
||
|
+/*
|
||
|
+ * Copyright © 2008 Dave Airlie
|
||
|
+ * Copyright © 2008 Jérôme Glisse
|
||
|
+ * All Rights Reserved.
|
||
|
+ *
|
||
|
+ * Permission is hereby granted, free of charge, to any person obtaining
|
||
|
+ * a copy of this software and associated documentation files (the
|
||
|
+ * "Software"), to deal in the Software without restriction, including
|
||
|
+ * without limitation the rights to use, copy, modify, merge, publish,
|
||
|
+ * distribute, sub license, and/or sell copies of the Software, and to
|
||
|
+ * permit persons to whom the Software is furnished to do so, subject to
|
||
|
+ * the following conditions:
|
||
|
+ *
|
||
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||
|
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||
|
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||
|
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
|
||
|
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||
|
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||
|
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
+ *
|
||
|
+ * The above copyright notice and this permission notice (including the
|
||
|
+ * next paragraph) shall be included in all copies or substantial portions
|
||
|
+ * of the Software.
|
||
|
+ */
|
||
|
+/*
|
||
|
+ * Authors:
|
||
|
+ * Dave Airlie
|
||
|
+ * Jérôme Glisse <glisse@freedesktop.org>
|
||
|
+ */
|
||
|
#include <radeon_bo.h>
|
||
|
#include <radeon_bo_int.h>
|
||
|
|
||
|
-void radeon_bo_debug(struct radeon_bo *bo,
|
||
|
- const char *op)
|
||
|
+void radeon_bo_debug(struct radeon_bo *bo, const char *op)
|
||
|
{
|
||
|
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
|
||
|
|
||
|
@@ -11,11 +41,11 @@ void radeon_bo_debug(struct radeon_bo *bo,
|
||
|
}
|
||
|
|
||
|
struct radeon_bo *radeon_bo_open(struct radeon_bo_manager *bom,
|
||
|
- uint32_t handle,
|
||
|
- uint32_t size,
|
||
|
- uint32_t alignment,
|
||
|
- uint32_t domains,
|
||
|
- uint32_t flags)
|
||
|
+ uint32_t handle,
|
||
|
+ uint32_t size,
|
||
|
+ uint32_t alignment,
|
||
|
+ uint32_t domains,
|
||
|
+ uint32_t flags)
|
||
|
{
|
||
|
struct radeon_bo *bo;
|
||
|
bo = bom->funcs->bo_open(bom, handle, size, alignment, domains, flags);
|
||
|
@@ -55,26 +85,25 @@ int radeon_bo_wait(struct radeon_bo *bo)
|
||
|
{
|
||
|
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
|
||
|
if (!boi->bom->funcs->bo_wait)
|
||
|
- return 0;
|
||
|
+ return 0;
|
||
|
return boi->bom->funcs->bo_wait(boi);
|
||
|
}
|
||
|
|
||
|
-int radeon_bo_is_busy(struct radeon_bo *bo,
|
||
|
- uint32_t *domain)
|
||
|
+int radeon_bo_is_busy(struct radeon_bo *bo, uint32_t *domain)
|
||
|
{
|
||
|
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
|
||
|
return boi->bom->funcs->bo_is_busy(boi, domain);
|
||
|
}
|
||
|
|
||
|
int radeon_bo_set_tiling(struct radeon_bo *bo,
|
||
|
- uint32_t tiling_flags, uint32_t pitch)
|
||
|
+ uint32_t tiling_flags, uint32_t pitch)
|
||
|
{
|
||
|
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
|
||
|
return boi->bom->funcs->bo_set_tiling(boi, tiling_flags, pitch);
|
||
|
}
|
||
|
|
||
|
int radeon_bo_get_tiling(struct radeon_bo *bo,
|
||
|
- uint32_t *tiling_flags, uint32_t *pitch)
|
||
|
+ uint32_t *tiling_flags, uint32_t *pitch)
|
||
|
{
|
||
|
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
|
||
|
return boi->bom->funcs->bo_get_tiling(boi, tiling_flags, pitch);
|
||
|
@@ -84,12 +113,11 @@ int radeon_bo_is_static(struct radeon_bo *bo)
|
||
|
{
|
||
|
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
|
||
|
if (boi->bom->funcs->bo_is_static)
|
||
|
- return boi->bom->funcs->bo_is_static(boi);
|
||
|
+ return boi->bom->funcs->bo_is_static(boi);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
-int radeon_bo_is_referenced_by_cs(struct radeon_bo *bo,
|
||
|
- struct radeon_cs *cs)
|
||
|
+int radeon_bo_is_referenced_by_cs(struct radeon_bo *bo, struct radeon_cs *cs)
|
||
|
{
|
||
|
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
|
||
|
return boi->cref > 1;
|
||
|
@@ -107,7 +135,7 @@ uint32_t radeon_bo_get_src_domain(struct radeon_bo *bo)
|
||
|
|
||
|
src_domain = boi->space_accounted & 0xffff;
|
||
|
if (!src_domain)
|
||
|
- src_domain = boi->space_accounted >> 16;
|
||
|
+ src_domain = boi->space_accounted >> 16;
|
||
|
|
||
|
return src_domain;
|
||
|
}
|
||
|
diff --git a/radeon/radeon_bo.h b/radeon/radeon_bo.h
|
||
|
index beb2369..8859c2c 100644
|
||
|
--- a/radeon/radeon_bo.h
|
||
|
+++ b/radeon/radeon_bo.h
|
||
|
@@ -1,7 +1,7 @@
|
||
|
-/*
|
||
|
+/*
|
||
|
* Copyright © 2008 Jérôme Glisse
|
||
|
* All Rights Reserved.
|
||
|
- *
|
||
|
+ *
|
||
|
* Permission is hereby granted, free of charge, to any person obtaining
|
||
|
* a copy of this software and associated documentation files (the
|
||
|
* "Software"), to deal in the Software without restriction, including
|
||
|
@@ -9,14 +9,14 @@
|
||
|
* distribute, sub license, and/or sell copies of the Software, and to
|
||
|
* permit persons to whom the Software is furnished to do so, subject to
|
||
|
* the following conditions:
|
||
|
- *
|
||
|
+ *
|
||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||
|
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
|
||
|
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||
|
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
*
|
||
|
* The above copyright notice and this permission notice (including the
|
||
|
@@ -49,15 +49,14 @@ struct radeon_bo {
|
||
|
|
||
|
struct radeon_bo_manager;
|
||
|
|
||
|
-void radeon_bo_debug(struct radeon_bo *bo,
|
||
|
- const char *op);
|
||
|
+void radeon_bo_debug(struct radeon_bo *bo, const char *op);
|
||
|
|
||
|
struct radeon_bo *radeon_bo_open(struct radeon_bo_manager *bom,
|
||
|
- uint32_t handle,
|
||
|
- uint32_t size,
|
||
|
- uint32_t alignment,
|
||
|
- uint32_t domains,
|
||
|
- uint32_t flags);
|
||
|
+ uint32_t handle,
|
||
|
+ uint32_t size,
|
||
|
+ uint32_t alignment,
|
||
|
+ uint32_t domains,
|
||
|
+ uint32_t flags);
|
||
|
|
||
|
void radeon_bo_ref(struct radeon_bo *bo);
|
||
|
struct radeon_bo *radeon_bo_unref(struct radeon_bo *bo);
|
||
|
@@ -68,8 +67,7 @@ int radeon_bo_is_busy(struct radeon_bo *bo, uint32_t *domain);
|
||
|
int radeon_bo_set_tiling(struct radeon_bo *bo, uint32_t tiling_flags, uint32_t pitch);
|
||
|
int radeon_bo_get_tiling(struct radeon_bo *bo, uint32_t *tiling_flags, uint32_t *pitch);
|
||
|
int radeon_bo_is_static(struct radeon_bo *bo);
|
||
|
-int radeon_bo_is_referenced_by_cs(struct radeon_bo *bo,
|
||
|
- struct radeon_cs *cs);
|
||
|
+int radeon_bo_is_referenced_by_cs(struct radeon_bo *bo, struct radeon_cs *cs);
|
||
|
uint32_t radeon_bo_get_handle(struct radeon_bo *bo);
|
||
|
uint32_t radeon_bo_get_src_domain(struct radeon_bo *bo);
|
||
|
#endif
|
||
|
diff --git a/radeon/radeon_bo_gem.c b/radeon/radeon_bo_gem.c
|
||
|
index 9bf119a..bc8058d 100644
|
||
|
--- a/radeon/radeon_bo_gem.c
|
||
|
+++ b/radeon/radeon_bo_gem.c
|
||
|
@@ -1,8 +1,8 @@
|
||
|
-/*
|
||
|
+/*
|
||
|
* Copyright © 2008 Dave Airlie
|
||
|
* Copyright © 2008 Jérôme Glisse
|
||
|
* All Rights Reserved.
|
||
|
- *
|
||
|
+ *
|
||
|
* Permission is hereby granted, free of charge, to any person obtaining
|
||
|
* a copy of this software and associated documentation files (the
|
||
|
* "Software"), to deal in the Software without restriction, including
|
||
|
@@ -10,14 +10,14 @@
|
||
|
* distribute, sub license, and/or sell copies of the Software, and to
|
||
|
* permit persons to whom the Software is furnished to do so, subject to
|
||
|
* the following conditions:
|
||
|
- *
|
||
|
+ *
|
||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||
|
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
|
||
|
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||
|
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
*
|
||
|
* The above copyright notice and this permission notice (including the
|
||
|
@@ -156,7 +156,7 @@ static int bo_map(struct radeon_bo_int *boi, int write)
|
||
|
return 0;
|
||
|
}
|
||
|
if (bo_gem->priv_ptr) {
|
||
|
- goto wait;
|
||
|
+ goto wait;
|
||
|
}
|
||
|
|
||
|
boi->ptr = NULL;
|
||
|
@@ -223,14 +223,14 @@ static int bo_is_busy(struct radeon_bo_int *boi, uint32_t *domain)
|
||
|
args.domain = 0;
|
||
|
|
||
|
ret = drmCommandWriteRead(boi->bom->fd, DRM_RADEON_GEM_BUSY,
|
||
|
- &args, sizeof(args));
|
||
|
+ &args, sizeof(args));
|
||
|
|
||
|
*domain = args.domain;
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static int bo_set_tiling(struct radeon_bo_int *boi, uint32_t tiling_flags,
|
||
|
- uint32_t pitch)
|
||
|
+ uint32_t pitch)
|
||
|
{
|
||
|
struct drm_radeon_gem_set_tiling args;
|
||
|
int r;
|
||
|
@@ -240,14 +240,14 @@ static int bo_set_tiling(struct radeon_bo_int *boi, uint32_t tiling_flags,
|
||
|
args.pitch = pitch;
|
||
|
|
||
|
r = drmCommandWriteRead(boi->bom->fd,
|
||
|
- DRM_RADEON_GEM_SET_TILING,
|
||
|
- &args,
|
||
|
- sizeof(args));
|
||
|
+ DRM_RADEON_GEM_SET_TILING,
|
||
|
+ &args,
|
||
|
+ sizeof(args));
|
||
|
return r;
|
||
|
}
|
||
|
|
||
|
static int bo_get_tiling(struct radeon_bo_int *boi, uint32_t *tiling_flags,
|
||
|
- uint32_t *pitch)
|
||
|
+ uint32_t *pitch)
|
||
|
{
|
||
|
struct drm_radeon_gem_set_tiling args;
|
||
|
int r;
|
||
|
@@ -255,12 +255,12 @@ static int bo_get_tiling(struct radeon_bo_int *boi, uint32_t *tiling_flags,
|
||
|
args.handle = boi->handle;
|
||
|
|
||
|
r = drmCommandWriteRead(boi->bom->fd,
|
||
|
- DRM_RADEON_GEM_GET_TILING,
|
||
|
- &args,
|
||
|
- sizeof(args));
|
||
|
+ DRM_RADEON_GEM_GET_TILING,
|
||
|
+ &args,
|
||
|
+ sizeof(args));
|
||
|
|
||
|
if (r)
|
||
|
- return r;
|
||
|
+ return r;
|
||
|
|
||
|
*tiling_flags = args.tiling_flags;
|
||
|
*pitch = args.pitch;
|
||
|
@@ -318,7 +318,7 @@ int radeon_gem_get_kernel_name(struct radeon_bo *bo, uint32_t *name)
|
||
|
flink.handle = bo->handle;
|
||
|
r = drmIoctl(boi->bom->fd, DRM_IOCTL_GEM_FLINK, &flink);
|
||
|
if (r) {
|
||
|
- return r;
|
||
|
+ return r;
|
||
|
}
|
||
|
*name = flink.name;
|
||
|
return 0;
|
||
|
diff --git a/radeon/radeon_bo_gem.h b/radeon/radeon_bo_gem.h
|
||
|
index 4a8df9a..c56c58e 100644
|
||
|
--- a/radeon/radeon_bo_gem.h
|
||
|
+++ b/radeon/radeon_bo_gem.h
|
||
|
@@ -1,8 +1,8 @@
|
||
|
-/*
|
||
|
+/*
|
||
|
* Copyright © 2008 Dave Airlie
|
||
|
* Copyright © 2008 Jérôme Glisse
|
||
|
* All Rights Reserved.
|
||
|
- *
|
||
|
+ *
|
||
|
* Permission is hereby granted, free of charge, to any person obtaining
|
||
|
* a copy of this software and associated documentation files (the
|
||
|
* "Software"), to deal in the Software without restriction, including
|
||
|
@@ -10,14 +10,14 @@
|
||
|
* distribute, sub license, and/or sell copies of the Software, and to
|
||
|
* permit persons to whom the Software is furnished to do so, subject to
|
||
|
* the following conditions:
|
||
|
- *
|
||
|
+ *
|
||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||
|
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
|
||
|
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||
|
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
*
|
||
|
* The above copyright notice and this permission notice (including the
|
||
|
diff --git a/radeon/radeon_bo_int.h b/radeon/radeon_bo_int.h
|
||
|
index 190c332..9589ead 100644
|
||
|
--- a/radeon/radeon_bo_int.h
|
||
|
+++ b/radeon/radeon_bo_int.h
|
||
|
@@ -35,9 +35,9 @@ struct radeon_bo_funcs {
|
||
|
int (*bo_wait)(struct radeon_bo_int *bo);
|
||
|
int (*bo_is_static)(struct radeon_bo_int *bo);
|
||
|
int (*bo_set_tiling)(struct radeon_bo_int *bo, uint32_t tiling_flags,
|
||
|
- uint32_t pitch);
|
||
|
+ uint32_t pitch);
|
||
|
int (*bo_get_tiling)(struct radeon_bo_int *bo, uint32_t *tiling_flags,
|
||
|
- uint32_t *pitch);
|
||
|
+ uint32_t *pitch);
|
||
|
int (*bo_is_busy)(struct radeon_bo_int *bo, uint32_t *domain);
|
||
|
int (*bo_is_referenced_by_cs)(struct radeon_bo_int *bo, struct radeon_cs *cs);
|
||
|
};
|
||
|
diff --git a/radeon/radeon_cs.c b/radeon/radeon_cs.c
|
||
|
index 689eb81..cc9be39 100644
|
||
|
--- a/radeon/radeon_cs.c
|
||
|
+++ b/radeon/radeon_cs.c
|
||
|
@@ -3,42 +3,41 @@
|
||
|
#include "radeon_cs.h"
|
||
|
#include "radeon_cs_int.h"
|
||
|
|
||
|
-struct radeon_cs *radeon_cs_create(struct radeon_cs_manager *csm,
|
||
|
- uint32_t ndw)
|
||
|
+struct radeon_cs *radeon_cs_create(struct radeon_cs_manager *csm, uint32_t ndw)
|
||
|
{
|
||
|
struct radeon_cs_int *csi = csm->funcs->cs_create(csm, ndw);
|
||
|
return (struct radeon_cs *)csi;
|
||
|
}
|
||
|
|
||
|
int radeon_cs_write_reloc(struct radeon_cs *cs,
|
||
|
- struct radeon_bo *bo,
|
||
|
- uint32_t read_domain,
|
||
|
- uint32_t write_domain,
|
||
|
- uint32_t flags)
|
||
|
+ struct radeon_bo *bo,
|
||
|
+ uint32_t read_domain,
|
||
|
+ uint32_t write_domain,
|
||
|
+ uint32_t flags)
|
||
|
{
|
||
|
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
|
||
|
|
||
|
return csi->csm->funcs->cs_write_reloc(csi,
|
||
|
- bo,
|
||
|
- read_domain,
|
||
|
- write_domain,
|
||
|
- flags);
|
||
|
+ bo,
|
||
|
+ read_domain,
|
||
|
+ write_domain,
|
||
|
+ flags);
|
||
|
}
|
||
|
|
||
|
int radeon_cs_begin(struct radeon_cs *cs,
|
||
|
- uint32_t ndw,
|
||
|
- const char *file,
|
||
|
- const char *func,
|
||
|
- int line)
|
||
|
+ uint32_t ndw,
|
||
|
+ const char *file,
|
||
|
+ const char *func,
|
||
|
+ int line)
|
||
|
{
|
||
|
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
|
||
|
return csi->csm->funcs->cs_begin(csi, ndw, file, func, line);
|
||
|
}
|
||
|
|
||
|
int radeon_cs_end(struct radeon_cs *cs,
|
||
|
- const char *file,
|
||
|
- const char *func,
|
||
|
- int line)
|
||
|
+ const char *file,
|
||
|
+ const char *func,
|
||
|
+ int line)
|
||
|
{
|
||
|
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
|
||
|
return csi->csm->funcs->cs_end(csi, file, func, line);
|
||
|
@@ -78,9 +77,9 @@ void radeon_cs_set_limit(struct radeon_cs *cs, uint32_t domain, uint32_t limit)
|
||
|
{
|
||
|
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
|
||
|
if (domain == RADEON_GEM_DOMAIN_VRAM)
|
||
|
- csi->csm->vram_limit = limit;
|
||
|
+ csi->csm->vram_limit = limit;
|
||
|
else
|
||
|
- csi->csm->gart_limit = limit;
|
||
|
+ csi->csm->gart_limit = limit;
|
||
|
}
|
||
|
|
||
|
void radeon_cs_space_set_flush(struct radeon_cs *cs, void (*fn)(void *), void *data)
|
||
|
@@ -89,4 +88,3 @@ void radeon_cs_space_set_flush(struct radeon_cs *cs, void (*fn)(void *), void *d
|
||
|
csi->space_flush_fn = fn;
|
||
|
csi->space_flush_data = data;
|
||
|
}
|
||
|
-
|
||
|
diff --git a/radeon/radeon_cs.h b/radeon/radeon_cs.h
|
||
|
index 0954ca0..49d5d9a 100644
|
||
|
--- a/radeon/radeon_cs.h
|
||
|
+++ b/radeon/radeon_cs.h
|
||
|
@@ -1,8 +1,8 @@
|
||
|
-/*
|
||
|
+/*
|
||
|
* Copyright © 2008 Nicolai Haehnle
|
||
|
* Copyright © 2008 Jérôme Glisse
|
||
|
* All Rights Reserved.
|
||
|
- *
|
||
|
+ *
|
||
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||
|
* copy of this software and associated documentation files (the
|
||
|
* "Software"), to deal in the Software without restriction, including
|
||
|
@@ -10,13 +10,13 @@
|
||
|
* distribute, sub license, and/or sell copies of the Software, and to
|
||
|
* permit persons to whom the Software is furnished to do so, subject to
|
||
|
* the following conditions:
|
||
|
- *
|
||
|
+ *
|
||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||
|
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||
|
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||
|
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||
|
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
*
|
||
|
* The above copyright notice and this permission notice (including the
|
||
|
@@ -63,16 +63,16 @@ struct radeon_cs {
|
||
|
struct radeon_cs_manager;
|
||
|
|
||
|
extern struct radeon_cs *radeon_cs_create(struct radeon_cs_manager *csm,
|
||
|
- uint32_t ndw);
|
||
|
+ uint32_t ndw);
|
||
|
|
||
|
extern int radeon_cs_begin(struct radeon_cs *cs,
|
||
|
- uint32_t ndw,
|
||
|
- const char *file,
|
||
|
- const char *func, int line);
|
||
|
+ uint32_t ndw,
|
||
|
+ const char *file,
|
||
|
+ const char *func, int line);
|
||
|
extern int radeon_cs_end(struct radeon_cs *cs,
|
||
|
- const char *file,
|
||
|
- const char *func,
|
||
|
- int line);
|
||
|
+ const char *file,
|
||
|
+ const char *func,
|
||
|
+ int line);
|
||
|
extern int radeon_cs_emit(struct radeon_cs *cs);
|
||
|
extern int radeon_cs_destroy(struct radeon_cs *cs);
|
||
|
extern int radeon_cs_erase(struct radeon_cs *cs);
|
||
|
@@ -81,10 +81,10 @@ extern void radeon_cs_print(struct radeon_cs *cs, FILE *file);
|
||
|
extern void radeon_cs_set_limit(struct radeon_cs *cs, uint32_t domain, uint32_t limit);
|
||
|
extern void radeon_cs_space_set_flush(struct radeon_cs *cs, void (*fn)(void *), void *data);
|
||
|
extern int radeon_cs_write_reloc(struct radeon_cs *cs,
|
||
|
- struct radeon_bo *bo,
|
||
|
- uint32_t read_domain,
|
||
|
- uint32_t write_domain,
|
||
|
- uint32_t flags);
|
||
|
+ struct radeon_bo *bo,
|
||
|
+ uint32_t read_domain,
|
||
|
+ uint32_t write_domain,
|
||
|
+ uint32_t flags);
|
||
|
|
||
|
/*
|
||
|
* add a persistent BO to the list
|
||
|
@@ -94,9 +94,9 @@ extern int radeon_cs_write_reloc(struct radeon_cs *cs,
|
||
|
* is a state emission with a color/textures etc followed by a bunch of vertices.
|
||
|
*/
|
||
|
void radeon_cs_space_add_persistent_bo(struct radeon_cs *cs,
|
||
|
- struct radeon_bo *bo,
|
||
|
- uint32_t read_domains,
|
||
|
- uint32_t write_domain);
|
||
|
+ struct radeon_bo *bo,
|
||
|
+ uint32_t read_domains,
|
||
|
+ uint32_t write_domain);
|
||
|
|
||
|
/* reset the persistent BO list */
|
||
|
void radeon_cs_space_reset_bos(struct radeon_cs *cs);
|
||
|
@@ -108,9 +108,9 @@ int radeon_cs_space_check(struct radeon_cs *cs);
|
||
|
* a temporary BO is like a DMA buffer, which gets flushed with the
|
||
|
* command buffer */
|
||
|
int radeon_cs_space_check_with_bo(struct radeon_cs *cs,
|
||
|
- struct radeon_bo *bo,
|
||
|
- uint32_t read_domains,
|
||
|
- uint32_t write_domain);
|
||
|
+ struct radeon_bo *bo,
|
||
|
+ uint32_t read_domains,
|
||
|
+ uint32_t write_domain);
|
||
|
|
||
|
static inline void radeon_cs_write_dword(struct radeon_cs *cs, uint32_t dword)
|
||
|
{
|
||
|
@@ -130,12 +130,12 @@ static inline void radeon_cs_write_qword(struct radeon_cs *cs, uint64_t qword)
|
||
|
}
|
||
|
|
||
|
static inline void radeon_cs_write_table(struct radeon_cs *cs,
|
||
|
- void *data, uint32_t size)
|
||
|
+ void *data, uint32_t size)
|
||
|
{
|
||
|
memcpy(cs->packets + cs->cdw, data, size * 4);
|
||
|
cs->cdw += size;
|
||
|
if (cs->section_ndw) {
|
||
|
- cs->section_cdw += size;
|
||
|
+ cs->section_cdw += size;
|
||
|
}
|
||
|
}
|
||
|
#endif
|
||
|
diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c
|
||
|
index 1e53099..c2301ad 100644
|
||
|
--- a/radeon/radeon_cs_gem.c
|
||
|
+++ b/radeon/radeon_cs_gem.c
|
||
|
@@ -1,7 +1,7 @@
|
||
|
-/*
|
||
|
+/*
|
||
|
* Copyright © 2008 Jérôme Glisse
|
||
|
* All Rights Reserved.
|
||
|
- *
|
||
|
+ *
|
||
|
* Permission is hereby granted, free of charge, to any person obtaining
|
||
|
* a copy of this software and associated documentation files (the
|
||
|
* "Software"), to deal in the Software without restriction, including
|
||
|
@@ -9,14 +9,14 @@
|
||
|
* distribute, sub license, and/or sell copies of the Software, and to
|
||
|
* permit persons to whom the Software is furnished to do so, subject to
|
||
|
* the following conditions:
|
||
|
- *
|
||
|
+ *
|
||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||
|
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
|
||
|
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||
|
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
*
|
||
|
* The above copyright notice and this permission notice (including the
|
||
|
@@ -43,6 +43,11 @@
|
||
|
#include "xf86drm.h"
|
||
|
#include "radeon_drm.h"
|
||
|
|
||
|
+struct radeon_cs_manager_gem {
|
||
|
+ struct radeon_cs_manager base;
|
||
|
+ uint32_t device_id;
|
||
|
+};
|
||
|
+
|
||
|
#pragma pack(1)
|
||
|
struct cs_reloc_gem {
|
||
|
uint32_t handle;
|
||
|
@@ -227,7 +232,7 @@ static int cs_gem_begin(struct radeon_cs_int *cs,
|
||
|
if (cs->cdw + ndw > cs->ndw) {
|
||
|
uint32_t tmp, *ptr;
|
||
|
|
||
|
- /* round up the required size to a multiple of 1024 */
|
||
|
+ /* round up the required size to a multiple of 1024 */
|
||
|
tmp = (cs->cdw + ndw + 0x3FF) & (~0x3FF);
|
||
|
ptr = (uint32_t*)realloc(cs->packets, 4 * tmp);
|
||
|
if (ptr == NULL) {
|
||
|
@@ -279,9 +284,9 @@ static int cs_gem_emit(struct radeon_cs_int *cs)
|
||
|
r = drmCommandWriteRead(cs->csm->fd, DRM_RADEON_CS,
|
||
|
&csg->cs, sizeof(struct drm_radeon_cs));
|
||
|
for (i = 0; i < csg->base.crelocs; i++) {
|
||
|
- csg->relocs_bo[i]->space_accounted = 0;
|
||
|
- radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]);
|
||
|
- csg->relocs_bo[i] = NULL;
|
||
|
+ csg->relocs_bo[i]->space_accounted = 0;
|
||
|
+ radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]);
|
||
|
+ csg->relocs_bo[i] = NULL;
|
||
|
}
|
||
|
|
||
|
cs->csm->read_used = 0;
|
||
|
@@ -309,7 +314,7 @@ static int cs_gem_erase(struct radeon_cs_int *cs)
|
||
|
if (csg->relocs_bo) {
|
||
|
for (i = 0; i < csg->base.crelocs; i++) {
|
||
|
if (csg->relocs_bo[i]) {
|
||
|
- radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]);
|
||
|
+ radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]);
|
||
|
csg->relocs_bo[i] = NULL;
|
||
|
}
|
||
|
}
|
||
|
@@ -328,104 +333,18 @@ static int cs_gem_need_flush(struct radeon_cs_int *cs)
|
||
|
return 0; //(cs->relocs_total_size > (32*1024*1024));
|
||
|
}
|
||
|
|
||
|
-#define PACKET_TYPE0 0
|
||
|
-#define PACKET_TYPE1 1
|
||
|
-#define PACKET_TYPE2 2
|
||
|
-#define PACKET_TYPE3 3
|
||
|
-
|
||
|
-#define PACKET3_NOP 0x10
|
||
|
-#define PACKET3_SET_SCISSORS 0x1E
|
||
|
-#define PACKET3_3D_DRAW_VBUF 0x28
|
||
|
-#define PACKET3_3D_DRAW_IMMD 0x29
|
||
|
-#define PACKET3_3D_DRAW_INDX 0x2A
|
||
|
-#define PACKET3_3D_LOAD_VBPNTR 0x2F
|
||
|
-#define PACKET3_INDX_BUFFER 0x33
|
||
|
-#define PACKET3_3D_DRAW_VBUF_2 0x34
|
||
|
-#define PACKET3_3D_DRAW_IMMD_2 0x35
|
||
|
-#define PACKET3_3D_DRAW_INDX_2 0x36
|
||
|
-
|
||
|
-#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
|
||
|
-#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
|
||
|
-#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
|
||
|
-#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
|
||
|
-#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
|
||
|
-
|
||
|
static void cs_gem_print(struct radeon_cs_int *cs, FILE *file)
|
||
|
{
|
||
|
- unsigned opcode;
|
||
|
- unsigned reg;
|
||
|
- unsigned cnt;
|
||
|
- unsigned int i, j;
|
||
|
-
|
||
|
- for (i = 0; i < cs->cdw;) {
|
||
|
- cnt = CP_PACKET_GET_COUNT(cs->packets[i]) + 1;
|
||
|
- switch (CP_PACKET_GET_TYPE(cs->packets[i])) {
|
||
|
- case PACKET_TYPE0:
|
||
|
- fprintf(file, "Pkt0 at %d (%d dwords):\n", i, cnt);
|
||
|
- reg = CP_PACKET0_GET_REG(cs->packets[i]);
|
||
|
- if (CP_PACKET0_GET_ONE_REG_WR(cs->packets[i++])) {
|
||
|
- for (j = 0; j < cnt; j++) {
|
||
|
- fprintf(file, " 0x%08X -> 0x%04X\n",
|
||
|
- cs->packets[i++], reg);
|
||
|
- }
|
||
|
- } else {
|
||
|
- for (j = 0; j < cnt; j++) {
|
||
|
- fprintf(file, " 0x%08X -> 0x%04X\n",
|
||
|
- cs->packets[i++], reg);
|
||
|
- reg += 4;
|
||
|
- }
|
||
|
- }
|
||
|
- break;
|
||
|
- case PACKET_TYPE3:
|
||
|
- fprintf(file, "Pkt3 at %d :\n", i);
|
||
|
- opcode = CP_PACKET3_GET_OPCODE(cs->packets[i++]);
|
||
|
- switch (opcode) {
|
||
|
- case PACKET3_NOP:
|
||
|
- fprintf(file, " PACKET3_NOP:\n");
|
||
|
- break;
|
||
|
- case PACKET3_3D_DRAW_VBUF:
|
||
|
- fprintf(file, " PACKET3_3D_DRAW_VBUF:\n");
|
||
|
- break;
|
||
|
- case PACKET3_3D_DRAW_IMMD:
|
||
|
- fprintf(file, " PACKET3_3D_DRAW_IMMD:\n");
|
||
|
- break;
|
||
|
- case PACKET3_3D_DRAW_INDX:
|
||
|
- fprintf(file, " PACKET3_3D_DRAW_INDX:\n");
|
||
|
- break;
|
||
|
- case PACKET3_3D_LOAD_VBPNTR:
|
||
|
- fprintf(file, " PACKET3_3D_LOAD_VBPNTR:\n");
|
||
|
- break;
|
||
|
- case PACKET3_INDX_BUFFER:
|
||
|
- fprintf(file, " PACKET3_INDX_BUFFER:\n");
|
||
|
- break;
|
||
|
- case PACKET3_3D_DRAW_VBUF_2:
|
||
|
- fprintf(file, " PACKET3_3D_DRAW_VBUF_2:\n");
|
||
|
- break;
|
||
|
- case PACKET3_3D_DRAW_IMMD_2:
|
||
|
- fprintf(file, " PACKET3_3D_DRAW_IMMD_2:\n");
|
||
|
- break;
|
||
|
- case PACKET3_3D_DRAW_INDX_2:
|
||
|
- fprintf(file, " PACKET3_3D_DRAW_INDX_2:\n");
|
||
|
- break;
|
||
|
- default:
|
||
|
- fprintf(file, "Unknow opcode 0x%02X at %d\n", opcode, i);
|
||
|
- return;
|
||
|
- }
|
||
|
- for (j = 0; j < cnt; j++) {
|
||
|
- fprintf(file, " 0x%08X\n", cs->packets[i++]);
|
||
|
- }
|
||
|
- break;
|
||
|
- case PACKET_TYPE1:
|
||
|
- case PACKET_TYPE2:
|
||
|
- default:
|
||
|
- fprintf(file, "Unknow packet 0x%08X at %d\n", cs->packets[i], i);
|
||
|
- return;
|
||
|
- }
|
||
|
+ struct radeon_cs_manager_gem *csm;
|
||
|
+ unsigned int i;
|
||
|
+
|
||
|
+ csm = (struct radeon_cs_manager_gem *)cs->csm;
|
||
|
+ fprintf(file, "VENDORID:DEVICEID 0x%04X:0x%04X\n", 0x1002, csm->device_id);
|
||
|
+ for (i = 0; i < cs->cdw; i++) {
|
||
|
+ fprintf(file, "0x%08X\n", cs->packets[i]);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
-
|
||
|
-
|
||
|
static struct radeon_cs_funcs radeon_cs_gem_funcs = {
|
||
|
cs_gem_create,
|
||
|
cs_gem_write_reloc,
|
||
|
@@ -438,18 +357,31 @@ static struct radeon_cs_funcs radeon_cs_gem_funcs = {
|
||
|
cs_gem_print,
|
||
|
};
|
||
|
|
||
|
+static int radeon_get_device_id(int fd, uint32_t *device_id)
|
||
|
+{
|
||
|
+ struct drm_radeon_info info;
|
||
|
+ int r;
|
||
|
+
|
||
|
+ *device_id = 0;
|
||
|
+ info.request = RADEON_INFO_DEVICE_ID;
|
||
|
+ info.value = device_id;
|
||
|
+ r = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info,
|
||
|
+ sizeof(struct drm_radeon_info));
|
||
|
+ return r;
|
||
|
+}
|
||
|
+
|
||
|
struct radeon_cs_manager *radeon_cs_manager_gem_ctor(int fd)
|
||
|
{
|
||
|
- struct radeon_cs_manager *csm;
|
||
|
+ struct radeon_cs_manager_gem *csm;
|
||
|
|
||
|
- csm = (struct radeon_cs_manager*)calloc(1,
|
||
|
- sizeof(struct radeon_cs_manager));
|
||
|
+ csm = calloc(1, sizeof(struct radeon_cs_manager_gem));
|
||
|
if (csm == NULL) {
|
||
|
return NULL;
|
||
|
}
|
||
|
- csm->funcs = &radeon_cs_gem_funcs;
|
||
|
- csm->fd = fd;
|
||
|
- return csm;
|
||
|
+ csm->base.funcs = &radeon_cs_gem_funcs;
|
||
|
+ csm->base.fd = fd;
|
||
|
+ radeon_get_device_id(fd, &csm->device_id);
|
||
|
+ return &csm->base;
|
||
|
}
|
||
|
|
||
|
void radeon_cs_manager_gem_dtor(struct radeon_cs_manager *csm)
|
||
|
diff --git a/radeon/radeon_cs_gem.h b/radeon/radeon_cs_gem.h
|
||
|
index 5efd146..5dea38a 100644
|
||
|
--- a/radeon/radeon_cs_gem.h
|
||
|
+++ b/radeon/radeon_cs_gem.h
|
||
|
@@ -1,8 +1,8 @@
|
||
|
-/*
|
||
|
+/*
|
||
|
* Copyright © 2008 Nicolai Haehnle
|
||
|
* Copyright © 2008 Jérôme Glisse
|
||
|
* All Rights Reserved.
|
||
|
- *
|
||
|
+ *
|
||
|
* Permission is hereby granted, free of charge, to any person obtaining
|
||
|
* a copy of this software and associated documentation files (the
|
||
|
* "Software"), to deal in the Software without restriction, including
|
||
|
@@ -10,14 +10,14 @@
|
||
|
* distribute, sub license, and/or sell copies of the Software, and to
|
||
|
* permit persons to whom the Software is furnished to do so, subject to
|
||
|
* the following conditions:
|
||
|
- *
|
||
|
+ *
|
||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||
|
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
|
||
|
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||
|
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
*
|
||
|
* The above copyright notice and this permission notice (including the
|
||
|
diff --git a/radeon/radeon_cs_space.c b/radeon/radeon_cs_space.c
|
||
|
index b8054e1..208e1bb 100644
|
||
|
--- a/radeon/radeon_cs_space.c
|
||
|
+++ b/radeon/radeon_cs_space.c
|
||
|
@@ -1,7 +1,7 @@
|
||
|
-/*
|
||
|
+/*
|
||
|
* Copyright © 2009 Red Hat Inc.
|
||
|
* All Rights Reserved.
|
||
|
- *
|
||
|
+ *
|
||
|
* Permission is hereby granted, free of charge, to any person obtaining
|
||
|
* a copy of this software and associated documentation files (the
|
||
|
* "Software"), to deal in the Software without restriction, including
|
||
|
@@ -9,14 +9,14 @@
|
||
|
* distribute, sub license, and/or sell copies of the Software, and to
|
||
|
* permit persons to whom the Software is furnished to do so, subject to
|
||
|
* the following conditions:
|
||
|
- *
|
||
|
+ *
|
||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||
|
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||
|
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
|
||
|
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||
|
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
*
|
||
|
* The above copyright notice and this permission notice (including the
|
||
|
@@ -50,54 +50,54 @@ static inline int radeon_cs_setup_bo(struct radeon_cs_space_check *sc, struct ra
|
||
|
|
||
|
/* legacy needs a static check */
|
||
|
if (radeon_bo_is_static((struct radeon_bo *)sc->bo)) {
|
||
|
- bo->space_accounted = sc->new_accounted = (read_domains << 16) | write_domain;
|
||
|
- return 0;
|
||
|
+ bo->space_accounted = sc->new_accounted = (read_domains << 16) | write_domain;
|
||
|
+ return 0;
|
||
|
}
|
||
|
|
||
|
/* already accounted this bo */
|
||
|
if (write_domain && (write_domain == bo->space_accounted)) {
|
||
|
- sc->new_accounted = bo->space_accounted;
|
||
|
- return 0;
|
||
|
+ sc->new_accounted = bo->space_accounted;
|
||
|
+ return 0;
|
||
|
}
|
||
|
if (read_domains && ((read_domains << 16) == bo->space_accounted)) {
|
||
|
- sc->new_accounted = bo->space_accounted;
|
||
|
- return 0;
|
||
|
+ sc->new_accounted = bo->space_accounted;
|
||
|
+ return 0;
|
||
|
}
|
||
|
|
||
|
if (bo->space_accounted == 0) {
|
||
|
- if (write_domain == RADEON_GEM_DOMAIN_VRAM)
|
||
|
- sizes->op_vram_write += bo->size;
|
||
|
- else if (write_domain == RADEON_GEM_DOMAIN_GTT)
|
||
|
- sizes->op_gart_write += bo->size;
|
||
|
- else
|
||
|
- sizes->op_read += bo->size;
|
||
|
- sc->new_accounted = (read_domains << 16) | write_domain;
|
||
|
+ if (write_domain == RADEON_GEM_DOMAIN_VRAM)
|
||
|
+ sizes->op_vram_write += bo->size;
|
||
|
+ else if (write_domain == RADEON_GEM_DOMAIN_GTT)
|
||
|
+ sizes->op_gart_write += bo->size;
|
||
|
+ else
|
||
|
+ sizes->op_read += bo->size;
|
||
|
+ sc->new_accounted = (read_domains << 16) | write_domain;
|
||
|
} else {
|
||
|
- uint16_t old_read, old_write;
|
||
|
-
|
||
|
- old_read = bo->space_accounted >> 16;
|
||
|
- old_write = bo->space_accounted & 0xffff;
|
||
|
-
|
||
|
- if (write_domain && (old_read & write_domain)) {
|
||
|
- sc->new_accounted = write_domain;
|
||
|
- /* moving from read to a write domain */
|
||
|
- if (write_domain == RADEON_GEM_DOMAIN_VRAM) {
|
||
|
- sizes->op_read -= bo->size;
|
||
|
- sizes->op_vram_write += bo->size;
|
||
|
- } else if (write_domain == RADEON_GEM_DOMAIN_GTT) {
|
||
|
- sizes->op_read -= bo->size;
|
||
|
- sizes->op_gart_write += bo->size;
|
||
|
- }
|
||
|
- } else if (read_domains & old_write) {
|
||
|
- sc->new_accounted = bo->space_accounted & 0xffff;
|
||
|
- } else {
|
||
|
- /* rewrite the domains */
|
||
|
- if (write_domain != old_write)
|
||
|
- fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write);
|
||
|
- if (read_domains != old_read)
|
||
|
- fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read);
|
||
|
- return RADEON_CS_SPACE_FLUSH;
|
||
|
- }
|
||
|
+ uint16_t old_read, old_write;
|
||
|
+
|
||
|
+ old_read = bo->space_accounted >> 16;
|
||
|
+ old_write = bo->space_accounted & 0xffff;
|
||
|
+
|
||
|
+ if (write_domain && (old_read & write_domain)) {
|
||
|
+ sc->new_accounted = write_domain;
|
||
|
+ /* moving from read to a write domain */
|
||
|
+ if (write_domain == RADEON_GEM_DOMAIN_VRAM) {
|
||
|
+ sizes->op_read -= bo->size;
|
||
|
+ sizes->op_vram_write += bo->size;
|
||
|
+ } else if (write_domain == RADEON_GEM_DOMAIN_GTT) {
|
||
|
+ sizes->op_read -= bo->size;
|
||
|
+ sizes->op_gart_write += bo->size;
|
||
|
+ }
|
||
|
+ } else if (read_domains & old_write) {
|
||
|
+ sc->new_accounted = bo->space_accounted & 0xffff;
|
||
|
+ } else {
|
||
|
+ /* rewrite the domains */
|
||
|
+ if (write_domain != old_write)
|
||
|
+ fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write);
|
||
|
+ if (read_domains != old_read)
|
||
|
+ fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read);
|
||
|
+ return RADEON_CS_SPACE_FLUSH;
|
||
|
+ }
|
||
|
}
|
||
|
return 0;
|
||
|
}
|
||
|
@@ -113,48 +113,48 @@ static int radeon_cs_do_space_check(struct radeon_cs_int *cs, struct radeon_cs_s
|
||
|
/* check the totals for this operation */
|
||
|
|
||
|
if (cs->bo_count == 0 && !new_tmp)
|
||
|
- return 0;
|
||
|
+ return 0;
|
||
|
|
||
|
memset(&sizes, 0, sizeof(struct rad_sizes));
|
||
|
|
||
|
/* prepare */
|
||
|
for (i = 0; i < cs->bo_count; i++) {
|
||
|
- ret = radeon_cs_setup_bo(&cs->bos[i], &sizes);
|
||
|
- if (ret)
|
||
|
- return ret;
|
||
|
+ ret = radeon_cs_setup_bo(&cs->bos[i], &sizes);
|
||
|
+ if (ret)
|
||
|
+ return ret;
|
||
|
}
|
||
|
|
||
|
if (new_tmp) {
|
||
|
- ret = radeon_cs_setup_bo(new_tmp, &sizes);
|
||
|
- if (ret)
|
||
|
- return ret;
|
||
|
+ ret = radeon_cs_setup_bo(new_tmp, &sizes);
|
||
|
+ if (ret)
|
||
|
+ return ret;
|
||
|
}
|
||
|
-
|
||
|
+
|
||
|
if (sizes.op_read < 0)
|
||
|
- sizes.op_read = 0;
|
||
|
+ sizes.op_read = 0;
|
||
|
|
||
|
/* check sizes - operation first */
|
||
|
if ((sizes.op_read + sizes.op_gart_write > csm->gart_limit) ||
|
||
|
- (sizes.op_vram_write > csm->vram_limit)) {
|
||
|
- return RADEON_CS_SPACE_OP_TO_BIG;
|
||
|
+ (sizes.op_vram_write > csm->vram_limit)) {
|
||
|
+ return RADEON_CS_SPACE_OP_TO_BIG;
|
||
|
}
|
||
|
-
|
||
|
+
|
||
|
if (((csm->vram_write_used + sizes.op_vram_write) > csm->vram_limit) ||
|
||
|
- ((csm->read_used + csm->gart_write_used + sizes.op_gart_write + sizes.op_read) > csm->gart_limit)) {
|
||
|
- return RADEON_CS_SPACE_FLUSH;
|
||
|
+ ((csm->read_used + csm->gart_write_used + sizes.op_gart_write + sizes.op_read) > csm->gart_limit)) {
|
||
|
+ return RADEON_CS_SPACE_FLUSH;
|
||
|
}
|
||
|
-
|
||
|
+
|
||
|
csm->gart_write_used += sizes.op_gart_write;
|
||
|
csm->vram_write_used += sizes.op_vram_write;
|
||
|
csm->read_used += sizes.op_read;
|
||
|
/* commit */
|
||
|
for (i = 0; i < cs->bo_count; i++) {
|
||
|
- bo = cs->bos[i].bo;
|
||
|
- bo->space_accounted = cs->bos[i].new_accounted;
|
||
|
+ bo = cs->bos[i].bo;
|
||
|
+ bo->space_accounted = cs->bos[i].new_accounted;
|
||
|
}
|
||
|
if (new_tmp)
|
||
|
- new_tmp->bo->space_accounted = new_tmp->new_accounted;
|
||
|
-
|
||
|
+ new_tmp->bo->space_accounted = new_tmp->new_accounted;
|
||
|
+
|
||
|
return RADEON_CS_SPACE_OK;
|
||
|
}
|
||
|
|
||
|
@@ -164,10 +164,10 @@ void radeon_cs_space_add_persistent_bo(struct radeon_cs *cs, struct radeon_bo *b
|
||
|
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
|
||
|
int i;
|
||
|
for (i = 0; i < csi->bo_count; i++) {
|
||
|
- if (csi->bos[i].bo == boi &&
|
||
|
- csi->bos[i].read_domains == read_domains &&
|
||
|
- csi->bos[i].write_domain == write_domain)
|
||
|
- return;
|
||
|
+ if (csi->bos[i].bo == boi &&
|
||
|
+ csi->bos[i].read_domains == read_domains &&
|
||
|
+ csi->bos[i].write_domain == write_domain)
|
||
|
+ return;
|
||
|
}
|
||
|
radeon_bo_ref(bo);
|
||
|
i = csi->bo_count;
|
||
|
@@ -181,7 +181,7 @@ void radeon_cs_space_add_persistent_bo(struct radeon_cs *cs, struct radeon_bo *b
|
||
|
}
|
||
|
|
||
|
static int radeon_cs_check_space_internal(struct radeon_cs_int *cs,
|
||
|
- struct radeon_cs_space_check *tmp_bo)
|
||
|
+ struct radeon_cs_space_check *tmp_bo)
|
||
|
{
|
||
|
int ret;
|
||
|
int flushed = 0;
|
||
|
@@ -189,32 +189,32 @@ static int radeon_cs_check_space_internal(struct radeon_cs_int *cs,
|
||
|
again:
|
||
|
ret = radeon_cs_do_space_check(cs, tmp_bo);
|
||
|
if (ret == RADEON_CS_SPACE_OP_TO_BIG)
|
||
|
- return -1;
|
||
|
+ return -1;
|
||
|
if (ret == RADEON_CS_SPACE_FLUSH) {
|
||
|
- (*cs->space_flush_fn)(cs->space_flush_data);
|
||
|
- if (flushed)
|
||
|
- return -1;
|
||
|
- flushed = 1;
|
||
|
- goto again;
|
||
|
+ (*cs->space_flush_fn)(cs->space_flush_data);
|
||
|
+ if (flushed)
|
||
|
+ return -1;
|
||
|
+ flushed = 1;
|
||
|
+ goto again;
|
||
|
}
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int radeon_cs_space_check_with_bo(struct radeon_cs *cs,
|
||
|
- struct radeon_bo *bo,
|
||
|
- uint32_t read_domains, uint32_t write_domain)
|
||
|
+ struct radeon_bo *bo,
|
||
|
+ uint32_t read_domains, uint32_t write_domain)
|
||
|
{
|
||
|
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
|
||
|
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
|
||
|
struct radeon_cs_space_check temp_bo;
|
||
|
-
|
||
|
+
|
||
|
int ret = 0;
|
||
|
|
||
|
if (bo) {
|
||
|
- temp_bo.bo = boi;
|
||
|
- temp_bo.read_domains = read_domains;
|
||
|
- temp_bo.write_domain = write_domain;
|
||
|
- temp_bo.new_accounted = 0;
|
||
|
+ temp_bo.bo = boi;
|
||
|
+ temp_bo.read_domains = read_domains;
|
||
|
+ temp_bo.write_domain = write_domain;
|
||
|
+ temp_bo.new_accounted = 0;
|
||
|
}
|
||
|
|
||
|
ret = radeon_cs_check_space_internal(csi, bo ? &temp_bo : NULL);
|
||
|
@@ -232,13 +232,11 @@ void radeon_cs_space_reset_bos(struct radeon_cs *cs)
|
||
|
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
|
||
|
int i;
|
||
|
for (i = 0; i < csi->bo_count; i++) {
|
||
|
- radeon_bo_unref((struct radeon_bo *)csi->bos[i].bo);
|
||
|
- csi->bos[i].bo = NULL;
|
||
|
- csi->bos[i].read_domains = 0;
|
||
|
- csi->bos[i].write_domain = 0;
|
||
|
- csi->bos[i].new_accounted = 0;
|
||
|
+ radeon_bo_unref((struct radeon_bo *)csi->bos[i].bo);
|
||
|
+ csi->bos[i].bo = NULL;
|
||
|
+ csi->bos[i].read_domains = 0;
|
||
|
+ csi->bos[i].write_domain = 0;
|
||
|
+ csi->bos[i].new_accounted = 0;
|
||
|
}
|
||
|
csi->bo_count = 0;
|
||
|
}
|
||
|
-
|
||
|
-
|
||
|
diff --git a/tests/Makefile.am b/tests/Makefile.am
|
||
|
index 4e4882a..3e74705 100644
|
||
|
--- a/tests/Makefile.am
|
||
|
+++ b/tests/Makefile.am
|
||
|
@@ -12,6 +12,10 @@ noinst_PROGRAMS = \
|
||
|
|
||
|
SUBDIRS =
|
||
|
|
||
|
+if HAVE_LIBKMS
|
||
|
+SUBDIRS += kmstest
|
||
|
+endif
|
||
|
+
|
||
|
if HAVE_INTEL
|
||
|
endif
|
||
|
|
||
|
diff --git a/tests/drmstat.c b/tests/drmstat.c
|
||
|
index ed2aeb6..345b8d2 100644
|
||
|
--- a/tests/drmstat.c
|
||
|
+++ b/tests/drmstat.c
|
||
|
@@ -28,6 +28,8 @@
|
||
|
*
|
||
|
*/
|
||
|
|
||
|
+#include "config.h"
|
||
|
+
|
||
|
#include <stdio.h>
|
||
|
#include <stdlib.h>
|
||
|
#include <unistd.h>
|
||
|
@@ -39,8 +41,16 @@
|
||
|
#include <errno.h>
|
||
|
#include <signal.h>
|
||
|
#include <fcntl.h>
|
||
|
+#ifdef HAVE_ALLOCA_H
|
||
|
+# include <alloca.h>
|
||
|
+#endif
|
||
|
#include "xf86drm.h"
|
||
|
|
||
|
+/* Support gcc's __FUNCTION__ for people using other compilers */
|
||
|
+#if !defined(__GNUC__) && !defined(__FUNCTION__)
|
||
|
+# define __FUNCTION__ __func__ /* C99 */
|
||
|
+#endif
|
||
|
+
|
||
|
int sigio_fd;
|
||
|
|
||
|
static double usec(struct timeval *end, struct timeval *start)
|
||
|
diff --git a/tests/kmstest/Makefile.am b/tests/kmstest/Makefile.am
|
||
|
new file mode 100644
|
||
|
index 0000000..ae562a1
|
||
|
--- /dev/null
|
||
|
+++ b/tests/kmstest/Makefile.am
|
||
|
@@ -0,0 +1,17 @@
|
||
|
+AM_CFLAGS = \
|
||
|
+ -I$(top_srcdir)/include/drm \
|
||
|
+ -I$(top_srcdir)/libkms/ \
|
||
|
+ -I$(top_srcdir)
|
||
|
+
|
||
|
+noinst_PROGRAMS = \
|
||
|
+ kmstest
|
||
|
+
|
||
|
+kmstest_SOURCES = \
|
||
|
+ main.c
|
||
|
+
|
||
|
+kmstest_LDADD = \
|
||
|
+ $(top_builddir)/libdrm.la \
|
||
|
+ $(top_builddir)/libkms/libkms.la
|
||
|
+
|
||
|
+run: kmstest
|
||
|
+ ./kmstest
|
||
|
diff --git a/tests/kmstest/main.c b/tests/kmstest/main.c
|
||
|
new file mode 100644
|
||
|
index 0000000..7aaeb75
|
||
|
--- /dev/null
|
||
|
+++ b/tests/kmstest/main.c
|
||
|
@@ -0,0 +1,90 @@
|
||
|
+/**************************************************************************
|
||
|
+ *
|
||
|
+ * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
|
||
|
+ * All Rights Reserved.
|
||
|
+ *
|
||
|
+ * Permission is hereby granted, free of charge, to any person obtaining a
|
||
|
+ * copy of this software and associated documentation files (the
|
||
|
+ * "Software"), to deal in the Software without restriction, including
|
||
|
+ * without limitation the rights to use, copy, modify, merge, publish,
|
||
|
+ * distribute, sub license, and/or sell copies of the Software, and to
|
||
|
+ * permit persons to whom the Software is furnished to do so, subject to
|
||
|
+ * the following conditions:
|
||
|
+ *
|
||
|
+ * The above copyright notice and this permission notice (including the
|
||
|
+ * next paragraph) shall be included in all copies or substantial portions
|
||
|
+ * of the Software.
|
||
|
+ *
|
||
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||
|
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||
|
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||
|
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||
|
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||
|
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||
|
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||
|
+ *
|
||
|
+ **************************************************************************/
|
||
|
+
|
||
|
+
|
||
|
+#include <stdio.h>
|
||
|
+#include <string.h>
|
||
|
+#include "xf86drm.h"
|
||
|
+#include "libkms.h"
|
||
|
+
|
||
|
+#define CHECK_RET_RETURN(ret, str) \
|
||
|
+ if (ret < 0) { \
|
||
|
+ printf("%s: %s (%s)\n", __func__, str, strerror(-ret)); \
|
||
|
+ return ret; \
|
||
|
+ }
|
||
|
+
|
||
|
+int test_bo(struct kms_driver *kms)
|
||
|
+{
|
||
|
+ struct kms_bo *bo;
|
||
|
+ int ret;
|
||
|
+ unsigned attrs[7] = {
|
||
|
+ KMS_WIDTH, 1024,
|
||
|
+ KMS_HEIGHT, 768,
|
||
|
+ KMS_BO_TYPE, KMS_BO_TYPE_SCANOUT_X8R8G8B8,
|
||
|
+ KMS_TERMINATE_PROP_LIST,
|
||
|
+ };
|
||
|
+
|
||
|
+ ret = kms_bo_create(kms, attrs, &bo);
|
||
|
+ CHECK_RET_RETURN(ret, "Could not create bo");
|
||
|
+
|
||
|
+ kms_bo_destroy(&bo);
|
||
|
+
|
||
|
+ return 0;
|
||
|
+}
|
||
|
+
|
||
|
+char *drivers[] = {
|
||
|
+ "i915",
|
||
|
+ "radeon",
|
||
|
+ "vmwgfx",
|
||
|
+ NULL
|
||
|
+};
|
||
|
+
|
||
|
+int main(int argc, char** argv)
|
||
|
+{
|
||
|
+ struct kms_driver *kms;
|
||
|
+ int ret, fd, i;
|
||
|
+
|
||
|
+ for (i = 0, fd = -1; fd < 0 && drivers[i]; i++)
|
||
|
+ fd = drmOpen(drivers[i], NULL);
|
||
|
+ CHECK_RET_RETURN(fd, "Could not open device");
|
||
|
+
|
||
|
+ ret = kms_create(fd, &kms);
|
||
|
+ CHECK_RET_RETURN(ret, "Failed to create kms driver");
|
||
|
+
|
||
|
+ ret = test_bo(kms);
|
||
|
+ if (ret)
|
||
|
+ goto err;
|
||
|
+
|
||
|
+ printf("%s: All ok!\n", __func__);
|
||
|
+
|
||
|
+ kms_destroy(&kms);
|
||
|
+ return 0;
|
||
|
+
|
||
|
+err:
|
||
|
+ kms_destroy(&kms);
|
||
|
+ return ret;
|
||
|
+}
|
||
|
diff --git a/xf86drmMode.c b/xf86drmMode.c
|
||
|
index ca36b71..f330e6f 100644
|
||
|
--- a/xf86drmMode.c
|
||
|
+++ b/xf86drmMode.c
|
||
|
@@ -136,35 +136,62 @@ void drmModeFreeEncoder(drmModeEncoderPtr ptr)
|
||
|
|
||
|
drmModeResPtr drmModeGetResources(int fd)
|
||
|
{
|
||
|
- struct drm_mode_card_res res;
|
||
|
+ struct drm_mode_card_res res, counts;
|
||
|
drmModeResPtr r = 0;
|
||
|
|
||
|
+retry:
|
||
|
memset(&res, 0, sizeof(struct drm_mode_card_res));
|
||
|
-
|
||
|
if (drmIoctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res))
|
||
|
return 0;
|
||
|
|
||
|
- if (res.count_fbs)
|
||
|
+ counts = res;
|
||
|
+
|
||
|
+ if (res.count_fbs) {
|
||
|
res.fb_id_ptr = VOID2U64(drmMalloc(res.count_fbs*sizeof(uint32_t)));
|
||
|
- if (res.count_crtcs)
|
||
|
+ if (!res.fb_id_ptr)
|
||
|
+ goto err_allocs;
|
||
|
+ }
|
||
|
+ if (res.count_crtcs) {
|
||
|
res.crtc_id_ptr = VOID2U64(drmMalloc(res.count_crtcs*sizeof(uint32_t)));
|
||
|
- if (res.count_connectors)
|
||
|
+ if (!res.crtc_id_ptr)
|
||
|
+ goto err_allocs;
|
||
|
+ }
|
||
|
+ if (res.count_connectors) {
|
||
|
res.connector_id_ptr = VOID2U64(drmMalloc(res.count_connectors*sizeof(uint32_t)));
|
||
|
- if (res.count_encoders)
|
||
|
+ if (!res.connector_id_ptr)
|
||
|
+ goto err_allocs;
|
||
|
+ }
|
||
|
+ if (res.count_encoders) {
|
||
|
res.encoder_id_ptr = VOID2U64(drmMalloc(res.count_encoders*sizeof(uint32_t)));
|
||
|
+ if (!res.encoder_id_ptr)
|
||
|
+ goto err_allocs;
|
||
|
+ }
|
||
|
|
||
|
- if (drmIoctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res)) {
|
||
|
- r = NULL;
|
||
|
+ if (drmIoctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res))
|
||
|
goto err_allocs;
|
||
|
+
|
||
|
+ /* The number of available connectors and etc may have changed with a
|
||
|
+ * hotplug event in between the ioctls, in which case the field is
|
||
|
+ * silently ignored by the kernel.
|
||
|
+ */
|
||
|
+ if (counts.count_fbs < res.count_fbs ||
|
||
|
+ counts.count_crtcs < res.count_crtcs ||
|
||
|
+ counts.count_connectors < res.count_connectors ||
|
||
|
+ counts.count_encoders < res.count_encoders)
|
||
|
+ {
|
||
|
+ drmFree(U642VOID(res.fb_id_ptr));
|
||
|
+ drmFree(U642VOID(res.crtc_id_ptr));
|
||
|
+ drmFree(U642VOID(res.connector_id_ptr));
|
||
|
+ drmFree(U642VOID(res.encoder_id_ptr));
|
||
|
+
|
||
|
+ goto retry;
|
||
|
}
|
||
|
|
||
|
/*
|
||
|
* return
|
||
|
*/
|
||
|
-
|
||
|
-
|
||
|
if (!(r = drmMalloc(sizeof(*r))))
|
||
|
- return 0;
|
||
|
+ goto err_allocs;
|
||
|
|
||
|
r->min_width = res.min_width;
|
||
|
r->max_width = res.max_width;
|
||
|
@@ -174,11 +201,23 @@ drmModeResPtr drmModeGetResources(int fd)
|
||
|
r->count_crtcs = res.count_crtcs;
|
||
|
r->count_connectors = res.count_connectors;
|
||
|
r->count_encoders = res.count_encoders;
|
||
|
- /* TODO we realy should test if these allocs fails. */
|
||
|
- r->fbs = drmAllocCpy(U642VOID(res.fb_id_ptr), res.count_fbs, sizeof(uint32_t));
|
||
|
- r->crtcs = drmAllocCpy(U642VOID(res.crtc_id_ptr), res.count_crtcs, sizeof(uint32_t));
|
||
|
- r->connectors = drmAllocCpy(U642VOID(res.connector_id_ptr), res.count_connectors, sizeof(uint32_t));
|
||
|
- r->encoders = drmAllocCpy(U642VOID(res.encoder_id_ptr), res.count_encoders, sizeof(uint32_t));
|
||
|
+
|
||
|
+ r->fbs = drmAllocCpy(U642VOID(res.fb_id_ptr), res.count_fbs, sizeof(uint32_t));
|
||
|
+ r->crtcs = drmAllocCpy(U642VOID(res.crtc_id_ptr), res.count_crtcs, sizeof(uint32_t));
|
||
|
+ r->connectors = drmAllocCpy(U642VOID(res.connector_id_ptr), res.count_connectors, sizeof(uint32_t));
|
||
|
+ r->encoders = drmAllocCpy(U642VOID(res.encoder_id_ptr), res.count_encoders, sizeof(uint32_t));
|
||
|
+ if ((res.count_fbs && !r->fbs) ||
|
||
|
+ (res.count_crtcs && !r->crtcs) ||
|
||
|
+ (res.count_connectors && !r->connectors) ||
|
||
|
+ (res.count_encoders && !r->encoders))
|
||
|
+ {
|
||
|
+ drmFree(r->fbs);
|
||
|
+ drmFree(r->crtcs);
|
||
|
+ drmFree(r->connectors);
|
||
|
+ drmFree(r->encoders);
|
||
|
+ drmFree(r);
|
||
|
+ r = 0;
|
||
|
+ }
|
||
|
|
||
|
err_allocs:
|
||
|
drmFree(U642VOID(res.fb_id_ptr));
|
||
|
@@ -371,37 +410,57 @@ drmModeEncoderPtr drmModeGetEncoder(int fd, uint32_t encoder_id)
|
||
|
|
||
|
drmModeConnectorPtr drmModeGetConnector(int fd, uint32_t connector_id)
|
||
|
{
|
||
|
- struct drm_mode_get_connector conn;
|
||
|
+ struct drm_mode_get_connector conn, counts;
|
||
|
drmModeConnectorPtr r = NULL;
|
||
|
|
||
|
+retry:
|
||
|
+ memset(&conn, 0, sizeof(struct drm_mode_get_connector));
|
||
|
conn.connector_id = connector_id;
|
||
|
- conn.connector_type_id = 0;
|
||
|
- conn.connector_type = 0;
|
||
|
- conn.count_modes = 0;
|
||
|
- conn.modes_ptr = 0;
|
||
|
- conn.count_props = 0;
|
||
|
- conn.props_ptr = 0;
|
||
|
- conn.prop_values_ptr = 0;
|
||
|
- conn.count_encoders = 0;
|
||
|
- conn.encoders_ptr = 0;
|
||
|
|
||
|
if (drmIoctl(fd, DRM_IOCTL_MODE_GETCONNECTOR, &conn))
|
||
|
return 0;
|
||
|
|
||
|
+ counts = conn;
|
||
|
+
|
||
|
if (conn.count_props) {
|
||
|
conn.props_ptr = VOID2U64(drmMalloc(conn.count_props*sizeof(uint32_t)));
|
||
|
+ if (!conn.props_ptr)
|
||
|
+ goto err_allocs;
|
||
|
conn.prop_values_ptr = VOID2U64(drmMalloc(conn.count_props*sizeof(uint64_t)));
|
||
|
+ if (!conn.prop_values_ptr)
|
||
|
+ goto err_allocs;
|
||
|
}
|
||
|
|
||
|
- if (conn.count_modes)
|
||
|
+ if (conn.count_modes) {
|
||
|
conn.modes_ptr = VOID2U64(drmMalloc(conn.count_modes*sizeof(struct drm_mode_modeinfo)));
|
||
|
+ if (!conn.modes_ptr)
|
||
|
+ goto err_allocs;
|
||
|
+ }
|
||
|
|
||
|
- if (conn.count_encoders)
|
||
|
+ if (conn.count_encoders) {
|
||
|
conn.encoders_ptr = VOID2U64(drmMalloc(conn.count_encoders*sizeof(uint32_t)));
|
||
|
+ if (!conn.encoders_ptr)
|
||
|
+ goto err_allocs;
|
||
|
+ }
|
||
|
|
||
|
if (drmIoctl(fd, DRM_IOCTL_MODE_GETCONNECTOR, &conn))
|
||
|
goto err_allocs;
|
||
|
|
||
|
+ /* The number of available connectors and etc may have changed with a
|
||
|
+ * hotplug event in between the ioctls, in which case the field is
|
||
|
+ * silently ignored by the kernel.
|
||
|
+ */
|
||
|
+ if (counts.count_props < conn.count_props ||
|
||
|
+ counts.count_modes < conn.count_modes ||
|
||
|
+ counts.count_encoders < conn.count_encoders) {
|
||
|
+ drmFree(U642VOID(conn.props_ptr));
|
||
|
+ drmFree(U642VOID(conn.prop_values_ptr));
|
||
|
+ drmFree(U642VOID(conn.modes_ptr));
|
||
|
+ drmFree(U642VOID(conn.encoders_ptr));
|
||
|
+
|
||
|
+ goto retry;
|
||
|
+ }
|
||
|
+
|
||
|
if(!(r = drmMalloc(sizeof(*r)))) {
|
||
|
goto err_allocs;
|
||
|
}
|
||
|
@@ -414,7 +473,6 @@ drmModeConnectorPtr drmModeGetConnector(int fd, uint32_t connector_id)
|
||
|
/* convert subpixel from kernel to userspace */
|
||
|
r->subpixel = conn.subpixel + 1;
|
||
|
r->count_modes = conn.count_modes;
|
||
|
- /* TODO we should test if these alloc & cpy fails. */
|
||
|
r->count_props = conn.count_props;
|
||
|
r->props = drmAllocCpy(U642VOID(conn.props_ptr), conn.count_props, sizeof(uint32_t));
|
||
|
r->prop_values = drmAllocCpy(U642VOID(conn.prop_values_ptr), conn.count_props, sizeof(uint64_t));
|
||
|
@@ -424,8 +482,17 @@ drmModeConnectorPtr drmModeGetConnector(int fd, uint32_t connector_id)
|
||
|
r->connector_type = conn.connector_type;
|
||
|
r->connector_type_id = conn.connector_type_id;
|
||
|
|
||
|
- if (!r->props || !r->prop_values || !r->modes || !r->encoders)
|
||
|
- goto err_allocs;
|
||
|
+ if ((r->count_props && !r->props) ||
|
||
|
+ (r->count_props && !r->prop_values) ||
|
||
|
+ (r->count_modes && !r->modes) ||
|
||
|
+ (r->count_encoders && !r->encoders)) {
|
||
|
+ drmFree(r->props);
|
||
|
+ drmFree(r->prop_values);
|
||
|
+ drmFree(r->modes);
|
||
|
+ drmFree(r->encoders);
|
||
|
+ drmFree(r);
|
||
|
+ r = 0;
|
||
|
+ }
|
||
|
|
||
|
err_allocs:
|
||
|
drmFree(U642VOID(conn.prop_values_ptr));
|