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libatomic_ops-7.4.6

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This commit is contained in:
Rex Dieter 2017-05-31 07:44:54 -05:00
parent 3eeefda8be
commit 90b4e28a97
5 changed files with 13 additions and 284 deletions
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1
.gitignore vendored
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@ -1,2 +1,3 @@
/libatomic_ops-7.4.2.tar.gz
/libatomic_ops-7.4.4.tar.gz
/libatomic_ops-7.4.6.tar.gz

142
0016-Use-LLD-and-SCD-instructions-on-mips64.patch
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@ -1,142 +0,0 @@
From 54d1da56809b892d2fc521fea0fd41ea8c23e4f2 Mon Sep 17 00:00:00 2001
From: James Cowgill <james410@cowgill.org.uk>
Date: Thu, 8 Jan 2015 16:00:38 +0000
Subject: [PATCH 16/59] Use LLD and SCD instructions on mips64
---
src/atomic_ops/sysdeps/gcc/mips.h | 54 ++++++++++++++++++++++-----------------
1 file changed, 30 insertions(+), 24 deletions(-)
diff --git a/src/atomic_ops/sysdeps/gcc/mips.h b/src/atomic_ops/sysdeps/gcc/mips.h
index a891de6..83a6bd3 100644
--- a/src/atomic_ops/sysdeps/gcc/mips.h
+++ b/src/atomic_ops/sysdeps/gcc/mips.h
@@ -15,7 +15,6 @@
* FIXME: This should probably make finer distinctions. SGI MIPS is
* much more strongly ordered, and in fact closer to sequentially
* consistent. This is really aimed at modern embedded implementations.
- * It looks to me like this assumes a 32-bit ABI. -HB
*/
#include "../all_aligned_atomic_load_store.h"
@@ -27,14 +26,24 @@
/* Data dependence does not imply read ordering. */
#define AO_NO_DD_ORDERING
+#ifdef __mips64
+# define AO_MIPS_SET_ISA " .set mips3\n"
+# define AO_MIPS_LL_1(args) " lld " args "\n"
+# define AO_MIPS_SC(args) " scd " args "\n"
+#else
+# define AO_MIPS_SET_ISA " .set mips2\n"
+# define AO_MIPS_LL_1(args) " ll " args "\n"
+# define AO_MIPS_SC(args) " sc " args "\n"
+# define AO_T_IS_INT
+#endif
+
#ifdef AO_ICE9A1_LLSC_WAR
/* ICE9 rev A1 chip (used in very few systems) is reported to */
/* have a low-frequency bug that causes LL to fail. */
/* To workaround, just issue the second 'LL'. */
-# define AO_MIPS_LL_FIX(args_str) \
- " ll " args_str "\n"
+# define AO_MIPS_LL(args) AO_MIPS_LL_1(args) AO_MIPS_LL_1(args)
#else
-# define AO_MIPS_LL_FIX(args_str) ""
+# define AO_MIPS_LL(args) AO_MIPS_LL_1(args)
#endif
AO_INLINE void
@@ -42,7 +51,7 @@ AO_nop_full(void)
{
__asm__ __volatile__(
" .set push \n"
- " .set mips2 \n"
+ AO_MIPS_SET_ISA
" .set noreorder \n"
" .set nomacro \n"
" sync \n"
@@ -60,13 +69,13 @@ AO_fetch_and_add(volatile AO_t *addr, AO_t incr)
__asm__ __volatile__(
" .set push\n"
- " .set mips2\n"
+ AO_MIPS_SET_ISA
" .set noreorder\n"
" .set nomacro\n"
- "1: ll %0, %2\n"
- AO_MIPS_LL_FIX("%0, %2")
+ "1: "
+ AO_MIPS_LL("%0, %2")
" addu %1, %0, %3\n"
- " sc %1, %2\n"
+ AO_MIPS_SC("%1, %2")
" beqz %1, 1b\n"
" nop\n"
" .set pop "
@@ -85,13 +94,13 @@ AO_test_and_set(volatile AO_TS_t *addr)
__asm__ __volatile__(
" .set push\n"
- " .set mips2\n"
+ AO_MIPS_SET_ISA
" .set noreorder\n"
" .set nomacro\n"
- "1: ll %0, %2\n"
- AO_MIPS_LL_FIX("%0, %2")
+ "1: "
+ AO_MIPS_LL("%0, %2")
" move %1, %3\n"
- " sc %1, %2\n"
+ AO_MIPS_SC("%1, %2")
" beqz %1, 1b\n"
" nop\n"
" .set pop "
@@ -114,14 +123,14 @@ AO_test_and_set(volatile AO_TS_t *addr)
__asm__ __volatile__(
" .set push \n"
- " .set mips2 \n"
+ AO_MIPS_SET_ISA
" .set noreorder \n"
" .set nomacro \n"
- "1: ll %0, %1 \n"
- AO_MIPS_LL_FIX("%0, %1")
+ "1: "
+ AO_MIPS_LL("%0, %1")
" bne %0, %4, 2f \n"
" move %0, %3 \n"
- " sc %0, %1 \n"
+ AO_MIPS_SC("%0, %1")
" .set pop \n"
" beqz %0, 1b \n"
" li %2, 1 \n"
@@ -142,14 +151,14 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
__asm__ __volatile__(
" .set push\n"
- " .set mips2\n"
+ AO_MIPS_SET_ISA
" .set noreorder\n"
" .set nomacro\n"
- "1: ll %0, %2\n"
- AO_MIPS_LL_FIX("%0, %2")
+ "1: "
+ AO_MIPS_LL("%0, %2")
" bne %0, %4, 2f\n"
" move %1, %3\n"
- " sc %1, %2\n"
+ AO_MIPS_SC("%1, %2")
" beqz %1, 1b\n"
" nop\n"
" .set pop\n"
@@ -167,6 +176,3 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
/* CAS primitives with acquire, release and full semantics are */
/* generated automatically (and AO_int_... primitives are */
/* defined properly after the first generalization pass). */
-
-/* FIXME: 32-bit ABI is assumed. */
-#define AO_T_IS_INT
--
2.7.4

129
libatomic_ops-7.4.4-Use-LLD-and-SCD-instructions-on-mips64.patch
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@ -1,129 +0,0 @@
diff -up libatomic_ops-7.4.4/src/atomic_ops/sysdeps/gcc/mips.h.0016 libatomic_ops-7.4.4/src/atomic_ops/sysdeps/gcc/mips.h
--- libatomic_ops-7.4.4/src/atomic_ops/sysdeps/gcc/mips.h.0016 2016-05-24 15:01:55.000000000 -0500
+++ libatomic_ops-7.4.4/src/atomic_ops/sysdeps/gcc/mips.h 2016-06-17 10:25:42.139250860 -0500
@@ -15,7 +15,6 @@
* FIXME: This should probably make finer distinctions. SGI MIPS is
* much more strongly ordered, and in fact closer to sequentially
* consistent. This is really aimed at modern embedded implementations.
- * It looks to me like this assumes a 32-bit ABI. -HB
*/
#include "../all_aligned_atomic_load_store.h"
@@ -25,14 +24,24 @@
/* Data dependence does not imply read ordering. */
#define AO_NO_DD_ORDERING
+#ifdef __mips64
+# define AO_MIPS_SET_ISA " .set mips3\n"
+# define AO_MIPS_LL_1(args) " lld " args "\n"
+# define AO_MIPS_SC(args) " scd " args "\n"
+#else
+# define AO_MIPS_SET_ISA " .set mips2\n"
+# define AO_MIPS_LL_1(args) " ll " args "\n"
+# define AO_MIPS_SC(args) " sc " args "\n"
+# define AO_T_IS_INT
+#endif
+
#ifdef AO_ICE9A1_LLSC_WAR
/* ICE9 rev A1 chip (used in very few systems) is reported to */
/* have a low-frequency bug that causes LL to fail. */
/* To workaround, just issue the second 'LL'. */
-# define AO_MIPS_LL_FIX(args_str) \
- " ll " args_str "\n"
+# define AO_MIPS_LL(args) AO_MIPS_LL_1(args) AO_MIPS_LL_1(args)
#else
-# define AO_MIPS_LL_FIX(args_str) ""
+# define AO_MIPS_LL(args) AO_MIPS_LL_1(args)
#endif
AO_INLINE void
@@ -40,7 +49,7 @@ AO_nop_full(void)
{
__asm__ __volatile__(
" .set push \n"
- " .set mips2 \n"
+ AO_MIPS_SET_ISA
" .set noreorder \n"
" .set nomacro \n"
" sync \n"
@@ -58,13 +67,13 @@ AO_fetch_and_add(volatile AO_t *addr, AO
__asm__ __volatile__(
" .set push\n"
- " .set mips2\n"
+ AO_MIPS_SET_ISA
" .set noreorder\n"
" .set nomacro\n"
- "1: ll %0, %2\n"
- AO_MIPS_LL_FIX("%0, %2")
+ "1: "
+ AO_MIPS_LL("%0, %2")
" addu %1, %0, %3\n"
- " sc %1, %2\n"
+ AO_MIPS_SC("%1, %2")
" beqz %1, 1b\n"
" nop\n"
" .set pop "
@@ -83,13 +92,13 @@ AO_test_and_set(volatile AO_TS_t *addr)
__asm__ __volatile__(
" .set push\n"
- " .set mips2\n"
+ AO_MIPS_SET_ISA
" .set noreorder\n"
" .set nomacro\n"
- "1: ll %0, %2\n"
- AO_MIPS_LL_FIX("%0, %2")
+ "1: "
+ AO_MIPS_LL("%0, %2")
" move %1, %3\n"
- " sc %1, %2\n"
+ AO_MIPS_SC("%1, %2")
" beqz %1, 1b\n"
" nop\n"
" .set pop "
@@ -112,14 +121,14 @@ AO_test_and_set(volatile AO_TS_t *addr)
__asm__ __volatile__(
" .set push \n"
- " .set mips2 \n"
+ AO_MIPS_SET_ISA
" .set noreorder \n"
" .set nomacro \n"
- "1: ll %0, %1 \n"
- AO_MIPS_LL_FIX("%0, %1")
+ "1: "
+ AO_MIPS_LL("%0, %1")
" bne %0, %4, 2f \n"
" move %0, %3 \n"
- " sc %0, %1 \n"
+ AO_MIPS_SC("%0, %1")
" .set pop \n"
" beqz %0, 1b \n"
" li %2, 1 \n"
@@ -140,14 +149,14 @@ AO_fetch_compare_and_swap(volatile AO_t
__asm__ __volatile__(
" .set push\n"
- " .set mips2\n"
+ AO_MIPS_SET_ISA
" .set noreorder\n"
" .set nomacro\n"
- "1: ll %0, %2\n"
- AO_MIPS_LL_FIX("%0, %2")
+ "1: "
+ AO_MIPS_LL("%0, %2")
" bne %0, %4, 2f\n"
" move %1, %3\n"
- " sc %1, %2\n"
+ AO_MIPS_SC("%1, %2")
" beqz %1, 1b\n"
" nop\n"
" .set pop\n"
@@ -165,6 +174,3 @@ AO_fetch_compare_and_swap(volatile AO_t
/* CAS primitives with acquire, release and full semantics are */
/* generated automatically (and AO_int_... primitives are */
/* defined properly after the first generalization pass). */
-
-/* FIXME: 32-bit ABI is assumed. */
-#define AO_T_IS_INT

23
libatomic_ops.spec
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@ -1,14 +1,13 @@
Name: libatomic_ops
Summary: Atomic memory update operations
Version: 7.4.4
Release: 2%{?dist}
Version: 7.4.6
Release: 1%{?dist}
# libatomic_ops MIT, libatomic_ops_gpl GPLv2
License: GPLv2 and MIT
URL: http://www.hboehm.info/gc/
#URL: https://github.com/ivmai/libatomic_ops/
#Source0: http://www.ivmaisoft.com/_bin/atomic_ops/libatomic_ops-%{version}.tar.gz
Source0: http://www.hboehm.info/gc/gc_source/libatomic_ops-%{version}.tar.gz
#URL: http://www.hboehm.info/gc/
URL: https://github.com/ivmai/libatomic_ops/
Source0: https://github.com/ivmai/libatomic_ops/releases/download/v%{version}/libatomic_ops-%{version}.tar.gz
# updated GPLv2 license text
Source1: http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
@ -16,9 +15,6 @@ Source1: http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
# 7.4 branch
# master branch
#Patch116: 0016-Use-LLD-and-SCD-instructions-on-mips64.patch
## rebased for 7.4.4
Patch116: libatomic_ops-7.4.4-Use-LLD-and-SCD-instructions-on-mips64.patch
## upstreamable patches
# https://bugzilla.redhat.com/show_bug.cgi?id=1096574
@ -50,7 +46,7 @@ Files for developing with %{name} and linking statically.
%prep
%autosetup -p1
# patch50 introduces rpath (probably due to older libtool), refresh stuff here
# refresh stuff here to be rid of rpath
autoreconf -fi
install -m644 -p %{SOURCE1} ./COPYING
@ -70,7 +66,7 @@ make install DESTDIR=%{buildroot}
## unpackaged files
rm -fv %{buildroot}%{_libdir}/lib*.la
# omit dup'd docs
rm -fv %{buildroot}%{_datadir}/libatomic_ops/{COPYING,README*,*.txt}
rm -fv %{buildroot}%{_docdir}/libatomic_ops/{COPYING,README*,*.txt}
%check
@ -85,7 +81,7 @@ make check %{?arch_ignore}
%files
%license COPYING
%doc doc/LICENSING.txt
%license doc/LICENSING.txt
%doc AUTHORS ChangeLog README.md
%{_libdir}/libatomic_ops.so.1*
%{_libdir}/libatomic_ops_gpl.so.1*
@ -106,6 +102,9 @@ make check %{?arch_ignore}
%changelog
* Wed May 31 2017 Rex Dieter <rdieter@fedoraproject.org> - 7.4.6-1
- libatomic_ops-7.4.6
* Fri Feb 10 2017 Fedora Release Engineering <releng@fedoraproject.org> - 7.4.4-2
- Rebuilt for https://fedoraproject.org/wiki/Fedora_26_Mass_Rebuild

2
sources
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@ -1 +1 @@
426d804baae12c372967a6d183e25af2 libatomic_ops-7.4.4.tar.gz
SHA512 (libatomic_ops-7.4.6.tar.gz) = 29c6f937aa5d21343741aa0661aaf33ec9196b7784b7165d40dd87ce7bf8a7691f5ba94040663f078465ded1935ca01bb829a4b56b190f9db63cc141515d9819