73 lines
2.8 KiB
Diff
73 lines
2.8 KiB
Diff
From 58553ad03187f0cf208d6c4a0dc026c6338e5edd Mon Sep 17 00:00:00 2001
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From: "Daisuke Hatayama (Fujitsu)" <d.hatayama@fujitsu.com>
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Date: Wed, 29 Mar 2023 12:44:10 +0000
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Subject: [PATCH 5/7] [PATCH] sadump: fix failure of reading memory when
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5-level paging is enabled
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makedumpfile fails as follows for memory dumps collected by sadump
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when 5-level paging is enabled on the corresponding systems:
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# makedumpfile -l -d 31 -x ./vmlinux ./dump.sadump dump.sadump-ld31
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__vtop4_x86_64: Can't get a valid pgd.
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...snip...
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__vtop4_x86_64: Can't get a valid pgd.
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calc_kaslr_offset: failed to calculate kaslr_offset and phys_base; default to 0
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__vtop4_x86_64: Can't get a valid pgd.
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readmem: Can't convert a virtual address(ffffffff82fce960) to physical address.
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readmem: type_addr: 0, addr:ffffffff82fce960, size:1024
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cpu_online_mask_init: Can't read cpu_online_mask memory.
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makedumpfile Failed.
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This is because 5-level paging support has not been done yet for
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sadump; the work of the 5-level paging support was done by the commit
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30a3214a7193e94c551c0cebda5918a72a35c589 (PATCH 4/4 arch/x86_64: Add
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5-level paging support) but that was focused on the core part only.
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Having said that, most of things has already been finished in the
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commit. What needs to be newly added for sadump is just how to check
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if 5-level paging is enabled for a given memory dump.
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For that purpose, let's refer to CR4.LA57, bit 12 of CR4, representing
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whether 5-level paging is enabled or not. We can do this because
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memory dumps collected by sadump have SMRAM as note information and
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they include CR4 together with the other control registers.
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Signed-off-by: HATAYAMA Daisuke <d.hatayama@fujitsu.com>
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---
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sadump_info.c | 4 ++++
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1 file changed, 4 insertions(+)
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diff --git a/makedumpfile-1.7.2/sadump_info.c b/makedumpfile-1.7.2/sadump_info.c
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index adfa8dc..2c44068 100644
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--- a/makedumpfile-1.7.2/sadump_info.c
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+++ b/makedumpfile-1.7.2/sadump_info.c
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@@ -1362,6 +1362,7 @@ static int linux_banner_sanity_check(ulong cr3)
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#define PTI_USER_PGTABLE_BIT (info->page_shift)
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#define PTI_USER_PGTABLE_MASK (1 << PTI_USER_PGTABLE_BIT)
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#define CR3_PCID_MASK 0xFFFull
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+#define CR4_LA57 (1 << 12)
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int
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calc_kaslr_offset(void)
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{
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@@ -1397,6 +1398,8 @@ calc_kaslr_offset(void)
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else
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cr3 = smram.Cr3 & ~CR3_PCID_MASK;
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+ NUMBER(pgtable_l5_enabled) = !!(smram.Cr4 & CR4_LA57);
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+
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/* Convert virtual address of IDT table to physical address */
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idtr_paddr = vtop4_x86_64_pagetable(idtr, cr3);
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if (idtr_paddr == NOT_PADDR) {
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@@ -1417,6 +1420,7 @@ calc_kaslr_offset(void)
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DEBUG_MSG("sadump: idtr=%" PRIx64 "\n", idtr);
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DEBUG_MSG("sadump: cr3=%" PRIx64 "\n", cr3);
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+ DEBUG_MSG("sadump: cr4=%" PRIx32 "\n", smram.Cr4);
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DEBUG_MSG("sadump: idtr(phys)=%" PRIx64 "\n", idtr_paddr);
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DEBUG_MSG("sadump: devide_error(vmlinux)=%lx\n",
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divide_error_vmlinux);
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--
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2.33.1
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