87 lines
3.2 KiB
Diff
87 lines
3.2 KiB
Diff
From 373fedf7ca5674e2ab511685e183e6e6c6e00d91 Mon Sep 17 00:00:00 2001
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From: "Borislav Petkov (AMD)" <bp@alien8.de>
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Date: Sat, 25 Feb 2023 01:11:31 +0100
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Subject: [PATCH 34/36] x86/CPU/AMD: Make sure EFER[AIBRSE] is set
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The AutoIBRS bit gets set only on the BSP as part of determining which
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mitigation to enable on AMD. Setting on the APs relies on the
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circumstance that the APs get booted through the trampoline and EFER
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- the MSR which contains that bit - gets replicated on every AP from the
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BSP.
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However, this can change in the future and considering the security
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implications of this bit not being set on every CPU, make sure it is set
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by verifying EFER later in the boot process and on every AP.
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Reported-by: Josh Poimboeuf <jpoimboe@kernel.org>
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Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
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Acked-by: Dave Hansen <dave.hansen@linux.intel.com>
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Link: https://lore.kernel.org/r/20230224185257.o3mcmloei5zqu7wa@treble
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(cherry picked from commit 8cc68c9c9e92dbaae51a711454c66eb668045508)
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CVE: CVE-2023-20593
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Signed-off-by: Mridula Shastry <mridula.c.shastry@oracle.com>
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Reviewed-by: Todd Vierling <todd.vierling@oracle.com>
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---
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arch/x86/kernel/cpu/amd.c | 11 +++++++++++
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arch/x86/kernel/cpu/bugs.c | 3 +--
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arch/x86/kernel/cpu/cpu.h | 8 ++++++++
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3 files changed, 20 insertions(+), 2 deletions(-)
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diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
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index 2406a71a1eb6..c2979e3bed04 100644
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--- a/arch/x86/kernel/cpu/amd.c
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+++ b/arch/x86/kernel/cpu/amd.c
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@@ -1046,6 +1046,17 @@ static void init_amd(struct cpuinfo_x86 *c)
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msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
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check_null_seg_clears_base(c);
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+
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+ /*
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+ * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up
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+ * using the trampoline code and as part of it, MSR_EFER gets prepared there in
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+ * order to be replicated onto them. Regardless, set it here again, if not set,
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+ * to protect against any future refactoring/code reorganization which might
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+ * miss setting this important bit.
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+ */
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+ if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
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+ cpu_has(c, X86_FEATURE_AUTOIBRS))
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+ WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
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}
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#ifdef CONFIG_X86_32
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diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
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index 43295a878b8f..d8c1bbea4e90 100644
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--- a/arch/x86/kernel/cpu/bugs.c
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+++ b/arch/x86/kernel/cpu/bugs.c
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@@ -748,8 +748,7 @@ static int __init nospectre_v1_cmdline(char *str)
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}
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early_param("nospectre_v1", nospectre_v1_cmdline);
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-static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
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- SPECTRE_V2_NONE;
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+enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = SPECTRE_V2_NONE;
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#undef pr_fmt
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#define pr_fmt(fmt) "RETBleed: " fmt
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diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
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index 1add3618f766..0af870727bfa 100644
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--- a/arch/x86/kernel/cpu/cpu.h
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+++ b/arch/x86/kernel/cpu/cpu.h
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@@ -88,4 +88,12 @@ extern void update_srbds_msr(void);
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void init_ia32_feat_ctl(struct cpuinfo_x86 *c);
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#endif
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+extern enum spectre_v2_mitigation spectre_v2_enabled;
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+
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+static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
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+{
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+ return mode == SPECTRE_V2_EIBRS ||
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+ mode == SPECTRE_V2_EIBRS_RETPOLINE ||
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+ mode == SPECTRE_V2_EIBRS_LFENCE;
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+}
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#endif /* ARCH_X86_CPU_H */
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--
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2.39.3
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