149 lines
5.4 KiB
Diff
149 lines
5.4 KiB
Diff
From 97e9891f4f6253ec70fc870e639d7e4d07b9e361 Mon Sep 17 00:00:00 2001
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From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
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Date: Wed, 30 Nov 2022 07:25:51 -0800
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Subject: [PATCH 32/36] x86/bugs: Make sure MSR_SPEC_CTRL is updated properly
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upon resume from S3
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The "force" argument to write_spec_ctrl_current() is currently ambiguous
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as it does not guarantee the MSR write. This is due to the optimization
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that writes to the MSR happen only when the new value differs from the
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cached value.
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This is fine in most cases, but breaks for S3 resume when the cached MSR
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value gets out of sync with the hardware MSR value due to S3 resetting
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it.
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When x86_spec_ctrl_current is same as x86_spec_ctrl_base, the MSR write
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is skipped. Which results in SPEC_CTRL mitigations not getting restored.
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Move the MSR write from write_spec_ctrl_current() to a new function that
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unconditionally writes to the MSR. Update the callers accordingly and
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rename functions.
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[ bp: Rework a bit. ]
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Fixes: caa0ff24d5d0 ("x86/bugs: Keep a per-CPU IA32_SPEC_CTRL value")
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Suggested-by: Borislav Petkov <bp@alien8.de>
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Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
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Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
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Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: <stable@kernel.org>
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Link: https://lore.kernel.org/r/806d39b0bfec2fe8f50dc5446dff20f5bb24a959.1669821572.git.pawan.kumar.gupta@linux.intel.com
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Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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(cherry picked from commit 66065157420c5b9b3f078f43d313c153e1ff7f83)
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Signed-off-by: Mridula Shastry <mridula.c.shastry@oracle.com>
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Reviewed-by: Todd Vierling <todd.vierling@oracle.com>
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---
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arch/x86/include/asm/nospec-branch.h | 2 +-
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arch/x86/kernel/cpu/bugs.c | 21 ++++++++++++++-------
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arch/x86/kernel/process.c | 2 +-
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3 files changed, 16 insertions(+), 9 deletions(-)
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diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h
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index 442e62e7be47..53e56fc9cf70 100644
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--- a/arch/x86/include/asm/nospec-branch.h
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+++ b/arch/x86/include/asm/nospec-branch.h
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@@ -318,7 +318,7 @@ static inline void indirect_branch_prediction_barrier(void)
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/* The Intel SPEC CTRL MSR base value cache */
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extern u64 x86_spec_ctrl_base;
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DECLARE_PER_CPU(u64, x86_spec_ctrl_current);
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-extern void write_spec_ctrl_current(u64 val, bool force);
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+extern void update_spec_ctrl_cond(u64 val);
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extern u64 spec_ctrl_current(void);
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/*
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diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
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index 5dc79427d047..53623ea69873 100644
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--- a/arch/x86/kernel/cpu/bugs.c
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+++ b/arch/x86/kernel/cpu/bugs.c
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@@ -60,11 +60,18 @@ EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
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static DEFINE_MUTEX(spec_ctrl_mutex);
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+/* Update SPEC_CTRL MSR and its cached copy unconditionally */
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+static void update_spec_ctrl(u64 val)
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+{
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+ this_cpu_write(x86_spec_ctrl_current, val);
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+ wrmsrl(MSR_IA32_SPEC_CTRL, val);
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+}
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+
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/*
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* Keep track of the SPEC_CTRL MSR value for the current task, which may differ
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* from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
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*/
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-void write_spec_ctrl_current(u64 val, bool force)
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+void update_spec_ctrl_cond(u64 val)
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{
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if (this_cpu_read(x86_spec_ctrl_current) == val)
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return;
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@@ -76,7 +83,7 @@ void write_spec_ctrl_current(u64 val, bool force)
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* forced or the exit MSR write is skipped the update can be delayed
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* until that time.
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*/
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- if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS) ||
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+ if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS) ||
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cpu_feature_enabled(X86_FEATURE_IBRS_EXIT_SKIP))
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wrmsrl(MSR_IA32_SPEC_CTRL, val);
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}
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@@ -1308,7 +1315,7 @@ static void __init spec_ctrl_disable_kernel_rrsba(void)
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if (ia32_cap & ARCH_CAP_RRSBA) {
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x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
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- write_spec_ctrl_current(x86_spec_ctrl_base, true);
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+ update_spec_ctrl(x86_spec_ctrl_base);
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}
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}
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@@ -1440,7 +1447,7 @@ static void __init spectre_v2_select_mitigation(void)
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if (spectre_v2_in_ibrs_mode(mode)) {
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x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
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- write_spec_ctrl_current(x86_spec_ctrl_base, true);
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+ update_spec_ctrl(x86_spec_ctrl_base);
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}
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switch (mode) {
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@@ -1565,7 +1572,7 @@ static void __init spectre_v2_select_mitigation(void)
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static void update_stibp_msr(void * __unused)
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{
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u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
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- write_spec_ctrl_current(val, true);
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+ update_spec_ctrl(val);
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}
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/* Update x86_spec_ctrl_base in case SMT state changed. */
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@@ -1798,7 +1805,7 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
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x86_amd_ssb_disable();
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} else {
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x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
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- write_spec_ctrl_current(x86_spec_ctrl_base, true);
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+ update_spec_ctrl(x86_spec_ctrl_base);
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}
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}
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@@ -2016,7 +2023,7 @@ int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
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void x86_spec_ctrl_setup_ap(void)
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{
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if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
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- write_spec_ctrl_current(x86_spec_ctrl_base, true);
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+ update_spec_ctrl(x86_spec_ctrl_base);
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if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
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x86_amd_ssb_disable();
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diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
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index 87bcb25ff8b2..a62f200aa736 100644
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--- a/arch/x86/kernel/process.c
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+++ b/arch/x86/kernel/process.c
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@@ -583,7 +583,7 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp,
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}
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if (updmsr)
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- write_spec_ctrl_current(msr, false);
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+ update_spec_ctrl_cond(msr);
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}
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static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
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--
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2.39.3
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