94 lines
2.6 KiB
Diff
94 lines
2.6 KiB
Diff
From ef8a26638432066d8e683b216142d695fd16d222 Mon Sep 17 00:00:00 2001
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From: Daiki Ueno <ueno@gnu.org>
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Date: Mon, 15 Aug 2022 09:39:18 +0900
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Subject: [PATCH] accelerated: clear AVX bits if it cannot be queried through
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XSAVE
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The algorithm to detect AVX is described in 14.3 of "Intel® 64 and IA-32
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Architectures Software Developer’s Manual".
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GnuTLS previously only followed that algorithm when registering the
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crypto backend, while the CRYPTOGAMS derived SHA code assembly expects
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that the extension bits are propagated to _gnutls_x86_cpuid_s.
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Signed-off-by: Daiki Ueno <ueno@gnu.org>
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---
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lib/accelerated/x86/x86-common.c | 37 +++++++++++++++++++++++++++-----
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1 file changed, 32 insertions(+), 5 deletions(-)
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diff --git a/lib/accelerated/x86/x86-common.c b/lib/accelerated/x86/x86-common.c
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index 7ddaa594e6..85e2f93d4d 100644
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--- a/lib/accelerated/x86/x86-common.c
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+++ b/lib/accelerated/x86/x86-common.c
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@@ -81,6 +81,26 @@ unsigned int _gnutls_x86_cpuid_s[4];
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# define bit_AVX 0x10000000
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#endif
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+#ifndef bit_AVX2
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+# define bit_AVX2 0x00000020
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+#endif
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+
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+#ifndef bit_AVX512F
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+# define bit_AVX512F 0x00010000
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+#endif
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+
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+#ifndef bit_AVX512IFMA
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+# define bit_AVX512IFMA 0x00200000
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+#endif
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+
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+#ifndef bit_AVX512BW
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+# define bit_AVX512BW 0x40000000
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+#endif
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+
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+#ifndef bit_AVX512VL
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+# define bit_AVX512VL 0x80000000
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+#endif
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+
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#ifndef bit_OSXSAVE
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# define bit_OSXSAVE 0x8000000
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#endif
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@@ -148,7 +168,7 @@ static unsigned check_4th_gen_intel_features(unsigned ecx)
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{
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uint32_t xcr0;
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- if ((ecx & OSXSAVE_MASK) != OSXSAVE_MASK)
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+ if ((ecx & bit_OSXSAVE) != bit_OSXSAVE)
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return 0;
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#if defined(_MSC_VER) && !defined(__clang__)
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@@ -236,10 +256,7 @@ static unsigned check_sha(void)
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#ifdef ASM_X86_64
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static unsigned check_avx_movbe(void)
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{
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- if (check_4th_gen_intel_features(_gnutls_x86_cpuid_s[1]) == 0)
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- return 0;
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-
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- return ((_gnutls_x86_cpuid_s[1] & bit_AVX));
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+ return (_gnutls_x86_cpuid_s[1] & (bit_AVX|bit_MOVBE)) == (bit_AVX|bit_MOVBE);
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}
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static unsigned check_pclmul(void)
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@@ -895,6 +912,16 @@ void register_x86_intel_crypto(unsigned capabilities)
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_gnutls_x86_cpuid_s[0] &= ~(1 << 30);
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}
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+ if (!check_4th_gen_intel_features(_gnutls_x86_cpuid_s[1])) {
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+ _gnutls_x86_cpuid_s[1] &= ~bit_AVX;
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+
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+ /* Clear AVX2 bits as well, according to what OpenSSL does.
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+ * Should we clear bit_AVX512DQ, bit_AVX512PF, bit_AVX512ER, and
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+ * bit_AVX512CD? */
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+ _gnutls_x86_cpuid_s[2] &= ~(bit_AVX2|bit_AVX512F|bit_AVX512IFMA|
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+ bit_AVX512BW|bit_AVX512BW);
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+ }
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+
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if (check_ssse3()) {
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_gnutls_debug_log("Intel SSSE3 was detected\n");
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--
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2.37.2
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