1bea1361dc
Upstream commit: 31da30f23cddd36db29d5b6a1c7619361b271fb4 - iconv: ISO-2022-CN-EXT: fix out-of-bound writes when writing escape sequence (CVE-2024-2961) - x86_64: Exclude SSE, AVX and FMA4 variants in libm multiarch - Apply the Makefile sorting fix - powerpc: Fix ld.so address determination for PCREL mode (bug 31640) - x86-64: Simplify minimum ISA check ifdef conditional with if - x86-64: Don't use SSE resolvers for ISA level 3 or above - AArch64: Check kernel version for SVE ifuncs - aarch64: fix check for SVE support in assembler - aarch64/fpu: Sync libmvec routines from 2.39 and before with AOR - i386: Use generic memrchr in libc (bug 31316)
109 lines
3.2 KiB
Diff
109 lines
3.2 KiB
Diff
commit 9883f4304cfb1558d0f1e6d9f48c4ab0a35355fe
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Author: H.J. Lu <hjl.tools@gmail.com>
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Date: Wed Feb 28 09:51:14 2024 -0800
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x86-64: Don't use SSE resolvers for ISA level 3 or above
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When glibc is built with ISA level 3 or above enabled, SSE resolvers
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aren't available and glibc fails to build:
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ld: .../elf/librtld.os: in function `init_cpu_features':
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.../elf/../sysdeps/x86/cpu-features.c:1200:(.text+0x1445f): undefined reference to `_dl_runtime_resolve_fxsave'
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ld: .../elf/librtld.os: relocation R_X86_64_PC32 against undefined hidden symbol `_dl_runtime_resolve_fxsave' can not be used when making a shared object
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/usr/local/bin/ld: final link failed: bad value
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For ISA level 3 or above, don't use _dl_runtime_resolve_fxsave nor
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_dl_tlsdesc_dynamic_fxsave.
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This fixes BZ #31429.
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Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
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(cherry picked from commit befe2d3c4dec8be2cdd01a47132e47bdb7020922)
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diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
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index 6fe1b728c607f39e..b8abe733abe54fc4 100644
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--- a/sysdeps/x86/cpu-features.c
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+++ b/sysdeps/x86/cpu-features.c
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@@ -18,6 +18,7 @@
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#include <dl-hwcap.h>
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#include <libc-pointer-arith.h>
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+#include <isa-level.h>
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#include <get-isa-level.h>
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#include <cacheinfo.h>
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#include <dl-cacheinfo.h>
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@@ -1198,7 +1199,9 @@ no_cpuid:
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TUNABLE_CALLBACK (set_x86_shstk));
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#endif
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+#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
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if (GLRO(dl_x86_cpu_features).xsave_state_size != 0)
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+#endif
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{
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if (CPU_FEATURE_USABLE_P (cpu_features, XSAVEC))
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{
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@@ -1219,22 +1222,24 @@ no_cpuid:
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#endif
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}
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}
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+#if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
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else
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{
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-#ifdef __x86_64__
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+# ifdef __x86_64__
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GLRO(dl_x86_64_runtime_resolve) = _dl_runtime_resolve_fxsave;
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-# ifdef SHARED
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+# ifdef SHARED
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GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave;
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-# endif
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-#else
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-# ifdef SHARED
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+# endif
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+# else
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+# ifdef SHARED
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if (CPU_FEATURE_USABLE_P (cpu_features, FXSR))
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GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fxsave;
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else
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GLRO(dl_x86_tlsdesc_dynamic) = _dl_tlsdesc_dynamic_fnsave;
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+# endif
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# endif
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-#endif
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}
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+#endif
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#ifdef SHARED
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# ifdef __x86_64__
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diff --git a/sysdeps/x86_64/dl-tlsdesc.S b/sysdeps/x86_64/dl-tlsdesc.S
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index ea69f5223a77e0c0..057a10862afd6208 100644
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--- a/sysdeps/x86_64/dl-tlsdesc.S
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+++ b/sysdeps/x86_64/dl-tlsdesc.S
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@@ -20,6 +20,7 @@
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#include <tls.h>
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#include <cpu-features-offsets.h>
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#include <features-offsets.h>
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+#include <isa-level.h>
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#include "tlsdesc.h"
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#include "dl-trampoline-save.h"
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@@ -79,12 +80,14 @@ _dl_tlsdesc_undefweak:
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.size _dl_tlsdesc_undefweak, .-_dl_tlsdesc_undefweak
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#ifdef SHARED
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-# define USE_FXSAVE
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-# define STATE_SAVE_ALIGNMENT 16
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-# define _dl_tlsdesc_dynamic _dl_tlsdesc_dynamic_fxsave
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-# include "dl-tlsdesc-dynamic.h"
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-# undef _dl_tlsdesc_dynamic
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-# undef USE_FXSAVE
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+# if MINIMUM_X86_ISA_LEVEL < AVX_X86_ISA_LEVEL
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+# define USE_FXSAVE
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+# define STATE_SAVE_ALIGNMENT 16
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+# define _dl_tlsdesc_dynamic _dl_tlsdesc_dynamic_fxsave
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+# include "dl-tlsdesc-dynamic.h"
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+# undef _dl_tlsdesc_dynamic
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+# undef USE_FXSAVE
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+# endif
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# define USE_XSAVE
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# define STATE_SAVE_ALIGNMENT 64
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