535 lines
16 KiB
Diff
535 lines
16 KiB
Diff
commit a98dc92dd1e278df4c501deb07985018bc2b06de
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Author: mayshao-oc <mayshao-oc@zhaoxin.com>
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Date: Sun Apr 26 13:48:27 2020 +0800
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x86: Add cache information support for Zhaoxin processors
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To obtain Zhaoxin CPU cache information, add a new function
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handle_zhaoxin().
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Add a new function get_common_cache_info() that extracts the code
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in init_cacheinfo() to get the value of the variable shared, threads.
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Add Zhaoxin branch in init_cacheinfo() for initializing variables,
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such as __x86_shared_cache_size.
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diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
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index f1125f30223f5ca3..aa7cb705d546bcd0 100644
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--- a/sysdeps/x86/cacheinfo.c
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+++ b/sysdeps/x86/cacheinfo.c
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@@ -436,6 +436,57 @@ handle_amd (int name)
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}
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+static long int __attribute__ ((noinline))
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+handle_zhaoxin (int name)
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+{
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+ unsigned int eax;
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+ unsigned int ebx;
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+ unsigned int ecx;
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+ unsigned int edx;
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+
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+ int folded_rel_name = (M(name) / 3) * 3;
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+
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+ unsigned int round = 0;
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+ while (1)
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+ {
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+ __cpuid_count (4, round, eax, ebx, ecx, edx);
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+
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+ enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f;
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+ if (type == null)
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+ break;
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+
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+ unsigned int level = (eax >> 5) & 0x7;
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+
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+ if ((level == 1 && type == data
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+ && folded_rel_name == M(_SC_LEVEL1_DCACHE_SIZE))
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+ || (level == 1 && type == inst
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+ && folded_rel_name == M(_SC_LEVEL1_ICACHE_SIZE))
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+ || (level == 2 && folded_rel_name == M(_SC_LEVEL2_CACHE_SIZE))
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+ || (level == 3 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE)))
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+ {
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+ unsigned int offset = M(name) - folded_rel_name;
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+
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+ if (offset == 0)
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+ /* Cache size. */
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+ return (((ebx >> 22) + 1)
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+ * (((ebx >> 12) & 0x3ff) + 1)
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+ * ((ebx & 0xfff) + 1)
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+ * (ecx + 1));
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+ if (offset == 1)
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+ return (ebx >> 22) + 1;
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+
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+ assert (offset == 2);
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+ return (ebx & 0xfff) + 1;
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+ }
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+
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+ ++round;
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+ }
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+
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+ /* Nothing found. */
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+ return 0;
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+}
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+
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+
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/* Get the value of the system variable NAME. */
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long int
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attribute_hidden
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@@ -449,6 +500,9 @@ __cache_sysconf (int name)
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if (cpu_features->basic.kind == arch_kind_amd)
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return handle_amd (name);
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+ if (cpu_features->basic.kind == arch_kind_zhaoxin)
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+ return handle_zhaoxin (name);
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+
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// XXX Fill in more vendors.
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/* CPU not known, we have no information. */
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@@ -482,6 +536,224 @@ int __x86_prefetchw attribute_hidden;
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#endif
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+static void
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+get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr,
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+ long int core)
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+{
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+ unsigned int eax;
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+ unsigned int ebx;
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+ unsigned int ecx;
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+ unsigned int edx;
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+
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+ /* Number of logical processors sharing L2 cache. */
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+ int threads_l2;
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+
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+ /* Number of logical processors sharing L3 cache. */
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+ int threads_l3;
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+
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+ const struct cpu_features *cpu_features = __get_cpu_features ();
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+ int max_cpuid = cpu_features->basic.max_cpuid;
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+ unsigned int family = cpu_features->basic.family;
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+ unsigned int model = cpu_features->basic.model;
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+ long int shared = *shared_ptr;
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+ unsigned int threads = *threads_ptr;
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+ bool inclusive_cache = true;
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+ bool support_count_mask = true;
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+
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+ /* Try L3 first. */
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+ unsigned int level = 3;
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+
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+ if (cpu_features->basic.kind == arch_kind_zhaoxin && family == 6)
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+ support_count_mask = false;
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+
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+ if (shared <= 0)
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+ {
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+ /* Try L2 otherwise. */
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+ level = 2;
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+ shared = core;
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+ threads_l2 = 0;
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+ threads_l3 = -1;
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+ }
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+ else
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+ {
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+ threads_l2 = 0;
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+ threads_l3 = 0;
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+ }
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+
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+ /* A value of 0 for the HTT bit indicates there is only a single
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+ logical processor. */
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+ if (HAS_CPU_FEATURE (HTT))
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+ {
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+ /* Figure out the number of logical threads that share the
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+ highest cache level. */
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+ if (max_cpuid >= 4)
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+ {
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+ int i = 0;
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+
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+ /* Query until cache level 2 and 3 are enumerated. */
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+ int check = 0x1 | (threads_l3 == 0) << 1;
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+ do
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+ {
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+ __cpuid_count (4, i++, eax, ebx, ecx, edx);
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+
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+ /* There seems to be a bug in at least some Pentium Ds
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+ which sometimes fail to iterate all cache parameters.
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+ Do not loop indefinitely here, stop in this case and
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+ assume there is no such information. */
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+ if (cpu_features->basic.kind == arch_kind_intel
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+ && (eax & 0x1f) == 0 )
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+ goto intel_bug_no_cache_info;
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+
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+ switch ((eax >> 5) & 0x7)
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+ {
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+ default:
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+ break;
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+ case 2:
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+ if ((check & 0x1))
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+ {
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+ /* Get maximum number of logical processors
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+ sharing L2 cache. */
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+ threads_l2 = (eax >> 14) & 0x3ff;
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+ check &= ~0x1;
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+ }
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+ break;
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+ case 3:
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+ if ((check & (0x1 << 1)))
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+ {
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+ /* Get maximum number of logical processors
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+ sharing L3 cache. */
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+ threads_l3 = (eax >> 14) & 0x3ff;
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+
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+ /* Check if L2 and L3 caches are inclusive. */
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+ inclusive_cache = (edx & 0x2) != 0;
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+ check &= ~(0x1 << 1);
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+ }
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+ break;
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+ }
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+ }
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+ while (check);
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+
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+ /* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum
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+ numbers of addressable IDs for logical processors sharing
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+ the cache, instead of the maximum number of threads
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+ sharing the cache. */
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+ if (max_cpuid >= 11 && support_count_mask)
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+ {
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+ /* Find the number of logical processors shipped in
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+ one core and apply count mask. */
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+ i = 0;
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+
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+ /* Count SMT only if there is L3 cache. Always count
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+ core if there is no L3 cache. */
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+ int count = ((threads_l2 > 0 && level == 3)
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+ | ((threads_l3 > 0
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+ || (threads_l2 > 0 && level == 2)) << 1));
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+
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+ while (count)
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+ {
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+ __cpuid_count (11, i++, eax, ebx, ecx, edx);
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+
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+ int shipped = ebx & 0xff;
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+ int type = ecx & 0xff00;
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+ if (shipped == 0 || type == 0)
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+ break;
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+ else if (type == 0x100)
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+ {
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+ /* Count SMT. */
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+ if ((count & 0x1))
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+ {
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+ int count_mask;
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+
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+ /* Compute count mask. */
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+ asm ("bsr %1, %0"
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+ : "=r" (count_mask) : "g" (threads_l2));
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+ count_mask = ~(-1 << (count_mask + 1));
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+ threads_l2 = (shipped - 1) & count_mask;
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+ count &= ~0x1;
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+ }
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+ }
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+ else if (type == 0x200)
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+ {
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+ /* Count core. */
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+ if ((count & (0x1 << 1)))
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+ {
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+ int count_mask;
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+ int threads_core
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+ = (level == 2 ? threads_l2 : threads_l3);
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+
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+ /* Compute count mask. */
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+ asm ("bsr %1, %0"
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+ : "=r" (count_mask) : "g" (threads_core));
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+ count_mask = ~(-1 << (count_mask + 1));
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+ threads_core = (shipped - 1) & count_mask;
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+ if (level == 2)
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+ threads_l2 = threads_core;
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+ else
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+ threads_l3 = threads_core;
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+ count &= ~(0x1 << 1);
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+ }
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+ }
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+ }
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+ }
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+ if (threads_l2 > 0)
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+ threads_l2 += 1;
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+ if (threads_l3 > 0)
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+ threads_l3 += 1;
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+ if (level == 2)
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+ {
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+ if (threads_l2)
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+ {
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+ threads = threads_l2;
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+ if (cpu_features->basic.kind == arch_kind_intel
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+ && threads > 2
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+ && family == 6)
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+ switch (model)
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+ {
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+ case 0x37:
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+ case 0x4a:
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+ case 0x4d:
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+ case 0x5a:
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+ case 0x5d:
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+ /* Silvermont has L2 cache shared by 2 cores. */
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+ threads = 2;
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+ break;
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+ default:
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+ break;
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+ }
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+ }
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+ }
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+ else if (threads_l3)
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+ threads = threads_l3;
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+ }
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+ else
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+ {
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+intel_bug_no_cache_info:
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+ /* Assume that all logical threads share the highest cache
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+ level. */
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+ threads
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+ = ((cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx
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+ >> 16) & 0xff);
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+ }
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+
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+ /* Cap usage of highest cache level to the number of supported
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+ threads. */
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+ if (shared > 0 && threads > 0)
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+ shared /= threads;
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+ }
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+
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+ /* Account for non-inclusive L2 and L3 caches. */
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+ if (!inclusive_cache)
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+ {
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+ if (threads_l2 > 0)
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+ core /= threads_l2;
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+ shared += core;
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+ }
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+
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+ *shared_ptr = shared;
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+ *threads_ptr = threads;
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+}
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+
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+
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static void
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__attribute__((constructor))
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init_cacheinfo (void)
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@@ -494,211 +766,25 @@ init_cacheinfo (void)
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int max_cpuid_ex;
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long int data = -1;
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long int shared = -1;
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- unsigned int level;
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+ long int core;
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unsigned int threads = 0;
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const struct cpu_features *cpu_features = __get_cpu_features ();
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- int max_cpuid = cpu_features->basic.max_cpuid;
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if (cpu_features->basic.kind == arch_kind_intel)
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{
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data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features);
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-
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- long int core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features);
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- bool inclusive_cache = true;
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-
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- /* Try L3 first. */
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- level = 3;
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+ core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features);
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shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features);
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- /* Number of logical processors sharing L2 cache. */
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- int threads_l2;
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-
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- /* Number of logical processors sharing L3 cache. */
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- int threads_l3;
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-
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- if (shared <= 0)
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- {
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- /* Try L2 otherwise. */
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- level = 2;
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- shared = core;
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- threads_l2 = 0;
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- threads_l3 = -1;
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- }
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- else
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- {
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- threads_l2 = 0;
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- threads_l3 = 0;
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- }
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-
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- /* A value of 0 for the HTT bit indicates there is only a single
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- logical processor. */
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- if (HAS_CPU_FEATURE (HTT))
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- {
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- /* Figure out the number of logical threads that share the
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- highest cache level. */
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- if (max_cpuid >= 4)
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- {
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- unsigned int family = cpu_features->basic.family;
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- unsigned int model = cpu_features->basic.model;
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-
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- int i = 0;
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-
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- /* Query until cache level 2 and 3 are enumerated. */
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- int check = 0x1 | (threads_l3 == 0) << 1;
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- do
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- {
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- __cpuid_count (4, i++, eax, ebx, ecx, edx);
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-
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- /* There seems to be a bug in at least some Pentium Ds
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- which sometimes fail to iterate all cache parameters.
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- Do not loop indefinitely here, stop in this case and
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- assume there is no such information. */
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- if ((eax & 0x1f) == 0)
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- goto intel_bug_no_cache_info;
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-
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- switch ((eax >> 5) & 0x7)
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- {
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- default:
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- break;
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- case 2:
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- if ((check & 0x1))
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- {
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- /* Get maximum number of logical processors
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- sharing L2 cache. */
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- threads_l2 = (eax >> 14) & 0x3ff;
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- check &= ~0x1;
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- }
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- break;
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- case 3:
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- if ((check & (0x1 << 1)))
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- {
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- /* Get maximum number of logical processors
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- sharing L3 cache. */
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- threads_l3 = (eax >> 14) & 0x3ff;
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-
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- /* Check if L2 and L3 caches are inclusive. */
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- inclusive_cache = (edx & 0x2) != 0;
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- check &= ~(0x1 << 1);
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- }
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- break;
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- }
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- }
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- while (check);
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-
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- /* If max_cpuid >= 11, THREADS_L2/THREADS_L3 are the maximum
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- numbers of addressable IDs for logical processors sharing
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- the cache, instead of the maximum number of threads
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- sharing the cache. */
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- if (max_cpuid >= 11)
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- {
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- /* Find the number of logical processors shipped in
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- one core and apply count mask. */
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- i = 0;
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-
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- /* Count SMT only if there is L3 cache. Always count
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- core if there is no L3 cache. */
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- int count = ((threads_l2 > 0 && level == 3)
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- | ((threads_l3 > 0
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- || (threads_l2 > 0 && level == 2)) << 1));
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-
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- while (count)
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- {
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- __cpuid_count (11, i++, eax, ebx, ecx, edx);
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-
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- int shipped = ebx & 0xff;
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- int type = ecx & 0xff00;
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- if (shipped == 0 || type == 0)
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- break;
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- else if (type == 0x100)
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- {
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- /* Count SMT. */
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- if ((count & 0x1))
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- {
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- int count_mask;
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-
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- /* Compute count mask. */
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- asm ("bsr %1, %0"
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- : "=r" (count_mask) : "g" (threads_l2));
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- count_mask = ~(-1 << (count_mask + 1));
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- threads_l2 = (shipped - 1) & count_mask;
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- count &= ~0x1;
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- }
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- }
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- else if (type == 0x200)
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- {
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- /* Count core. */
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- if ((count & (0x1 << 1)))
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- {
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- int count_mask;
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- int threads_core
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- = (level == 2 ? threads_l2 : threads_l3);
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-
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- /* Compute count mask. */
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- asm ("bsr %1, %0"
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- : "=r" (count_mask) : "g" (threads_core));
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- count_mask = ~(-1 << (count_mask + 1));
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- threads_core = (shipped - 1) & count_mask;
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- if (level == 2)
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- threads_l2 = threads_core;
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- else
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- threads_l3 = threads_core;
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- count &= ~(0x1 << 1);
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- }
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- }
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- }
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- }
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- if (threads_l2 > 0)
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- threads_l2 += 1;
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- if (threads_l3 > 0)
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- threads_l3 += 1;
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- if (level == 2)
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- {
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- if (threads_l2)
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- {
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- threads = threads_l2;
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- if (threads > 2 && family == 6)
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- switch (model)
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- {
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- case 0x37:
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- case 0x4a:
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- case 0x4d:
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- case 0x5a:
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- case 0x5d:
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- /* Silvermont has L2 cache shared by 2 cores. */
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- threads = 2;
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- break;
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- default:
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- break;
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- }
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- }
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- }
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- else if (threads_l3)
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- threads = threads_l3;
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- }
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- else
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- {
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-intel_bug_no_cache_info:
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- /* Assume that all logical threads share the highest cache
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- level. */
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-
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- threads
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- = ((cpu_features->cpuid[COMMON_CPUID_INDEX_1].ebx
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- >> 16) & 0xff);
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- }
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-
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- /* Cap usage of highest cache level to the number of supported
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- threads. */
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- if (shared > 0 && threads > 0)
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- shared /= threads;
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- }
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+ get_common_cache_info (&shared, &threads, core);
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+ }
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+ else if (cpu_features->basic.kind == arch_kind_zhaoxin)
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+ {
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+ data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE);
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+ core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE);
|
|
+ shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE);
|
|
|
|
- /* Account for non-inclusive L2 and L3 caches. */
|
|
- if (!inclusive_cache)
|
|
- {
|
|
- if (threads_l2 > 0)
|
|
- core /= threads_l2;
|
|
- shared += core;
|
|
- }
|
|
+ get_common_cache_info (&shared, &threads, core);
|
|
}
|
|
else if (cpu_features->basic.kind == arch_kind_amd)
|
|
{
|