70ebc1f0c6
Upstream commit: cff1042cceec3502269947e96cf7023451af22f3 Resolves: RHEL-87416 Resolves: RHEL-71923 Resolves: RHEL-82285 Resolves: RHEL-82286 Resolves: RHEL-84837 Resolves: RHEL-86433 Resolves: RHEL-95485
48 lines
1.6 KiB
Diff
48 lines
1.6 KiB
Diff
commit 60cd7123a6c4441a509c22cc1d5da60df2c1dfeb
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Author: Florian Weimer <fweimer@redhat.com>
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Date: Fri Mar 28 09:26:06 2025 +0100
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x86: Skip XSAVE state size reset if ISA level requires XSAVE
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If we have to use XSAVE or XSAVEC trampolines, do not adjust the size
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information they need. Technically, it is an operator error to try to
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run with -XSAVE,-XSAVEC on such builds, but this change here disables
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some unnecessary code with higher ISA levels and simplifies testing.
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Related to commit befe2d3c4dec8be2cdd01a47132e47bdb7020922
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("x86-64: Don't use SSE resolvers for ISA level 3 or above").
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Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
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(cherry picked from commit 59585ddaa2d44f22af04bb4b8bd4ad1e302c4c02)
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diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
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index 3d7c2819d7cc6643..4c535970d10a2d67 100644
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--- a/sysdeps/x86/cpu-features.c
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+++ b/sysdeps/x86/cpu-features.c
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@@ -24,6 +24,7 @@
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#include <dl-cacheinfo.h>
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#include <dl-minsigstacksize.h>
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#include <dl-hwcap2.h>
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+#include <gcc-macros.h>
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extern void TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *)
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attribute_hidden;
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@@ -1092,6 +1093,9 @@ no_cpuid:
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TUNABLE_CALLBACK (set_prefer_map_32bit_exec));
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#endif
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+ /* Do not add the logic to disable XSAVE/XSAVEC if this glibc build
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+ requires AVX and therefore XSAVE or XSAVEC support. */
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+#ifndef GCCMACRO__AVX__
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bool disable_xsave_features = false;
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if (!CPU_FEATURE_USABLE_P (cpu_features, OSXSAVE))
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@@ -1145,6 +1149,7 @@ no_cpuid:
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CPU_FEATURE_UNSET (cpu_features, FMA4);
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}
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+#endif
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#ifdef __x86_64__
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GLRO(dl_hwcap) = HWCAP_X86_64;
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