glibc/glibc-upstream-2.34-268.patch
Florian Weimer 5f265ff1c6 Import glibc-2.34-37.fc35 from f35
* Wed Jun  8 2022 Florian Weimer <fweimer@redhat.com> - 2.34-37
- Enable rseq by default and add GLIBC_2.35 rseq symbols (#2085529)

* Wed Jun  8 2022 Florian Weimer <fweimer@redhat.com> - 2.34-36
- Sync with upstream branch release/2.34/master,
  commit 4c92a1041257c0155c6aa7a182fe5f78e477b0e6:
- powerpc: Fix VSX register number on __strncpy_power9 [BZ #29197]
- socket: Fix mistyped define statement in socket/sys/socket.h (BZ #29225)
- iconv: Use 64 bit stat for gconv_parseconfdir (BZ# 29213)
- catgets: Use 64 bit stat for __open_catalog (BZ# 29211)
- inet: Use 64 bit stat for ruserpass (BZ# 29210)
- socket: Use 64 bit stat for isfdtype (BZ# 29209)
- posix: Use 64 bit stat for fpathconf (_PC_ASYNC_IO) (BZ# 29208)
- posix: Use 64 bit stat for posix_fallocate fallback (BZ# 29207)
- misc: Use 64 bit stat for getusershell (BZ# 29204)
- misc: Use 64 bit stat for daemon (BZ# 29203)

Resolves: #2085529
Resolves: #2091549
Related: #2091541
2022-06-08 17:01:17 +02:00

43 lines
1.5 KiB
Diff

commit 4c92a1041257c0155c6aa7a182fe5f78e477b0e6
Author: Matheus Castanho <msc@linux.ibm.com>
Date: Tue Jun 7 10:27:26 2022 -0300
powerpc: Fix VSX register number on __strncpy_power9 [BZ #29197]
__strncpy_power9 initializes VR 18 with zeroes to be used throughout the
code, including when zero-padding the destination string. However, the
v18 reference was mistakenly being used for stxv and stxvl, which take a
VSX vector as operand. The code ended up using the uninitialized VSR 18
register by mistake.
Both occurrences have been changed to use the proper VSX number for VR 18
(i.e. VSR 50).
Tested on powerpc, powerpc64 and powerpc64le.
Signed-off-by: Kewen Lin <linkw@gcc.gnu.org>
(cherry picked from commit 0218463dd8265ed937622f88ac68c7d984fe0cfc)
diff --git a/sysdeps/powerpc/powerpc64/le/power9/strncpy.S b/sysdeps/powerpc/powerpc64/le/power9/strncpy.S
index 291941c1e5c0eb4b..5421525acee3ebfe 100644
--- a/sysdeps/powerpc/powerpc64/le/power9/strncpy.S
+++ b/sysdeps/powerpc/powerpc64/le/power9/strncpy.S
@@ -352,7 +352,7 @@ L(zero_padding_loop):
cmpldi cr6,r5,16 /* Check if length was reached. */
ble cr6,L(zero_padding_end)
- stxv v18,0(r11)
+ stxv 32+v18,0(r11)
addi r11,r11,16
addi r5,r5,-16
@@ -360,7 +360,7 @@ L(zero_padding_loop):
L(zero_padding_end):
sldi r10,r5,56 /* stxvl wants size in top 8 bits */
- stxvl v18,r11,r10 /* Partial store */
+ stxvl 32+v18,r11,r10 /* Partial store */
blr
.align 4