217 lines
8.8 KiB
Diff
217 lines
8.8 KiB
Diff
From af992e7abdc9049714da76cae1e5e18bc4838fb8 Mon Sep 17 00:00:00 2001
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From: Noah Goldstein <goldstein.w.n@gmail.com>
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Date: Wed, 7 Jun 2023 13:18:01 -0500
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Subject: [PATCH] x86: Increase `non_temporal_threshold` to roughly `sizeof_L3
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/ 4`
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Content-type: text/plain; charset=UTF-8
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Current `non_temporal_threshold` set to roughly '3/4 * sizeof_L3 /
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ncores_per_socket'. This patch updates that value to roughly
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'sizeof_L3 / 4`
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The original value (specifically dividing the `ncores_per_socket`) was
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done to limit the amount of other threads' data a `memcpy`/`memset`
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could evict.
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Dividing by 'ncores_per_socket', however leads to exceedingly low
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non-temporal thresholds and leads to using non-temporal stores in
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cases where REP MOVSB is multiple times faster.
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Furthermore, non-temporal stores are written directly to main memory
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so using it at a size much smaller than L3 can place soon to be
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accessed data much further away than it otherwise could be. As well,
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modern machines are able to detect streaming patterns (especially if
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REP MOVSB is used) and provide LRU hints to the memory subsystem. This
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in affect caps the total amount of eviction at 1/cache_associativity,
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far below meaningfully thrashing the entire cache.
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As best I can tell, the benchmarks that lead this small threshold
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where done comparing non-temporal stores versus standard cacheable
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stores. A better comparison (linked below) is to be REP MOVSB which,
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on the measure systems, is nearly 2x faster than non-temporal stores
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at the low-end of the previous threshold, and within 10% for over
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100MB copies (well past even the current threshold). In cases with a
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low number of threads competing for bandwidth, REP MOVSB is ~2x faster
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up to `sizeof_L3`.
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The divisor of `4` is a somewhat arbitrary value. From benchmarks it
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seems Skylake and Icelake both prefer a divisor of `2`, but older CPUs
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such as Broadwell prefer something closer to `8`. This patch is meant
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to be followed up by another one to make the divisor cpu-specific, but
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in the meantime (and for easier backporting), this patch settles on
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`4` as a middle-ground.
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Benchmarks comparing non-temporal stores, REP MOVSB, and cacheable
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stores where done using:
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https://github.com/goldsteinn/memcpy-nt-benchmarks
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Sheets results (also available in pdf on the github):
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https://docs.google.com/spreadsheets/d/e/2PACX-1vS183r0rW_jRX6tG_E90m9qVuFiMbRIJvi5VAE8yYOvEOIEEc3aSNuEsrFbuXw5c3nGboxMmrupZD7K/pubhtml
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Reviewed-by: DJ Delorie <dj@redhat.com>
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Reviewed-by: Carlos O'Donell <carlos@redhat.com>
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---
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sysdeps/x86/dl-cacheinfo.h | 70 +++++++++++++++++++++++---------------
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1 file changed, 43 insertions(+), 27 deletions(-)
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[DJ - ported to C8S]
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diff -rup a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h
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--- a/sysdeps/x86/cacheinfo.h 2023-08-08 11:54:09.969791421 -0400
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+++ b/sysdeps/x86/cacheinfo.h 2023-08-08 13:44:55.185333601 -0400
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@@ -46,7 +46,7 @@ long int __x86_rep_movsb_threshold attri
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long int __x86_rep_stosb_threshold attribute_hidden = 2048;
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static void
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-get_common_cache_info (long int *shared_ptr, unsigned int *threads_ptr,
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+get_common_cache_info (long int *shared_ptr, long int * shared_per_thread_ptr, unsigned int *threads_ptr,
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long int core)
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{
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unsigned int eax;
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@@ -65,6 +65,7 @@ get_common_cache_info (long int *shared_
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unsigned int family = cpu_features->basic.family;
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unsigned int model = cpu_features->basic.model;
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long int shared = *shared_ptr;
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+ long int shared_per_thread = *shared_per_thread_ptr;
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unsigned int threads = *threads_ptr;
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bool inclusive_cache = true;
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bool support_count_mask = true;
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@@ -80,6 +81,7 @@ get_common_cache_info (long int *shared_
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/* Try L2 otherwise. */
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level = 2;
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shared = core;
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+ shared_per_thread = core;
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threads_l2 = 0;
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threads_l3 = -1;
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}
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@@ -236,29 +238,28 @@ get_common_cache_info (long int *shared_
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}
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else
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{
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-intel_bug_no_cache_info:
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- /* Assume that all logical threads share the highest cache
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- level. */
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- threads
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- = ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx
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- >> 16) & 0xff);
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- }
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-
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- /* Cap usage of highest cache level to the number of supported
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- threads. */
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- if (shared > 0 && threads > 0)
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- shared /= threads;
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+ intel_bug_no_cache_info:
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+ /* Assume that all logical threads share the highest cache
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+ level. */
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+ threads = ((cpu_features->features[COMMON_CPUID_INDEX_1].cpuid.ebx >> 16)
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+ & 0xff);
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+
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+ /* Get per-thread size of highest level cache. */
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+ if (shared_per_thread > 0 && threads > 0)
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+ shared_per_thread /= threads;
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+ }
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}
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/* Account for non-inclusive L2 and L3 caches. */
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if (!inclusive_cache)
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{
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if (threads_l2 > 0)
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- core /= threads_l2;
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+ shared_per_thread += core / threads_l2;
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shared += core;
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}
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*shared_ptr = shared;
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+ *shared_per_thread_ptr = shared_per_thread;
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*threads_ptr = threads;
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}
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@@ -272,6 +273,7 @@ init_cacheinfo (void)
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int max_cpuid_ex;
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long int data = -1;
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long int shared = -1;
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+ long int shared_per_thread = -1;
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long int core;
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unsigned int threads = 0;
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const struct cpu_features *cpu_features = __get_cpu_features ();
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@@ -287,22 +289,25 @@ init_cacheinfo (void)
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data = handle_intel (_SC_LEVEL1_DCACHE_SIZE, cpu_features);
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core = handle_intel (_SC_LEVEL2_CACHE_SIZE, cpu_features);
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shared = handle_intel (_SC_LEVEL3_CACHE_SIZE, cpu_features);
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+ shared_per_thread = shared;
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- get_common_cache_info (&shared, &threads, core);
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+ get_common_cache_info (&shared, &shared_per_thread, &threads, core);
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}
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else if (cpu_features->basic.kind == arch_kind_zhaoxin)
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{
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data = handle_zhaoxin (_SC_LEVEL1_DCACHE_SIZE);
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core = handle_zhaoxin (_SC_LEVEL2_CACHE_SIZE);
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shared = handle_zhaoxin (_SC_LEVEL3_CACHE_SIZE);
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+ shared_per_thread = shared;
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- get_common_cache_info (&shared, &threads, core);
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+ get_common_cache_info (&shared, &shared_per_thread, &threads, core);
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}
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else if (cpu_features->basic.kind == arch_kind_amd)
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{
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data = handle_amd (_SC_LEVEL1_DCACHE_SIZE);
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long int core = handle_amd (_SC_LEVEL2_CACHE_SIZE);
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shared = handle_amd (_SC_LEVEL3_CACHE_SIZE);
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+ shared_per_thread = shared;
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/* Get maximum extended function. */
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__cpuid (0x80000000, max_cpuid_ex, ebx, ecx, edx);
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@@ -352,6 +357,9 @@ init_cacheinfo (void)
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shared += core;
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}
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}
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+
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+ if (shared_per_thread <= 0)
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+ shared_per_thread = shared;
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}
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if (cpu_features->data_cache_size != 0)
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@@ -380,20 +388,30 @@ init_cacheinfo (void)
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__x86_shared_cache_size = shared;
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}
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- /* The default setting for the non_temporal threshold is 3/4 of one
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- thread's share of the chip's cache. For most Intel and AMD processors
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- with an initial release date between 2017 and 2020, a thread's typical
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- share of the cache is from 500 KBytes to 2 MBytes. Using the 3/4
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- threshold leaves 125 KBytes to 500 KBytes of the thread's data
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- in cache after a maximum temporal copy, which will maintain
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- in cache a reasonable portion of the thread's stack and other
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- active data. If the threshold is set higher than one thread's
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- share of the cache, it has a substantial risk of negatively
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- impacting the performance of other threads running on the chip. */
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+ /* The default setting for the non_temporal threshold is 1/4 of size
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+ of the chip's cache. For most Intel and AMD processors with an
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+ initial release date between 2017 and 2023, a thread's typical
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+ share of the cache is from 18-64MB. Using the 1/4 L3 is meant to
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+ estimate the point where non-temporal stores begin out-competing
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+ REP MOVSB. As well the point where the fact that non-temporal
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+ stores are forced back to main memory would already occurred to the
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+ majority of the lines in the copy. Note, concerns about the
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+ entire L3 cache being evicted by the copy are mostly alleviated
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+ by the fact that modern HW detects streaming patterns and
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+ provides proper LRU hints so that the maximum thrashing
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+ capped at 1/associativity. */
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+ unsigned long int non_temporal_threshold = shared / 4;
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+ /* If no ERMS, we use the per-thread L3 chunking. Normal cacheable stores run
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+ a higher risk of actually thrashing the cache as they don't have a HW LRU
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+ hint. As well, their performance in highly parallel situations is
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+ noticeably worse. */
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+ if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS))
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+ non_temporal_threshold = shared_per_thread * 3 / 4;
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+
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__x86_shared_non_temporal_threshold
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= (cpu_features->non_temporal_threshold != 0
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? cpu_features->non_temporal_threshold
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- : __x86_shared_cache_size * 3 / 4);
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+ : non_temporal_threshold);
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/* NB: The REP MOVSB threshold must be greater than VEC_SIZE * 8. */
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unsigned int minimum_rep_movsb_threshold;
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Only in b/sysdeps/x86: cacheinfo.h~
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