101 lines
3.5 KiB
Diff
101 lines
3.5 KiB
Diff
Backport the sysdeps/x86/isa-level.h changes from:
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commit ceabdcd130ca7043b0fcf2676183d79431d10493
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Author: Noah Goldstein <goldstein.w.n@gmail.com>
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Date: Wed Jul 13 16:32:59 2022 -0700
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x86: Add support to build strcmp/strlen/strchr with explicit ISA level
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1. Add default ISA level selection in non-multiarch/rtld
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implementations.
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2. Add ISA level build guards to different implementations.
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- I.e strcmp-avx2.S which is ISA level 3 will only build if
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compiled ISA level <= 3. Otherwise there is no reason to
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include it as we will always use one of the ISA level 4
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implementations (strcmp-evex.S).
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3. Refactor the ifunc selector and ifunc implementation list to use
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the ISA level aware wrapper macros that allow functions below the
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compiled ISA level (with a guranteed replacement) to be skipped.
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Tested with and without multiarch on x86_64 for ISA levels:
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{generic, x86-64-v2, x86-64-v3, x86-64-v4}
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And m32 with and without multiarch.
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Conflicts:
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support/xpthread_cond_signal.c
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sysdeps/x86_64/memrchr.S
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sysdeps/x86_64/multiarch/Makefile
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sysdeps/x86_64/multiarch/ifunc-avx2.h
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sysdeps/x86_64/multiarch/ifunc-impl-list.c
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sysdeps/x86_64/multiarch/ifunc-strcasecmp.h
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sysdeps/x86_64/multiarch/ifunc-wcslen.h
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sysdeps/x86_64/multiarch/memrchr-sse2.S
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sysdeps/x86_64/multiarch/strcasecmp_l-sse2.S
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sysdeps/x86_64/multiarch/strchr-sse2.S
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sysdeps/x86_64/multiarch/strchrnul-sse2.S
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sysdeps/x86_64/multiarch/strcmp-avx2.S
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sysdeps/x86_64/multiarch/strcmp-evex.S
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sysdeps/x86_64/multiarch/strcmp-sse2.S
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sysdeps/x86_64/multiarch/strcmp-sse4_2.S
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sysdeps/x86_64/multiarch/strcmp.c
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sysdeps/x86_64/multiarch/strlen-sse2.S
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sysdeps/x86_64/multiarch/strncmp.c
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sysdeps/x86_64/multiarch/strnlen-sse2.S
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sysdeps/x86_64/multiarch/strrchr-sse2.S
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sysdeps/x86_64/multiarch/wcschr-sse2.S
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sysdeps/x86_64/multiarch/wcscmp-sse2.S
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sysdeps/x86_64/multiarch/wcslen-sse2.S
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sysdeps/x86_64/multiarch/wcslen-sse4_1.S
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sysdeps/x86_64/multiarch/wcsncmp-sse2.c
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sysdeps/x86_64/multiarch/wcsnlen-sse4_1.S
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sysdeps/x86_64/multiarch/wcsrchr-sse2.S
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sysdeps/x86_64/strcasecmp_l.S
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sysdeps/x86_64/strchr.S
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sysdeps/x86_64/strchrnul.S
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sysdeps/x86_64/strcmp.S
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sysdeps/x86_64/strlen.S
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sysdeps/x86_64/strncase_l.S
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sysdeps/x86_64/strncmp.S
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sysdeps/x86_64/strnlen.S
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sysdeps/x86_64/strrchr.S
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sysdeps/x86_64/wcschr.S
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sysdeps/x86_64/wcscmp.S
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sysdeps/x86_64/wcslen.S
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sysdeps/x86_64/wcsrchr.S
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(no backport of string function changes)
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diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
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index 77f9e2c0c3ccd41d..3c4480aba70193a2 100644
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--- a/sysdeps/x86/isa-level.h
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+++ b/sysdeps/x86/isa-level.h
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@@ -84,6 +84,7 @@
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/* ISA level >= 2 guaranteed includes. */
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#define SSE4_2_X86_ISA_LEVEL 2
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+#define SSE4_1_X86_ISA_LEVEL 2
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#define SSSE3_X86_ISA_LEVEL 2
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@@ -101,9 +102,18 @@
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when ISA level < 3. */
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#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
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+/* NB: This feature is disable when ISA level >= 3. All CPUs with
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+ this feature don't run on glibc built with ISA level >= 3. */
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+#define Slow_SSE42_X86_ISA_LEVEL 3
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+
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/* Feature(s) enabled when ISA level >= 2. */
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#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
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+/* NB: This feature is disable when ISA level >= 2, which was enabled
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+ for the early Atom CPUs. */
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+#define Slow_BSF_X86_ISA_LEVEL 2
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+
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+
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/* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
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macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
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runtime checks. They differ in two ways.
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