52 lines
1.6 KiB
Diff
52 lines
1.6 KiB
Diff
commit a3563f3f369878467dd74aeb360448119a7a4b41
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Author: Noah Goldstein <goldstein.w.n@gmail.com>
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Date: Mon Jun 27 21:07:03 2022 -0700
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x86: Add more feature definitions to isa-level.h
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This commit doesn't change anything in itself. It is just to add
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definitions that will be needed by future patches.
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diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
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index f293aea9068cc2a9..77f9e2c0c3ccd41d 100644
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--- a/sysdeps/x86/isa-level.h
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+++ b/sysdeps/x86/isa-level.h
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@@ -67,15 +67,27 @@
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/* Depending on the minimum ISA level, a feature check result can be a
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compile-time constant.. */
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+
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+/* For CPU_FEATURE_USABLE_P. */
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+
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/* ISA level >= 4 guaranteed includes. */
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#define AVX512F_X86_ISA_LEVEL 4
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#define AVX512VL_X86_ISA_LEVEL 4
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#define AVX512BW_X86_ISA_LEVEL 4
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+#define AVX512DQ_X86_ISA_LEVEL 4
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/* ISA level >= 3 guaranteed includes. */
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#define AVX_X86_ISA_LEVEL 3
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#define AVX2_X86_ISA_LEVEL 3
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#define BMI2_X86_ISA_LEVEL 3
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+#define MOVBE_X86_ISA_LEVEL 3
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+
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+/* ISA level >= 2 guaranteed includes. */
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+#define SSE4_2_X86_ISA_LEVEL 2
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+#define SSSE3_X86_ISA_LEVEL 2
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+
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+
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+/* For X86_ISA_CPU_FEATURES_ARCH_P. */
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/* NB: This feature is enabled when ISA level >= 3, which was disabled
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for the following CPUs:
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@@ -89,6 +101,9 @@
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when ISA level < 3. */
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#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
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+/* Feature(s) enabled when ISA level >= 2. */
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+#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
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+
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/* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
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macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
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runtime checks. They differ in two ways.
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